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add stm32 libs

balbekova 8 anos atrás
pai
25de8a1c72
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72 arquivos alterados com 49986 adições e 0 exclusões
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  1. 952 0
      stm32/stm32f4x7_ethernet/Release_Notes.html
  2. 2719 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth.c
  3. 1902 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth.h
  4. 236 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth_bsp.c
  5. 68 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth_bsp.h
  6. 113 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth_conf.h
  7. 92 0
      stm32/stm32f4x7_ethernet/stm32f4x7_eth_conf_template.h
  8. 928 0
      stm32/stm32f4xx_spl/Release_Notes.html
  9. 178 0
      stm32/stm32f4xx_spl/inc/misc.h
  10. 649 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_adc.h
  11. 644 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_can.h
  12. 83 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_crc.h
  13. 344 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_cryp.h
  14. 304 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_dac.h
  15. 109 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_dbgmcu.h
  16. 312 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_dcmi.h
  17. 609 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_dma.h
  18. 183 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_exti.h
  19. 340 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_flash.h
  20. 675 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_fsmc.h
  21. 412 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_gpio.h
  22. 250 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_hash.h
  23. 698 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_i2c.h
  24. 131 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_iwdg.h
  25. 185 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_pwr.h
  26. 516 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_rcc.h
  27. 120 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_rng.h
  28. 881 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_rtc.h
  29. 536 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_sdio.h
  30. 543 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_spi.h
  31. 179 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_syscfg.h
  32. 1150 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_tim.h
  33. 429 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_usart.h
  34. 111 0
      stm32/stm32f4xx_spl/inc/stm32f4xx_wwdg.h
  35. 249 0
      stm32/stm32f4xx_spl/src/misc.c
  36. 1748 0
      stm32/stm32f4xx_spl/src/stm32f4xx_adc.c
  37. 1704 0
      stm32/stm32f4xx_spl/src/stm32f4xx_can.c
  38. 133 0
      stm32/stm32f4xx_spl/src/stm32f4xx_crc.c
  39. 856 0
      stm32/stm32f4xx_spl/src/stm32f4xx_cryp.c
  40. 644 0
      stm32/stm32f4xx_spl/src/stm32f4xx_cryp_aes.c
  41. 297 0
      stm32/stm32f4xx_spl/src/stm32f4xx_cryp_des.c
  42. 314 0
      stm32/stm32f4xx_spl/src/stm32f4xx_cryp_tdes.c
  43. 707 0
      stm32/stm32f4xx_spl/src/stm32f4xx_dac.c
  44. 180 0
      stm32/stm32f4xx_spl/src/stm32f4xx_dbgmcu.c
  45. 540 0
      stm32/stm32f4xx_spl/src/stm32f4xx_dcmi.c
  46. 1289 0
      stm32/stm32f4xx_spl/src/stm32f4xx_dma.c
  47. 312 0
      stm32/stm32f4xx_spl/src/stm32f4xx_exti.c
  48. 1062 0
      stm32/stm32f4xx_spl/src/stm32f4xx_flash.c
  49. 987 0
      stm32/stm32f4xx_spl/src/stm32f4xx_fsmc.c
  50. 567 0
      stm32/stm32f4xx_spl/src/stm32f4xx_gpio.c
  51. 706 0
      stm32/stm32f4xx_spl/src/stm32f4xx_hash.c
  52. 320 0
      stm32/stm32f4xx_spl/src/stm32f4xx_hash_md5.c
  53. 323 0
      stm32/stm32f4xx_spl/src/stm32f4xx_hash_sha1.c
  54. 1401 0
      stm32/stm32f4xx_spl/src/stm32f4xx_i2c.c
  55. 269 0
      stm32/stm32f4xx_spl/src/stm32f4xx_iwdg.c
  56. 664 0
      stm32/stm32f4xx_spl/src/stm32f4xx_pwr.c
  57. 1814 0
      stm32/stm32f4xx_spl/src/stm32f4xx_rcc.c
  58. 405 0
      stm32/stm32f4xx_spl/src/stm32f4xx_rng.c
  59. 2759 0
      stm32/stm32f4xx_spl/src/stm32f4xx_rtc.c
  60. 1010 0
      stm32/stm32f4xx_spl/src/stm32f4xx_sdio.c
  61. 1292 0
      stm32/stm32f4xx_spl/src/stm32f4xx_spi.c
  62. 203 0
      stm32/stm32f4xx_spl/src/stm32f4xx_syscfg.c
  63. 3358 0
      stm32/stm32f4xx_spl/src/stm32f4xx_tim.c
  64. 1469 0
      stm32/stm32f4xx_spl/src/stm32f4xx_usart.c
  65. 309 0
      stm32/stm32f4xx_spl/src/stm32f4xx_wwdg.c
  66. 53 0
      stm32/system/core_cm4.c
  67. 1803 0
      stm32/system/core_cm4.h
  68. 640 0
      stm32/system/core_cmFunc.h
  69. 886 0
      stm32/system/core_cmInstr.h
  70. 697 0
      stm32/system/core_cmSimd.h
  71. 134 0
      stm32/system/stm32f4xx_conf.h
  72. 301 0
      stm32/system/syscalls/syscalls.c

+ 952 - 0
stm32/stm32f4x7_ethernet/Release_Notes.html
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+	mso-font-charset:0;
 
+	mso-generic-font-family:swiss;
 
+	mso-font-pitch:variable;
 
+	mso-font-signature:1627400839 -2147483648 8 0 66047 0;}
 
+@font-face
 
+	{font-family:Verdana;
 
+	panose-1:2 11 6 4 3 5 4 4 2 4;
 
+	mso-font-charset:0;
 
+	mso-generic-font-family:swiss;
 
+	mso-font-pitch:variable;
 
+	mso-font-signature:536871559 0 0 0 415 0;}
 
+ /* Style Definitions */
 
+ p.MsoNormal, li.MsoNormal, div.MsoNormal
 
+	{mso-style-unhide:no;
 
+	mso-style-qformat:yes;
 
+	mso-style-parent:"";
 
+	margin:0in;
 
+	margin-bottom:.0001pt;
 
+	mso-pagination:widow-orphan;
 
+	font-size:12.0pt;
 
+	font-family:"Times New Roman","serif";
 
+	mso-fareast-font-family:"Times New Roman";}
 
+h1
 
+	{mso-style-unhide:no;
 
+	mso-style-qformat:yes;
 
+	mso-style-link:"Heading 1 Char";
 
+	mso-margin-top-alt:auto;
 
+	margin-right:0in;
 
+	mso-margin-bottom-alt:auto;
 
+	margin-left:0in;
 
+	mso-pagination:widow-orphan;
 
+	mso-outline-level:1;
 
+	font-size:24.0pt;
 
+	font-family:"Times New Roman","serif";
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:minor-fareast;
 
+	font-weight:bold;}
 
+h2
 
+	{mso-style-unhide:no;
 
+	mso-style-qformat:yes;
 
+	mso-style-link:"Heading 2 Char";
 
+	mso-style-next:Normal;
 
+	margin-top:12.0pt;
 
+	margin-right:0in;
 
+	margin-bottom:3.0pt;
 
+	margin-left:0in;
 
+	mso-pagination:widow-orphan;
 
+	page-break-after:avoid;
 
+	mso-outline-level:2;
 
+	font-size:14.0pt;
 
+	font-family:"Arial","sans-serif";
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:minor-fareast;
 
+	font-weight:bold;
 
+	font-style:italic;}
 
+h3
 
+	{mso-style-unhide:no;
 
+	mso-style-qformat:yes;
 
+	mso-style-link:"Heading 3 Char";
 
+	mso-margin-top-alt:auto;
 
+	margin-right:0in;
 
+	mso-margin-bottom-alt:auto;
 
+	margin-left:0in;
 
+	mso-pagination:widow-orphan;
 
+	mso-outline-level:3;
 
+	font-size:13.5pt;
 
+	font-family:"Times New Roman","serif";
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:minor-fareast;
 
+	font-weight:bold;}
 
+a:link, span.MsoHyperlink
 
+	{mso-style-unhide:no;
 
+	color:blue;
 
+	text-decoration:underline;
 
+	text-underline:single;}
 
+a:visited, span.MsoHyperlinkFollowed
 
+	{mso-style-unhide:no;
 
+	color:blue;
 
+	text-decoration:underline;
 
+	text-underline:single;}
 
+p
 
+	{mso-style-unhide:no;
 
+	mso-margin-top-alt:auto;
 
+	margin-right:0in;
 
+	mso-margin-bottom-alt:auto;
 
+	margin-left:0in;
 
+	mso-pagination:widow-orphan;
 
+	font-size:12.0pt;
 
+	font-family:"Times New Roman","serif";
 
+	mso-fareast-font-family:"Times New Roman";}
 
+p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
 
+	{mso-style-unhide:no;
 
+	mso-style-link:"Balloon Text Char";
 
+	margin:0in;
 
+	margin-bottom:.0001pt;
 
+	mso-pagination:widow-orphan;
 
+	font-size:8.0pt;
 
+	font-family:"Tahoma","sans-serif";
 
+	mso-fareast-font-family:"Times New Roman";}
 
+span.Heading1Char
 
+	{mso-style-name:"Heading 1 Char";
 
+	mso-style-unhide:no;
 
+	mso-style-locked:yes;
 
+	mso-style-link:"Heading 1";
 
+	mso-ansi-font-size:14.0pt;
 
+	mso-bidi-font-size:14.0pt;
 
+	font-family:"Cambria","serif";
 
+	mso-ascii-font-family:Cambria;
 
+	mso-ascii-theme-font:major-latin;
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:major-fareast;
 
+	mso-hansi-font-family:Cambria;
 
+	mso-hansi-theme-font:major-latin;
 
+	mso-bidi-font-family:"Times New Roman";
 
+	mso-bidi-theme-font:major-bidi;
 
+	color:#365F91;
 
+	mso-themecolor:accent1;
 
+	mso-themeshade:191;
 
+	font-weight:bold;}
 
+span.Heading2Char
 
+	{mso-style-name:"Heading 2 Char";
 
+	mso-style-unhide:no;
 
+	mso-style-locked:yes;
 
+	mso-style-link:"Heading 2";
 
+	mso-ansi-font-size:13.0pt;
 
+	mso-bidi-font-size:13.0pt;
 
+	font-family:"Cambria","serif";
 
+	mso-ascii-font-family:Cambria;
 
+	mso-ascii-theme-font:major-latin;
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:major-fareast;
 
+	mso-hansi-font-family:Cambria;
 
+	mso-hansi-theme-font:major-latin;
 
+	mso-bidi-font-family:"Times New Roman";
 
+	mso-bidi-theme-font:major-bidi;
 
+	color:#4F81BD;
 
+	mso-themecolor:accent1;
 
+	font-weight:bold;}
 
+span.Heading3Char
 
+	{mso-style-name:"Heading 3 Char";
 
+	mso-style-unhide:no;
 
+	mso-style-locked:yes;
 
+	mso-style-link:"Heading 3";
 
+	mso-ansi-font-size:12.0pt;
 
+	mso-bidi-font-size:12.0pt;
 
+	font-family:"Cambria","serif";
 
+	mso-ascii-font-family:Cambria;
 
+	mso-ascii-theme-font:major-latin;
 
+	mso-fareast-font-family:"Times New Roman";
 
+	mso-fareast-theme-font:major-fareast;
 
+	mso-hansi-font-family:Cambria;
 
+	mso-hansi-theme-font:major-latin;
 
+	mso-bidi-font-family:"Times New Roman";
 
+	mso-bidi-theme-font:major-bidi;
 
+	color:#4F81BD;
 
+	mso-themecolor:accent1;
 
+	font-weight:bold;}
 
+span.BalloonTextChar
 
+	{mso-style-name:"Balloon Text Char";
 
+	mso-style-unhide:no;
 
+	mso-style-locked:yes;
 
+	mso-style-link:"Balloon Text";
 
+	mso-ansi-font-size:8.0pt;
 
+	mso-bidi-font-size:8.0pt;
 
+	font-family:"Tahoma","sans-serif";
 
+	mso-ascii-font-family:Tahoma;
 
+	mso-hansi-font-family:Tahoma;
 
+	mso-bidi-font-family:Tahoma;}
 
+.MsoChpDefault
 
+	{mso-style-type:export-only;
 
+	mso-default-props:yes;
 
+	font-size:10.0pt;
 
+	mso-ansi-font-size:10.0pt;
 
+	mso-bidi-font-size:10.0pt;}
 
+@page WordSection1
 
+	{size:8.5in 11.0in;
 
+	margin:1.0in 1.25in 1.0in 1.25in;
 
+	mso-header-margin:.5in;
 
+	mso-footer-margin:.5in;
 
+	mso-paper-source:0;}
 
+div.WordSection1
 
+	{page:WordSection1;}
 
+ /* List Definitions */
 
+ @list l0
 
+	{mso-list-id:62067358;
 
+	mso-list-template-ids:-174943062;}
 
+@list l0:level1
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l0:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l0:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1
 
+	{mso-list-id:128015942;
 
+	mso-list-template-ids:-90681214;}
 
+@list l1:level1
 
+	{mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l1:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2
 
+	{mso-list-id:216556000;
 
+	mso-list-template-ids:925924412;}
 
+@list l2:level1
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l2:level2
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l2:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l2:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3
 
+	{mso-list-id:562446694;
 
+	mso-list-template-ids:913898366;}
 
+@list l3:level1
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l3:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l3:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4
 
+	{mso-list-id:797802132;
 
+	mso-list-template-ids:-1971191336;}
 
+@list l4:level1
 
+	{mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l4:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5
 
+	{mso-list-id:907304066;
 
+	mso-list-template-ids:1969781532;}
 
+@list l5:level1
 
+	{mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l5:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6
 
+	{mso-list-id:1050613616;
 
+	mso-list-template-ids:-1009886748;}
 
+@list l6:level1
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l6:level2
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l6:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l6:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7
 
+	{mso-list-id:1234970193;
 
+	mso-list-template-ids:2055904002;}
 
+@list l7:level1
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l7:level2
 
+	{mso-level-number-format:bullet;
 
+	mso-level-text:\F0B7;
 
+	mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;
 
+	mso-ansi-font-size:10.0pt;
 
+	font-family:Symbol;}
 
+@list l7:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l7:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8
 
+	{mso-list-id:1846092290;
 
+	mso-list-template-ids:-768590846;}
 
+@list l8:level1
 
+	{mso-level-start-at:2;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level2
 
+	{mso-level-tab-stop:1.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level3
 
+	{mso-level-tab-stop:1.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level4
 
+	{mso-level-tab-stop:2.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level5
 
+	{mso-level-tab-stop:2.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level6
 
+	{mso-level-tab-stop:3.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level7
 
+	{mso-level-tab-stop:3.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level8
 
+	{mso-level-tab-stop:4.0in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l8:level9
 
+	{mso-level-tab-stop:4.5in;
 
+	mso-level-number-position:left;
 
+	text-indent:-.25in;}
 
+@list l9
 
+	{mso-list-id:1894656566;
 
+	mso-list-template-ids:1199983812;}
 
+@list l9:level1
 
+	{mso-level-start-at:2;
 
+	mso-level-tab-stop:.5in;
 
+	mso-level-number-position:left;
 
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+
 
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+ <tbody><tr style="">
 
+  <td style="padding: 0in;" valign="top">
 
+  <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
 
+   <tbody><tr style="">
 
+    <td style="padding: 0in 5.4pt;" valign="top">
 
+    <p class="MsoNormal"><span style="font-size: 8pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
 
+    </td>
 
+   </tr>
 
+   <tr style="">
 
+    <td style="padding: 1.5pt;">
 
+    <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: rgb(51, 102, 255);">Release Notes for STM32F4x7 Ethernet Driver</span><span style="font-size: 20pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><o:p></o:p></span></h1>
 
+    <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
 
+    2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
 
+    <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
 
+    </td>
 
+   </tr>
 
+  </tbody></table>
 
+  <p class="MsoNormal"><span style="font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; display: none;"><o:p>&nbsp;</o:p></span></p>
 
+  <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
 
+   <tbody><tr style="">
 
+    <td style="padding: 0in;" valign="top">
 
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
 
+    <ol style="margin-top: 0in;" start="1" type="1">
 
+     <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#History">STM32F4x7 Ethernet Driver
 
+         update History</a><o:p></o:p></span></li>
 
+     <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#License">License</a><o:p></o:p></span></li>
 
+    </ol>
 
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4x7 Ethernet Driver&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 168px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 14-October-2011</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
 
+Changes<o:p></o:p></span></u></b></p>
 
+<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release&nbsp;for <span style="font-weight: bold; font-style: italic;">STM32F407xx/417xx</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> devices</span></span></li></ul><span style="font-family: &quot;Times New Roman&quot;,&quot;serif&quot;;"><br></span>
 
+    <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
 
+    <p class="MsoNormal" style="margin: 4.5pt 0in;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">The enclosed firmware and all the related documentation are
 
+    not covered by a License Agreement, if you need such License you can
 
+    contact your local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
 
+    <p class="MsoNormal"><b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
 
+    CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR
 
+    THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE
 
+    FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
 
+    CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
 
+    CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
 
+    THEIR PRODUCTS. <o:p></o:p></span></b></p>
 
+    <p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
 
+    <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
 
+    <hr align="center" size="2" width="100%">
 
+    </span></div>
 
+    <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
 
+    complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32(<span style="color: black;">CORTEX M3) 32-Bit
 
+    Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
 
+    </td>
 
+   </tr>
 
+  </tbody></table>
 
+  <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
 
+  </td>
 
+ </tr>
 
+</tbody></table>
 
+
 
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+
 
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
 
+
 
+</div>
 
+
 
+</body></html>

+ 2719 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth.c
Ver arquivo 

@@ -0,0 +1,2719 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4x7_eth.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.0
 
+  * @date    14-October-2011
 
+  * @brief   This file is the low level driver for STM32F407xx/417xx Ethernet Controller.
 
+  *          This driver does not include low level functions for PTP time-stamp.            
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  *
 
+  * <h2><center>&copy; Portions COPYRIGHT 2011 STMicroelectronics</center></h2>
 
+  ******************************************************************************
 
+  */
 
+/**
 
+  ******************************************************************************
 
+  * <h2><center>&copy; Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.</center></h2>
 
+  * @file    stm32f4x7_eth.c
 
+  * @author  CMP Team
 
+  * @version V1.0.0
 
+  * @date    28-December-2012
 
+  * @brief   This file is the low level driver for STM32F407xx/417xx Ethernet Controller.
 
+  *          This driver does not include low level functions for PTP time-stamp.     
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, Embest SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
 
+  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
 
+  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
 
+  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  ******************************************************************************
 
+  */
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4x7_eth.h"
 
+#include "stm32f4xx_rcc.h"
 
+#include <string.h>
 
+
 
+/** @addtogroup STM32F4x7_ETH_Driver
 
+  * @brief ETH driver modules
 
+  * @{
 
+  */
 
+
 
+/** @defgroup ETH_Private_TypesDefinitions
 
+  * @{
 
+  */ 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ETH_Private_Defines
 
+  * @{
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Private_Macros
 
+  * @{
 
+  */ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Private_Variables
 
+  * @{
 
+  */ 
+
 
+#if defined   (__CC_ARM) /*!< ARM Compiler */
 
+  __align(4) 
+   ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
 
+  __align(4) 
+   ETH_DMADESCTypeDef  DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
 
+  __align(4) 
+   uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
 
+  __align(4) 
+   uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
 
+
 
+#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
 
+  #pragma data_alignment=4
 
+   ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
 
+  #pragma data_alignment=4
 
+   ETH_DMADESCTypeDef  DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
 
+  #pragma data_alignment=4
 
+   uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
 
+  #pragma data_alignment=4
 
+   uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
 
+
 
+#elif defined (__GNUC__) /*!< GNU Compiler */
 
+  ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Rx DMA Descriptor */
 
+  ETH_DMADESCTypeDef  DMATxDscrTab[ETH_TXBUFNB] __attribute__ ((aligned (4))); /* Ethernet Tx DMA Descriptor */
 
+  uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Receive Buffer */
 
+  uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__ ((aligned (4))); /* Ethernet Transmit Buffer */
 
+
 
+#elif defined  (__TASKING__) /*!< TASKING Compiler */                           
+  __align(4) 
+   ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB];/* Ethernet Rx MA Descriptor */
 
+  __align(4) 
+   ETH_DMADESCTypeDef  DMATxDscrTab[ETH_TXBUFNB];/* Ethernet Tx DMA Descriptor */
 
+  __align(4) 
+   uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; /* Ethernet Receive Buffer */
 
+  __align(4) 
+   uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; /* Ethernet Transmit Buffer */
 
+
 
+#endif /* __CC_ARM */
 
+
 
+
 
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
 
+__IO ETH_DMADESCTypeDef  *DMATxDescToSet;
 
+__IO ETH_DMADESCTypeDef  *DMARxDescToGet;
 
+
 
+
 
+/* Structure used to hold the last received packet descriptors info */
 
+
 
+ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
 
+__IO ETH_DMA_Rx_Frame_infos *DMA_RX_FRAME_infos;
 
+__IO uint32_t Frame_Rx_index;
 
+
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Private_FunctionPrototypes
 
+  * @{
 
+  */ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Private_Functions
 
+  * @{
 
+  */
 
+
 
+#ifndef USE_Delay
 
+/**
 
+  * @brief  Inserts a delay time.
 
+  * @param  nCount: specifies the delay time length.
 
+  * @retval None
 
+  */
 
+static void ETH_Delay(__IO uint32_t nCount)
 
+{
 
+  __IO uint32_t index = 0; 
+  for(index = nCount; index != 0; index--)
 
+  {
 
+  }
 
+}
 
+#endif /* USE_Delay*/
 
+
 
+
 
+
 
+/******************************************************************************/                             
+/*                           Global ETH MAC/DMA functions                     */
 
+/******************************************************************************/
 
+
 
+/**
 
+  * @brief  Deinitializes the ETHERNET peripheral registers to their default reset values.
 
+  * @param  None 
+  * @retval None
 
+  */
 
+void ETH_DeInit(void)
 
+{
 
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
 
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Fills each ETH_InitStruct member with its default value.
 
+  * @param  ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
 
+{
 
+  /* ETH_InitStruct members default value */
 
+  /*------------------------   MAC Configuration   ---------------------------*/
 
+  
+  /* PHY Auto-negotiation enabled */
 
+  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;           
+  /* MAC watchdog enabled: cuts-off long frame */
 
+  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
 
+  /* MAC Jabber enabled in Half-duplex mode */
 
+  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;                                                       
+  /* Ethernet interframe gap set to 96 bits */
 
+  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;                                                                                                                             
+  /* Carrier Sense Enabled in Half-Duplex mode */ 
+  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;                                
+  /* PHY speed configured to 100Mbit/s */
 
+  ETH_InitStruct->ETH_Speed = ETH_Speed_100M; 
+  /* Receive own Frames in Half-Duplex mode enabled */
 
+  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;                
+  /* MAC MII loopback disabled */ 
+  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;              
+  /* Full-Duplex mode selected */
 
+  ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;                      
+  /* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */
 
+  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;                                                             
+  /* Retry Transmission enabled for half-duplex mode */ 
+  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;                                                                                   
+  /* Automatic PAD/CRC strip disabled*/
 
+  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                          
+  /* half-duplex mode retransmission Backoff time_limit = 10 slot times*/ 
+  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;     
+  /* half-duplex mode Deferral check disabled */
 
+  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;                                                                                                                  
+  /* Receive all frames disabled */ 
+  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
 
+  /* Source address filtering (on the optional MAC addresses) disabled */
 
+  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;   
+  /* Do not forward control frames that do not pass the address filtering */
 
+  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;   
+  /* Disable reception of Broadcast frames */
 
+  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
 
+  /* Normal Destination address filtering (not reverse addressing) */
 
+  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
 
+  /* Promiscuous address filtering mode disabled */
 
+  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             
+  /* Perfect address filtering for multicast addresses */
 
+  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;       
+  /* Perfect address filtering for unicast addresses */
 
+  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;      
+  /* Initialize hash table high and low regs */
 
+  ETH_InitStruct->ETH_HashTableHigh = 0x0;                
+  ETH_InitStruct->ETH_HashTableLow = 0x0;                     
+  /* Flow control config (flow control disabled)*/
 
+  ETH_InitStruct->ETH_PauseTime = 0x0;                 
+  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;            
+  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;         
+  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;   
+  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;        
+  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
 
+  /* VLANtag config (VLAN field not checked) */
 
+  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;          
+  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;          
+  
+  /*---------------------- DMA Configuration   -------------------------------*/
 
+
 
+  /* Drops frames with with TCP/IP checksum errors */
 
+  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; 
+  /* Store and forward mode enabled for receive */
 
+  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;       
+  /* Flush received frame that created FIFO overflow */
 
+  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; 
+  /* Store and forward mode enabled for transmit */
 
+  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;  
+  /* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */
 
+  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;  
+  /* Disable forwarding frames with errors (short frames, CRC,...)*/
 
+  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; 
+  /* Disable undersized good frames */
 
+  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; 
+  /* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */
 
+  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;                             
+  /* Disable Operate on second frame (transmit a second frame to FIFO without 
+  waiting status of previous frame*/                           
+  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
 
+  /* DMA works on 32-bit aligned start source and destinations addresses */
 
+  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
 
+  /* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
 
+  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
 
+  /* DMA transfer max burst length = 32 beats = 32 x 32bits */
 
+  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
 
+  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
 
+  /* DMA Ring mode skip length = 0 */
 
+  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; 
+  /* Equal priority (round-robin) between transmit and receive DMA engines */
 
+  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Initializes the ETHERNET peripheral according to the specified
 
+  *   parameters in the ETH_InitStruct .
 
+  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
 
+  *   the configuration information for the specified ETHERNET peripheral.
 
+  * @param PHYAddress: external PHY address                    
+  * @retval ETH_ERROR: Ethernet initialization failed
 
+  *         ETH_SUCCESS: Ethernet successfully initialized                 
+  */
 
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
 
+{
 
+  uint32_t RegValue = 0, tmpreg = 0;
 
+  __IO uint32_t i = 0;
 
+  RCC_ClocksTypeDef  rcc_clocks;
 
+  uint32_t hclk = 60000000;
 
+  __IO uint32_t timeout = 0;
 
+  /* Check the parameters */
 
+  /* MAC --------------------------*/ 
+  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
 
+  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
 
+  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
 
+  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
 
+  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
 
+  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
 
+  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
 
+  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
 
+  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
 
+  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
 
+  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
 
+  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
 
+  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
 
+  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
 
+  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
 
+  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
 
+  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
 
+  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
 
+  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
 
+  assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
 
+  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  
+  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
 
+  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
 
+  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
 
+  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
 
+  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
 
+  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
 
+  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
 
+  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
 
+  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
 
+  /* DMA --------------------------*/
 
+  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
 
+  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
 
+  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
 
+  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
 
+  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
 
+  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
 
+  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
 
+  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
 
+  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
 
+  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
 
+  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
 
+  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
 
+  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 
+  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  
+  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       
+  /*-------------------------------- MAC Config ------------------------------*/   
+  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
 
+  /* Get the ETHERNET MACMIIAR value */
 
+  tmpreg = ETH->MACMIIAR;
 
+  /* Clear CSR Clock Range CR[2:0] bits */
 
+  tmpreg &= MACMIIAR_CR_MASK;
 
+  /* Get hclk frequency value */
 
+  RCC_GetClocksFreq(&rcc_clocks);
 
+  hclk = rcc_clocks.HCLK_Frequency;
 
+  
+  /* Set CR bits depending on hclk value */
 
+  if((hclk >= 20000000)&&(hclk < 35000000))
 
+  {
 
+    /* CSR Clock Range between 20-35 MHz */
 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
 
+  }
 
+  else if((hclk >= 35000000)&&(hclk < 60000000))
 
+  {
 
+    /* CSR Clock Range between 35-60 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;    
+  }  
+  else if((hclk >= 60000000)&&(hclk < 100000000))
 
+  {
 
+    /* CSR Clock Range between 60-100 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;    
+  }  
+  else if((hclk >= 100000000)&&(hclk < 150000000))
 
+  {
 
+    /* CSR Clock Range between 100-150 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;    
+  }   
+  else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
 
+  {
 
+    /* CSR Clock Range between 150-168 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;    
+  }
 
+  
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
 
+  ETH->MACMIIAR = (uint32_t)tmpreg;  
+  /*-------------------- PHY initialization and configuration ----------------*/
 
+  /* Put the PHY in reset mode */
 
+  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
 
+  {
 
+    /* Return ERROR in case of write timeout */
 
+    return ETH_ERROR;
 
+  }
 
+  
+  /* Delay to assure PHY reset */
 
+  _eth_delay_(PHY_RESET_DELAY);
 
+    
+  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
 
+  {  
+    /* We wait for linked status... */
 
+    do
 
+    {
 
+      timeout++;
 
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
 
+
 
+    /* Return ERROR in case of timeout */
 
+    if(timeout == PHY_READ_TO)
 
+    {
 
+      return ETH_ERROR;
 
+    }
 
+
 
+    /* Reset Timeout counter */
 
+    timeout = 0; 
+    /* Enable Auto-Negotiation */
 
+    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
 
+    {
 
+      /* Return ERROR in case of write timeout */
 
+      return ETH_ERROR;
 
+    }
 
+
 
+    /* Wait until the auto-negotiation will be completed */
 
+    do
 
+    {
 
+      timeout++;
 
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));  
+
 
+    /* Return ERROR in case of timeout */
 
+    if(timeout == PHY_READ_TO)
 
+    {
 
+      return ETH_ERROR;
 
+    }
 
+
 
+    /* Reset Timeout counter */
 
+    timeout = 0;
 
+    
+    /* Read the result of the auto-negotiation */
 
+    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
 
+
 
+		switch (RegValue & PHY_DUPLEX_SPEED_STATUS_MASK)
 
+		{
 
+		  case PHY_100BTX_FULL:
 
+			  ETH_InitStruct->ETH_Mode  = ETH_Mode_FullDuplex;
 
+				ETH_InitStruct->ETH_Speed = ETH_Speed_100M; 
+			  break;
 
+
 
+		  case PHY_100BTX_HALF:
 
+			  ETH_InitStruct->ETH_Mode  = ETH_Mode_HalfDuplex;
 
+				ETH_InitStruct->ETH_Speed = ETH_Speed_100M; 
+  			break;
 
+
 
+		  case PHY_10M_FULL:
 
+			  ETH_InitStruct->ETH_Mode  = ETH_Mode_FullDuplex;
 
+				ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
 
+			  break;
 
+
 
+		  case PHY_10M_HALF:
 
+			  ETH_InitStruct->ETH_Mode  = ETH_Mode_HalfDuplex;
 
+				ETH_InitStruct->ETH_Speed = ETH_Speed_10M; 
+			  break;
 
+
 
+		  default:
 
+			  break;
 
+		}		   
+  }
 
+  else
 
+  {
 
+    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
 
+                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
 
+    {
 
+      /* Return ERROR in case of write timeout */
 
+      return ETH_ERROR;
 
+    }
 
+    /* Delay to assure PHY configuration */
 
+    _eth_delay_(PHY_CONFIG_DELAY);
 
+    
+  }
 
+  /*------------------------ ETHERNET MACCR Configuration --------------------*/
 
+  /* Get the ETHERNET MACCR value */  
+  tmpreg = ETH->MACCR;
 
+  /* Clear WD, PCE, PS, TE and RE bits */
 
+  tmpreg &= MACCR_CLEAR_MASK;
 
+  /* Set the WD bit according to ETH_Watchdog value */
 
+  /* Set the JD: bit according to ETH_Jabber value */
 
+  /* Set the IFG bit according to ETH_InterFrameGap value */ 
+  /* Set the DCRS bit according to ETH_CarrierSense value */  
+  /* Set the FES bit according to ETH_Speed value */ 
+  /* Set the DO bit according to ETH_ReceiveOwn value */ 
+  /* Set the LM bit according to ETH_LoopbackMode value */ 
+  /* Set the DM bit according to ETH_Mode value */ 
+  /* Set the IPCO bit according to ETH_ChecksumOffload value */                   
+  /* Set the DR bit according to ETH_RetryTransmission value */ 
+  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 
+  /* Set the BL bit according to ETH_BackOffLimit value */ 
+  /* Set the DC bit according to ETH_DeferralCheck value */                          
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 
+                  ETH_InitStruct->ETH_Jabber | 
+                  ETH_InitStruct->ETH_InterFrameGap |
 
+                  ETH_InitStruct->ETH_CarrierSense |
 
+                  ETH_InitStruct->ETH_Speed | 
+                  ETH_InitStruct->ETH_ReceiveOwn |
 
+                  ETH_InitStruct->ETH_LoopbackMode |
 
+                  ETH_InitStruct->ETH_Mode | 
+                  ETH_InitStruct->ETH_ChecksumOffload |    
+                  ETH_InitStruct->ETH_RetryTransmission | 
+                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 
+                  ETH_InitStruct->ETH_BackOffLimit | 
+                  ETH_InitStruct->ETH_DeferralCheck);
 
+  /* Write to ETHERNET MACCR */
 
+  ETH->MACCR = (uint32_t)tmpreg;
 
+  
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+  /* Set the RA bit according to ETH_ReceiveAll value */
 
+  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
 
+  /* Set the PCF bit according to ETH_PassControlFrames value */
 
+  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
 
+  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
 
+  /* Set the PR bit according to ETH_PromiscuousMode value */
 
+  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
 
+  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
 
+  /* Write to ETHERNET MACFFR */  
+  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 
+                          ETH_InitStruct->ETH_SourceAddrFilter |
 
+                          ETH_InitStruct->ETH_PassControlFrames |
 
+                          ETH_InitStruct->ETH_BroadcastFramesReception | 
+                          ETH_InitStruct->ETH_DestinationAddrFilter |
 
+                          ETH_InitStruct->ETH_PromiscuousMode |
 
+                          ETH_InitStruct->ETH_MulticastFramesFilter |
 
+                          ETH_InitStruct->ETH_UnicastFramesFilter); 
+  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
 
+  /* Write to ETHERNET MACHTHR */
 
+  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
 
+  /* Write to ETHERNET MACHTLR */
 
+  ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
 
+  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
 
+  /* Get the ETHERNET MACFCR value */  
+  tmpreg = ETH->MACFCR;
 
+  /* Clear xx bits */
 
+  tmpreg &= MACFCR_CLEAR_MASK;
 
+  
+  /* Set the PT bit according to ETH_PauseTime value */
 
+  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
 
+  /* Set the PLT bit according to ETH_PauseLowThreshold value */
 
+  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
 
+  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
 
+  /* Set the TFE bit according to ETH_TransmitFlowControl value */  
+  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | 
+                   ETH_InitStruct->ETH_ZeroQuantaPause |
 
+                   ETH_InitStruct->ETH_PauseLowThreshold |
 
+                   ETH_InitStruct->ETH_UnicastPauseFrameDetect | 
+                   ETH_InitStruct->ETH_ReceiveFlowControl |
 
+                   ETH_InitStruct->ETH_TransmitFlowControl); 
+  /* Write to ETHERNET MACFCR */
 
+  ETH->MACFCR = (uint32_t)tmpreg;
 
+  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
 
+  /* Set the ETV bit according to ETH_VLANTagComparison value */
 
+  /* Set the VL bit according to ETH_VLANTagIdentifier value */  
+  ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | 
+                             ETH_InitStruct->ETH_VLANTagIdentifier); 
+       
+  /*-------------------------------- DMA Config ------------------------------*/
 
+  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
 
+  /* Get the ETHERNET DMAOMR value */  
+  tmpreg = ETH->DMAOMR;
 
+  /* Clear xx bits */
 
+  tmpreg &= DMAOMR_CLEAR_MASK;
 
+  
+  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
 
+  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
 
+  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
 
+  /* Set the TSF bit according to ETH_TransmitStoreForward value */
 
+  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
 
+  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
 
+  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
 
+  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
 
+  /* Set the OSF bit according to ETH_SecondFrameOperate value */
 
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | 
+                  ETH_InitStruct->ETH_ReceiveStoreForward |
 
+                  ETH_InitStruct->ETH_FlushReceivedFrame |
 
+                  ETH_InitStruct->ETH_TransmitStoreForward | 
+                  ETH_InitStruct->ETH_TransmitThresholdControl |
 
+                  ETH_InitStruct->ETH_ForwardErrorFrames |
 
+                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
 
+                  ETH_InitStruct->ETH_ReceiveThresholdControl |                                   
+                  ETH_InitStruct->ETH_SecondFrameOperate); 
+  /* Write to ETHERNET DMAOMR */
 
+  ETH->DMAOMR = (uint32_t)tmpreg;
 
+  
+  /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 
+  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
 
+  /* Set the FB bit according to ETH_FixedBurst value */
 
+  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
 
+  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
 
+  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
 
+  /* Set the PR and DA bits according to ETH_DMAArbitration value */         
+  ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | 
+                          ETH_InitStruct->ETH_FixedBurst |
 
+                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
 
+                          ETH_InitStruct->ETH_TxDMABurstLength | 
+                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
 
+                          ETH_InitStruct->ETH_DMAArbitration |
 
+                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
 
+                          
+  #ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+    /* Enable the Enhanced DMA descriptors */
 
+    ETH->DMABMR |= ETH_DMABMR_EDE;
 
+  #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+                              
+  /* Return Ethernet configuration success */
 
+  return ETH_SUCCESS;
 
+}
 
+
 
+/**
 
+  * @brief  Enables ENET MAC and DMA reception/transmission 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_Start(void)
 
+{
 
+  /* Enable transmit state machine of the MAC for transmission on the MII */  
+  ETH_MACTransmissionCmd(ENABLE);
 
+  /* Flush Transmit FIFO */
 
+  ETH_FlushTransmitFIFO();
 
+  /* Enable receive state machine of the MAC for reception from the MII */  
+  ETH_MACReceptionCmd(ENABLE);
 
+ 
+  /* Start DMA transmission */
 
+  ETH_DMATransmissionCmd(ENABLE); 
+  /* Start DMA reception */
 
+  ETH_DMAReceptionCmd(ENABLE);   
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC transmission.
 
+  * @param  NewState: new state of the MAC transmission.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MACTransmissionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC transmission */
 
+    ETH->MACCR |= ETH_MACCR_TE;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC transmission */
 
+    ETH->MACCR &= ~ETH_MACCR_TE;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC reception.
 
+  * @param  NewState: new state of the MAC reception.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MACReceptionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC reception */
 
+    ETH->MACCR |= ETH_MACCR_RE;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC reception */
 
+    ETH->MACCR &= ~ETH_MACCR_RE;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
 
+  * @param  None
 
+  * @retval The new state of flow control busy status bit (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetFlowControlBusyStatus(void)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* The Flow Control register should not be written to until this bit is cleared */
 
+  if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Initiate a Pause Control Frame (Full-duplex only).
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_InitiatePauseControlFrame(void)  
+{ 
+  /* When Set In full duplex MAC initiates pause control frame */
 
+  ETH->MACFCR |= ETH_MACFCR_FCBBPA;  
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).
 
+  * @param  NewState: new state of the MAC BackPressure operation activation.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_BackPressureActivationCmd(FunctionalState NewState)   
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Activate the MAC BackPressure operation */
 
+    /* In Half duplex: during backpressure, when the MAC receives a new frame,
 
+    the transmitter starts sending a JAM pattern resulting in a collision */
 
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA; 
+  }
 
+  else
 
+  {
 
+    /* Desactivate the MAC BackPressure operation */
 
+    ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; 
+  } 
+}
 
+
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
 
+  * @param  ETH_MAC_FLAG: specifies the flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  * @retval The new state of ETHERNET MAC flag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); 
+  if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.
 
+  * @param  ETH_MAC_IT: specifies the interrupt source to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MAC_IT_TST   : Time stamp trigger interrupt  
+  *     @arg ETH_MAC_IT_MMCT : MMC transmit interrupt 
+  *     @arg ETH_MAC_IT_MMCR : MMC receive interrupt  
+  *     @arg ETH_MAC_IT_MMC  : MMC interrupt 
+  *     @arg ETH_MAC_IT_PMT  : PMT interrupt 
+  * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
 
+  */
 
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); 
+  if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the specified ETHERNET MAC interrupts.
 
+  * @param  ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
 
+  *   enabled or disabled.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_IT_PMT : PMT interrupt 
+  * @param  NewState: new state of the specified ETHERNET MAC interrupts.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ETHERNET MAC interrupts */
 
+    ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ETHERNET MAC interrupts */
 
+    ETH->MACIMR |= ETH_MAC_IT;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Configures the selected MAC address.
 
+  * @param  MacAddr: The MAC address to configure.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
 
+  *     @arg ETH_MAC_Address3 : MAC Address3
 
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
 
+  * @retval None
 
+  */
 
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
 
+{
 
+  uint32_t tmpreg;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
 
+  
+  /* Calculate the selected MAC address high register */
 
+  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
 
+  /* Load the selected MAC address high register */
 
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
 
+  /* Calculate the selected MAC address low register */
 
+  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
 
+ 
+  /* Load the selected MAC address low register */
 
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Get the selected MAC address.
 
+  * @param  MacAddr: The MAC address to return.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
 
+  *     @arg ETH_MAC_Address3 : MAC Address3
 
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
 
+  * @retval None
 
+  */
 
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
 
+{
 
+  uint32_t tmpreg;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
 
+  
+  /* Get the selected MAC address high register */
 
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
 
+ 
+  /* Calculate the selected MAC address buffer */
 
+  Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
 
+  Addr[4] = (tmpreg & (uint8_t)0xFF);
 
+  /* Load the selected MAC address low register */
 
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
 
+  /* Calculate the selected MAC address buffer */
 
+  Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
 
+  Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
 
+  Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
 
+  Addr[0] = (tmpreg & (uint8_t)0xFF);
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the Address filter module uses the specified
 
+  *   ETHERNET MAC address for perfect filtering 
+  * @param  MacAddr: specifies the ETHERNET MAC address to be used for perfect filtering.
 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
 
+  *     @arg ETH_MAC_Address3 : MAC Address3
 
+  * @param  NewState: new state of the specified ETHERNET MAC address use.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ETHERNET MAC address for perfect filtering */
 
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ETHERNET MAC address for perfect filtering */
 
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Set the filter type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
 
+  *     @arg ETH_MAC_Address3 : MAC Address3
 
+  * @param  Filter: specifies the used frame received field for comparison 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
 
+  *                                     SA fields of the received frame.
 
+  *     @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
 
+  *                                     DA fields of the received frame.
 
+  * @retval None
 
+  */
 
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
 
+  assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
 
+  
+  if (Filter != ETH_MAC_AddressFilter_DA)
 
+  {
 
+    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
 
+       received frame. */
 
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
 
+  }
 
+  else
 
+  {
 
+    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
 
+       received frame. */
 
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Set the filter type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
 
+  *     @arg ETH_MAC_Address3 : MAC Address3
 
+  * @param  MaskByte: specifies the used address bytes for comparison 
+  *   This parameter can be any combination of the following values: 
+  *     @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
 
+  *     @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
 
+  *     @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
 
+  *     @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
 
+  *     @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
 
+  *     @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
 
+  * @retval None
 
+  */
 
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
 
+  assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
 
+  
+  /* Clear MBC bits in the selected MAC address  high register */
 
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
 
+  /* Set the selected Filter mask bytes */
 
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
 
+}
 
+
 
+
 
+/******************************************************************************/                             
+/*                           DMA Descriptors functions                        */
 
+/******************************************************************************/
 
+
 
+/**
 
+  * @brief  This function should be called to get the received frame (to be used 
+  * with polling method only).
 
+  * @param  none
 
+  * @retval Structure of type FrameTypeDef
 
+  */
 
+FrameTypeDef ETH_Get_Received_Frame(void)
 
+{ 
+  uint32_t framelength = 0;
 
+  FrameTypeDef frame = {0,0,0}; 
+  
+  /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
 
+  framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
 
+  frame.length = framelength;
 
+  
+  /* Get the address of the buffer start address */ 
+  /* Check if more than one segment in the frame */
 
+  if (DMA_RX_FRAME_infos->Seg_Count >1)
 
+  {
 
+    frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
 
+  }
 
+  else 
+  {
 
+    frame.buffer = DMARxDescToGet->Buffer1Addr;
 
+  }
 
+
 
+  frame.descriptor = DMARxDescToGet;
 
+  
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */      
+  /* Chained Mode */    
+  /* Selects the next DMA Rx descriptor list for next buffer to read */ 
+  DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);    
+  
+  /* Return Frame */
 
+  return (frame);  
+}
 
+
 
+
 
+/**
 
+  * @brief  This function should be called when a frame is received using DMA 
+  *         Receive interrupt, it allows scanning of Rx descriptors to get the
 
+  *         the receive frame (should be used with interrupt mode only)
 
+  * @param  None
 
+  * @retval Structure of type FrameTypeDef
 
+  */
 
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
 
+{ 
+  FrameTypeDef frame={0,0,0};
 
+  __IO uint32_t descriptor_scan_counter = 0; 
+  
+  /* scan descriptors owned by CPU */
 
+  while (((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET)&&
 
+        (descriptor_scan_counter<ETH_RXBUFNB))
 
+  {
 
+    
+    /* Just by security */
 
+    descriptor_scan_counter++;
 
+    
+    /* check if first segment in frame */
 
+    if(((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
 
+      ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
 
+    {
 
+      DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
 
+      DMA_RX_FRAME_infos->Seg_Count = 1;   
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
 
+    }
 
+    
+    /* check if intermediate segment */
 
+    else if (((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET)&&
 
+            ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET))
 
+    {
 
+      (DMA_RX_FRAME_infos->Seg_Count) ++;
 
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
 
+    }
 
+
 
+    /* should be last segment */
 
+    else
 
+    { 
+      /* last segment */
 
+      DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet;
 
+      
+      (DMA_RX_FRAME_infos->Seg_Count)++;
 
+        
+      /* first segment is last segment */
 
+      if ((DMA_RX_FRAME_infos->Seg_Count)==1)
 
+        DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
 
+      
+      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
 
+      frame.length = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
 
+
 
+  
+      /* Get the address of the buffer start address */ 
+      /* Check if more than one segment in the frame */
 
+      if (DMA_RX_FRAME_infos->Seg_Count >1)
 
+      {
 
+        frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
 
+      }
 
+      else 
+      {
 
+        frame.buffer = DMARxDescToGet->Buffer1Addr;
 
+      }
 
+      
+      frame.descriptor = DMARxDescToGet;
 
+  
+      /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */      
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
 
+     
+      /* Return Frame */
 
+      return (frame);  
+    }
 
+  }
 
+  return (frame); 
+}
 
+      
+          
+/**
 
+  * @brief  Prepares DMA Tx descriptors to transmit an ethernet frame
 
+  * @param  FrameLength : length of the frame to send
 
+  * @retval error status
 
+  */
 
+uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength)
 
+{   
+  uint32_t buf_count =0, size=0,i=0;
 
+  __IO ETH_DMADESCTypeDef *DMATxNextDesc;
 
+  
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
 
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
 
+  {  
+    /* Return ERROR: OWN bit set */
 
+    return ETH_ERROR;
 
+  }
 
+  
+  DMATxNextDesc = DMATxDescToSet;
 
+  
+  if (FrameLength > ETH_TX_BUF_SIZE)
 
+  {
 
+    buf_count = FrameLength/ETH_TX_BUF_SIZE;
 
+    if (FrameLength%ETH_TX_BUF_SIZE) buf_count++;
 
+  }
 
+  else buf_count =1;
 
+  
+  if (buf_count ==1)
 
+  {
 
+    /*set LAST and FIRST segment */
 
+    DMATxDescToSet->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS;
 
+    /* Set frame size */
 
+    DMATxDescToSet->ControlBufferSize = (FrameLength& ETH_DMATxDesc_TBS1);
 
+    /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
 
+    DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
 
+    DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
 
+  }
 
+  else
 
+  {
 
+    for (i=0; i< buf_count; i++)
 
+    {
 
+      if (i==0) 
+      {
 
+        /* Setting the first segment bit */
 
+        DMATxDescToSet->Status |= ETH_DMATxDesc_FS;  
+      }
 
+      
+      /* Program size */
 
+      DMATxNextDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1);
 
+       
+      if (i== (buf_count-1))
 
+      {
 
+        /* Setting the last segment bit */
 
+        DMATxNextDesc->Status |= ETH_DMATxDesc_LS;
 
+        size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE;
 
+        DMATxNextDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1);
 
+      }
 
+        
+      /*give back descriptor to DMA */
 
+      DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
 
+      
+      DMATxNextDesc = (ETH_DMADESCTypeDef *)(DMATxNextDesc->Buffer2NextDescAddr);
 
+      /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
 
+     }
 
+    DMATxDescToSet = DMATxNextDesc ;
 
+  }
 
+    
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
 
+  if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
 
+  {
 
+    /* Clear TBUS ETHERNET DMA flag */
 
+    ETH->DMASR = ETH_DMASR_TBUS;
 
+    /* Resume DMA transmission*/
 
+    ETH->DMATPDR = 0;
 
+  }
 
+  
+  /* Return SUCCESS */
 
+  return ETH_SUCCESS;   
+}
 
+
 
+
 
+/**
 
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
 
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  RxBuff: Pointer on the first RxBuffer list
 
+  * @param  RxBuffCount: Number of the used Rx desc in the list
 
+  * @retval None
 
+  */
 
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
 
+{
 
+  uint32_t i = 0;
 
+  ETH_DMADESCTypeDef *DMARxDesc;
 
+  
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
 
+  DMARxDescToGet = DMARxDescTab; 
+  /* Fill each DMARxDesc descriptor with the right values */
 
+  for(i=0; i < RxBuffCount; i++)
 
+  {
 
+    /* Get the pointer on the ith member of the Rx Desc list */
 
+    DMARxDesc = DMARxDescTab+i;
 
+    /* Set Own bit of the Rx descriptor Status */
 
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
 
+
 
+    /* Set Buffer1 size and Second Address Chained bit */
 
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE;  
+    /* Set Buffer1 address pointer */
 
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
 
+    
+    /* Initialize the next descriptor with the Next Descriptor Polling Enable */
 
+    if(i < (RxBuffCount-1))
 
+    {
 
+      /* Set next descriptor address register with next descriptor base address */
 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+    }
 
+    else
 
+    {
 
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+    }
 
+  }
 
+   
+  /* Set Receive Descriptor List Address Register */
 
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab; 
+  
+
 
+  DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
 
+
 
+}
 
+
 
+/**
 
+  * @brief  This function polls for a frame reception
 
+  * @param  None
 
+  * @retval Returns 1 when a frame is received, 0 if none.
 
+  */
 
+uint32_t ETH_CheckFrameReceived(void)
 
+{ 
+  /* check if last segment */
 
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET)) 
+    {   
+      DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet;
 
+      DMA_RX_FRAME_infos->Seg_Count++;
 
+      return 1;
 
+    }
 
+  
+    /* check if first segment */
 
+    else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))      
+    {
 
+      DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
 
+      DMA_RX_FRAME_infos->LS_Rx_Desc = NULL;
 
+      DMA_RX_FRAME_infos->Seg_Count = 1;   
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
 
+    }
 
+    
+    /* check if intermediate segment */ 
+    else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&&
 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
 
+    {
 
+      (DMA_RX_FRAME_infos->Seg_Count) ++;
 
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
 
+    } 
+    return 0;
 
+}
 
+
 
+
 
+
 
+/**
 
+  * @brief  Initializes the DMA Tx descriptors in chain mode.
 
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff: Pointer on the first TxBuffer list
 
+  * @param  TxBuffCount: Number of the used Tx desc in the list
 
+  * @retval None
 
+  */
 
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
 
+{
 
+  uint32_t i = 0;
 
+  ETH_DMADESCTypeDef *DMATxDesc;
 
+  
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
 
+  DMATxDescToSet = DMATxDescTab;
 
+  /* Fill each DMATxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
 
+  {
 
+    /* Get the pointer on the ith member of the Tx Desc list */
 
+    DMATxDesc = DMATxDescTab + i;
 
+    /* Set Second Address Chained bit */
 
+    DMATxDesc->Status = ETH_DMATxDesc_TCH;  
+       
+    /* Set Buffer1 address pointer */
 
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
 
+    
+    /* Initialize the next descriptor with the Next Descriptor Polling Enable */
 
+    if(i < (TxBuffCount-1))
 
+    {
 
+      /* Set next descriptor address register with next descriptor base address */
 
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
 
+    }
 
+    else
 
+    {
 
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+    }
 
+  }
 
+   
+  /* Set Transmit Desciptor List Address Register */
 
+  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
 
+}
 
+
 
+
 
+
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
 
+  * @param  ETH_DMATxDescFlag: specifies the flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
 
+  *     @arg ETH_DMATxDesc_IC  : Interrupt on completion
 
+  *     @arg ETH_DMATxDesc_LS  : Last Segment
 
+  *     @arg ETH_DMATxDesc_FS  : First Segment
 
+  *     @arg ETH_DMATxDesc_DC  : Disable CRC
 
+  *     @arg ETH_DMATxDesc_DP  : Disable Pad
 
+  *     @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
 
+  *     @arg ETH_DMATxDesc_CIC : Checksum insertion control      
+  *     @arg ETH_DMATxDesc_TER : Transmit End of Ring
 
+  *     @arg ETH_DMATxDesc_TCH : Second Address Chained
 
+  *     @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
 
+  *     @arg ETH_DMATxDesc_IHE : IP Header Error
 
+  *     @arg ETH_DMATxDesc_ES  : Error summary
 
+  *     @arg ETH_DMATxDesc_JT  : Jabber Timeout
 
+  *     @arg ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
 
+  *     @arg ETH_DMATxDesc_PCE : Payload Checksum Error
 
+  *     @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during transmission
 
+  *     @arg ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the transceiver
 
+  *     @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
 
+  *     @arg ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
 
+  *     @arg ETH_DMATxDesc_VF  : VLAN Frame
 
+  *     @arg ETH_DMATxDesc_CC  : Collision Count 
+  *     @arg ETH_DMATxDesc_ED  : Excessive Deferral
 
+  *     @arg ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
 
+  *     @arg ETH_DMATxDesc_DB  : Deferred Bit
 
+  * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
 
+  
+  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor                     
+  * @retval The Transmit descriptor collision counter value.
 
+  */
 
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
 
+{
 
+  /* Return the Receive descriptor frame length */
 
+  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
 
+}
 
+
 
+/**
 
+  * @brief  Set the specified DMA Tx Desc Own bit.
 
+  * @param  DMATxDesc: Pointer on a Tx desc
 
+  * @retval None
 
+  */
 
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
 
+{
 
+  /* Set the DMA Tx Desc Own bit */
 
+  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
 
+  * @param  DMATxDesc: Pointer on a Tx desc
 
+  * @param  NewState: new state of the DMA Tx Desc transmit interrupt.
 
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
 
+  */
 
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA Tx Desc Transmit interrupt */
 
+    DMATxDesc->Status |= ETH_DMATxDesc_IC;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA Tx Desc Transmit interrupt */
 
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  configure Tx descriptor as last or first segment
 
+  * @param  DMATxDesc: Pointer on a Tx desc
 
+  * @param  DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment 
+  *     @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment                   
+  * @retval None
 
+  */
 
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
 
+  
+  /* Selects the DMA Tx Desc Frame segment */
 
+  DMATxDesc->Status |= DMATxDesc_FrameSegment;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor 
+  * @param  DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
 
+  *     @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
 
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
 
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
+  * @retval None
 
+  */
 
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
 
+  
+  /* Set the selected DMA Tx desc checksum insertion control */
 
+  DMATxDesc->Status |= DMATxDesc_Checksum;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DMA Tx Desc CRC.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
 
+  * @param  NewState: new state of the specified DMA Tx Desc CRC.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DMA Tx Desc CRC */
 
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DMA Tx Desc CRC */
 
+    DMATxDesc->Status |= ETH_DMATxDesc_DC; 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the DMA Tx Desc second address chained.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
 
+  * @param  NewState: new state of the specified DMA Tx Desc second address chained.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DMA Tx Desc second address chained */
 
+    DMATxDesc->Status |= ETH_DMATxDesc_TCH;  
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DMA Tx Desc second address chained */
 
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
 
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
 
+  * @param  NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
 
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
 
+    DMATxDesc->Status |= ETH_DMATxDesc_DP; 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
 
+  * @param  DMATxDesc: Pointer on a Tx desc
 
+  * @param  BufferSize1: specifies the Tx desc buffer1 size.
 
+  * @param  BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
 
+  * @retval None
 
+  */
 
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
 
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
 
+  
+  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
 
+  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
 
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
 
+  * @param  ETH_DMARxDescFlag: specifies the flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine 
+  *     @arg ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
 
+  *     @arg ETH_DMARxDesc_ES:          Error summary
 
+  *     @arg ETH_DMARxDesc_DE:          Descriptor error: no more descriptors for receive frame
 
+  *     @arg ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
 
+  *     @arg ETH_DMARxDesc_LE:          Frame size not matching with length field
 
+  *     @arg ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
 
+  *     @arg ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
 
+  *     @arg ETH_DMARxDesc_FS:          First descriptor of the frame
 
+  *     @arg ETH_DMARxDesc_LS:          Last descriptor of the frame
 
+  *     @arg ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error 
+  *     @arg ETH_DMARxDesc_LC:          Late collision occurred during reception
 
+  *     @arg ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
 
+  *     @arg ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
 
+  *     @arg ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
 
+  *     @arg ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
 
+  *     @arg ETH_DMARxDesc_CE:          CRC error
 
+  *     @arg ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
 
+  * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
 
+  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not.
 
+  * @param  DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor
 
+  * @param  ETH_DMAPTPRxDescFlag: specifies the extended flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMAPTPRxDesc_PTPV:   PTP version  
+  *     @arg ETH_DMAPTPRxDesc_PTPFT:  PTP frame type
 
+  *     @arg ETH_DMAPTPRxDesc_PTPMT:  PTP message type   
+  *     @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received   
+  *     @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received    
+  *     @arg ETH_DMAPTPRxDesc_IPCB:   IP checksum bypassed  
+  *     @arg ETH_DMAPTPRxDesc_IPPE:   IP payload error
 
+  *     @arg ETH_DMAPTPRxDesc_IPHE:   IP header error 
+  *     @arg ETH_DMAPTPRxDesc_IPPT:   IP payload type 
+  * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(ETH_DMAPTPRxDescExtendedFlag));
 
+
 
+  if ((DMAPTPRxDesc->ExtendedStatus & ETH_DMAPTPRxDescExtendedFlag) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+
 
+/**
 
+  * @brief  Set the specified DMA Rx Desc Own bit.
 
+  * @param  DMARxDesc: Pointer on a Rx desc
 
+  * @retval None
 
+  */
 
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
 
+{
 
+  /* Set the DMA Rx Desc Own bit */
 
+  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the specified DMA Rx Desc frame length.
 
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor                     
+  * @retval The Rx descriptor received frame length.
 
+  */
 
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
 
+{
 
+  /* Return the Receive descriptor frame length */
 
+  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DMA Rx Desc receive interrupt.
 
+  * @param  DMARxDesc: Pointer on a Rx desc
 
+  * @param  NewState: new state of the specified DMA Rx Desc interrupt.
 
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
 
+  */
 
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA Rx Desc receive interrupt */
 
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA Rx Desc receive interrupt */
 
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Returns the specified ETHERNET DMA Rx Desc buffer size.
 
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor 
+  * @param  DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
 
+  *   This parameter can be any one of the following values:
 
+  *     @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
 
+  *     @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2                     
+  * @retval The Receive descriptor frame length.
 
+  */
 
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
 
+  
+  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
 
+  {
 
+    /* Return the DMA Rx Desc buffer2 size */
 
+    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); 
+  }
 
+  else
 
+  {
 
+    /* Return the DMA Rx Desc buffer1 size */
 
+    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Get the size of the received packet.
 
+  * @param  None
 
+  * @retval framelength: received packet size 
+  */
 
+uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc)
 
+{
 
+  uint32_t frameLength = 0;
 
+  if(((DMARxDesc->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
 
+     ((DMARxDesc->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
 
+     ((DMARxDesc->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET)) 
+  {
 
+    /* Get the size of the packet: including 4 bytes of the CRC */
 
+    frameLength =  ETH_GetDMARxDescFrameLength(DMARxDesc);
 
+  }
 
+  
+  /* Return Frame Length */ 
+  return frameLength;
 
+}
 
+
 
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+/**
 
+  * @brief  Enables or disables the Enhanced descriptor structure.
 
+  * @param  NewState: new state of the Enhanced descriptor structure.
 
+  *   This parameter can be: ENABLE or DISABLE. 
+  * @retval None
 
+  */
 
+void ETH_EnhancedDescriptorCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable enhanced descriptor structure */
 
+    ETH->DMABMR |= ETH_DMABMR_EDE;  
+  }
 
+  else
 
+  {
 
+    /* Disable enhanced descriptor structure */
 
+    ETH->DMABMR &= ~ETH_DMABMR_EDE;
 
+  }
 
+}
 
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+
 
+/******************************************************************************/                             
+/*                           DMA functions                                    */
 
+/******************************************************************************/
 
+/**
 
+  * @brief  Resets all MAC subsystem internal registers and logic.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_SoftwareReset(void)
 
+{
 
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
 
+  /* After reset all the registers holds their respective reset values */
 
+  ETH->DMABMR |= ETH_DMABMR_SR;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the ETHERNET software reset bit is set or not.
 
+  * @param  None
 
+  * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetSoftwareResetStatus(void)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
 
+  * @param  ETH_DMA_FLAG: specifies the flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
 
+  *     @arg ETH_DMA_FLAG_PMT : PMT flag 
+  *     @arg ETH_DMA_FLAG_MMC : MMC flag 
+  *     @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
 
+  *     @arg ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
 
+  *     @arg ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
 
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
 
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag  
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ET  : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag 
+  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
 
+{  
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
 
+  if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the ETHERNET’s DMA pending flag.
 
+  * @param  ETH_DMA_FLAG: specifies the flag to clear.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
 
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag 
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ETI : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Receive Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag
 
+  * @retval None
 
+  */
 
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
 
+  
+  /* Clear the selected ETHERNET DMA FLAG */
 
+  ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified ETHERNET DMA interrupts.
 
+  * @param  ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
 
+  *   enabled or disabled.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt
 
+  * @param  NewState: new state of the specified ETHERNET DMA interrupts.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ETHERNET DMA interrupts */
 
+    ETH->DMAIER |= ETH_DMA_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ETHERNET DMA interrupts */
 
+    ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET DMA interrupt has occurred or not.
 
+  * @param  ETH_DMA_IT: specifies the interrupt source to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
 
+  *     @arg ETH_DMA_IT_PMT : PMT interrupt 
+  *     @arg ETH_DMA_IT_MMC : MMC interrupt
 
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt 
+  * @retval The new state of ETH_DMA_IT (SET or RESET).
 
+  */
 
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
 
+{  
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
 
+  if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the ETHERNET’s DMA IT pending bit.
 
+  * @param  ETH_DMA_IT: specifies the interrupt pending bit to clear.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ETI : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Transmit Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Receive Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt
 
+  * @retval None
 
+  */
 
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
 
+  
+  /* Clear the selected ETHERNET DMA IT */
 
+  ETH->DMASR = (uint32_t) ETH_DMA_IT;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the ETHERNET DMA Transmit Process State.
 
+  * @param  None
 
+  * @retval The new ETHERNET DMA Transmit Process State:
 
+  *   This can be one of the following values:
 
+  *     - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
 
+  *     - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor 
+  *     - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
 
+  *     - ETH_DMA_TransmitProcess_Reading   : Running - reading the data from host memory
 
+  *     - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Descriptor unavailable
 
+  *     - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor  
+  */
 
+uint32_t ETH_GetTransmitProcessState(void)
 
+{
 
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); 
+}
 
+
 
+/**
 
+  * @brief  Returns the ETHERNET DMA Receive Process State.
 
+  * @param  None
 
+  * @retval The new ETHERNET DMA Receive Process State:
 
+  *   This can be one of the following values:
 
+  *     - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
 
+  *     - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor 
+  *     - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
 
+  *     - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Descriptor unavailable
 
+  *     - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
 
+  *     - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the receive frame into host memory  
+  */
 
+uint32_t ETH_GetReceiveProcessState(void)
 
+{
 
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); 
+}
 
+
 
+/**
 
+  * @brief  Clears the ETHERNET transmit FIFO.
 
+  * @param  None                
+  * @retval None
 
+  */
 
+void ETH_FlushTransmitFIFO(void)
 
+{
 
+  /* Set the Flush Transmit FIFO bit */
 
+  ETH->DMAOMR |= ETH_DMAOMR_FTF;  
+}
 
+
 
+/**
 
+  * @brief  Checks whether the ETHERNET flush transmit FIFO bit is cleared or not.
 
+  * @param  None                
+  * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
 
+{   
+  FlagStatus bitstatus = RESET;
 
+  if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus; 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DMA transmission.
 
+  * @param  NewState: new state of the DMA transmission.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMATransmissionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA transmission */
 
+    ETH->DMAOMR |= ETH_DMAOMR_ST;  
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA transmission */
 
+    ETH->DMAOMR &= ~ETH_DMAOMR_ST;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DMA reception.
 
+  * @param  NewState: new state of the DMA reception.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_DMAReceptionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA reception */
 
+    ETH->DMAOMR |= ETH_DMAOMR_SR;  
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA reception */
 
+    ETH->DMAOMR &= ~ETH_DMAOMR_SR;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
 
+  * @param  ETH_DMA_Overflow: specifies the DMA overflow flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflows Counter
 
+  *     @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Buffer Unavailable Missed Frame Counter
 
+  * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
 
+  
+  if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
 
+  * @param  None
 
+  * @retval The value of Rx overflow Missed Frame Counter.
 
+  */
 
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
 
+{
 
+  return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
 
+  * @param  None
 
+  * @retval The value of Buffer unavailable Missed Frame Counter.
 
+  */
 
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
 
+{
 
+  return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA DMACHTDR register value.
 
+  * @param  None
 
+  * @retval The value of the current Tx desc start address.
 
+  */
 
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
 
+{
 
+  return ((uint32_t)(ETH->DMACHTDR));
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA DMACHRDR register value.
 
+  * @param  None
 
+  * @retval The value of the current Rx desc start address.
 
+  */
 
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
 
+{
 
+  return ((uint32_t)(ETH->DMACHRDR));
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA DMACHTBAR register value.
 
+  * @param  None
 
+  * @retval The value of the current transmit descriptor data buffer address.
 
+  */
 
+uint32_t ETH_GetCurrentTxBufferAddress(void)
 
+{
 
+  return ((uint32_t)(ETH->DMACHTBAR));
 
+}
 
+
 
+/**
 
+  * @brief  Get the ETHERNET DMA DMACHRBAR register value.
 
+  * @param  None
 
+  * @retval The value of the current receive descriptor data buffer address.
 
+  */
 
+uint32_t ETH_GetCurrentRxBufferAddress(void)
 
+{
 
+  return ((uint32_t)(ETH->DMACHRBAR));
 
+}
 
+
 
+/**
 
+  * @brief  Resumes the DMA Transmission by writing to the DmaTxPollDemand register
 
+  *   (the data written could be anything). This forces  the DMA to resume transmission.
 
+  * @param  None
 
+  * @retval None.
 
+  */
 
+void ETH_ResumeDMATransmission(void)
 
+{
 
+  ETH->DMATPDR = 0;
 
+}
 
+
 
+/**
 
+  * @brief  Resumes the DMA Transmission by writing to the DmaRxPollDemand register
 
+  *   (the data written could be anything). This forces the DMA to resume reception.
 
+  * @param  None
 
+  * @retval None.
 
+  */
 
+void ETH_ResumeDMAReception(void)
 
+{
 
+  ETH->DMARPDR = 0;
 
+}
 
+
 
+/**
 
+  * @brief  Set the DMA Receive status watchdog timer register value
 
+  * @param  Value: DMA Receive status watchdog timer register value   
+  * @retval None
 
+  */
 
+void ETH_SetReceiveWatchdogTimer(uint8_t Value)
 
+{
 
+  /* Set the DMA Receive status watchdog timer register */
 
+  ETH->DMARSWTR = Value;
 
+}
 
+
 
+/******************************************************************************/                             
+/*                                PHY functions                               */
 
+/******************************************************************************/
 
+
 
+/**
 
+  * @brief  Read a PHY register
 
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31                  
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR: Transceiver Basic Control Register 
+  *     @arg PHY_BSR: Transceiver Basic Status Register 
+  *     @arg PHY_SR : Transceiver Status Register    
+  *     @arg More PHY register could be read depending on the used PHY
 
+  * @retval ETH_ERROR: in case of timeout
 
+  *         MAC MIIDR register value: Data read from the selected PHY register (correct read )
 
+  */
 
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
 
+{
 
+  uint32_t tmpreg = 0;     
+__IO uint32_t timeout = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
 
+  assert_param(IS_ETH_PHY_REG(PHYReg));
 
+  
+  /* Get the ETHERNET MACMIIAR value */
 
+  tmpreg = ETH->MACMIIAR;
 
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
 
+  tmpreg &= ~MACMIIAR_CR_MASK;
 
+  /* Prepare the MII address register value */
 
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
 
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
 
+  tmpreg &= ~ETH_MACMIIAR_MW;                              /* Set the read mode */
 
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
 
+  /* Write the result value into the MII Address register */
 
+  ETH->MACMIIAR = tmpreg;
 
+  /* Check for the Busy flag */
 
+  do
 
+  {
 
+    timeout++;
 
+    tmpreg = ETH->MACMIIAR;
 
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
 
+  /* Return ERROR in case of timeout */
 
+  if(timeout == PHY_READ_TO)
 
+  {
 
+    return (uint16_t)ETH_ERROR;
 
+  }
 
+  
+  /* Return data register value */
 
+  return (uint16_t)(ETH->MACMIIDR);
 
+}
 
+
 
+/**
 
+  * @brief  Write to a PHY register
 
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31
 
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR    : Transceiver Control Register  
+  *     @arg More PHY register could be written depending on the used PHY
 
+  * @param  PHYValue: the value to write
 
+  * @retval ETH_ERROR: in case of timeout
 
+  *         ETH_SUCCESS: for correct write
 
+  */
 
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
 
+{
 
+  uint32_t tmpreg = 0;     
+  __IO uint32_t timeout = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
 
+  assert_param(IS_ETH_PHY_REG(PHYReg));
 
+  
+  /* Get the ETHERNET MACMIIAR value */
 
+  tmpreg = ETH->MACMIIAR;
 
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
 
+  tmpreg &= ~MACMIIAR_CR_MASK;
 
+  /* Prepare the MII register address value */
 
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
 
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
 
+  tmpreg |= ETH_MACMIIAR_MW;                               /* Set the write mode */
 
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
 
+  /* Give the value to the MII data register */
 
+  ETH->MACMIIDR = PHYValue;
 
+  /* Write the result value into the MII Address register */
 
+  ETH->MACMIIAR = tmpreg;
 
+  /* Check for the Busy flag */
 
+  do
 
+  {
 
+    timeout++;
 
+    tmpreg = ETH->MACMIIAR;
 
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
 
+  /* Return ERROR in case of timeout */
 
+  if(timeout == PHY_WRITE_TO)
 
+  {
 
+    return ETH_ERROR;
 
+  }
 
+  
+  /* Return SUCCESS */
 
+  return ETH_SUCCESS;  
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the PHY loopBack mode.
 
+  * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
 
+  *  loopback at MII level
 
+  * @param  PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.                   
+  * @param  NewState: new state of the PHY loopBack mode.
 
+  *   This parameter can be: ENABLE or DISABLE.    
+  * @retval ETH_ERROR: in case of bad PHY configuration
 
+  *         ETH_SUCCESS: for correct PHY configuration
 
+  */
 
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
 
+{
 
+  uint16_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  /* Get the PHY configuration to update it */
 
+  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the PHY loopback mode */
 
+    tmpreg |= PHY_Loopback;  
+  }
 
+  else
 
+  {
 
+    /* Disable the PHY loopback mode: normal mode */
 
+    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
 
+  }
 
+  /* Update the PHY control register with the new configuration */
 
+  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
 
+  {
 
+    return ETH_SUCCESS;
 
+  }
 
+  else
 
+  {
 
+    /* Return SUCCESS */
 
+    return ETH_ERROR; 
+  }   
+} 
+
 
+/******************************************************************************/                             
+/*                           Power Management(PMT) functions                  */
 
+/******************************************************************************/    
+/**
 
+  * @brief  Reset Wakeup frame filter register pointer.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
 
+{  
+  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
 
+  ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;  
+}
 
+
 
+/**
 
+  * @brief  Populates the remote wakeup frame registers.
 
+  * @param  Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
 
+  * @retval None
 
+  */
 
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
 
+{
 
+  uint32_t i = 0;
 
+  
+  /* Fill Remote Wake-up Frame Filter register with Buffer data */
 
+  for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)
 
+  {
 
+    /* Write each time to the same register */ 
+    ETH->MACRWUFFR = Buffer[i];
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables any unicast packet filtered by the MAC address
 
+  *   recognition to be a wake-up frame.
 
+  * @param  NewState: new state of the MAC Global Unicast Wake-Up.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC Global Unicast Wake-Up */
 
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC Global Unicast Wake-Up */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
 
+  * @param  ETH_PMT_FLAG: specifies the flag to check.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 
+  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
+  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
 
+  * @retval The new state of ETHERNET PMT Flag (SET or RESET).
 
+  */
 
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
 
+  
+  if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC Wake-Up Frame Detection.
 
+  * @param  NewState: new state of the MAC Wake-Up Frame Detection.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC Wake-Up Frame Detection */
 
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC Wake-Up Frame Detection */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC Magic Packet Detection.
 
+  * @param  NewState: new state of the MAC Magic Packet Detection.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC Magic Packet Detection */
 
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC Magic Packet Detection */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the MAC Power Down.
 
+  * @param  NewState: new state of the MAC Power Down.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_PowerDownCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MAC Power Down */
 
+    /* This puts the MAC in power down mode */
 
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;  
+  }
 
+  else
 
+  {
 
+    /* Disable the MAC Power Down */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
 
+  }
 
+} 
+
 
+/******************************************************************************/                             
+/*                              MMC functions                                 */
 
+/******************************************************************************/                            
+/**
 
+  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)   
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_MMCCounterFullPreset(void)
 
+{
 
+  /* Preset and Initialize the MMC counters to almost-full value */
 
+  ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
 
+}
 
+
 
+/**
 
+  * @brief  Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16). 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_MMCCounterHalfPreset(void)
 
+{
 
+  /* Preset the MMC counters to almost-full value */
 
+  ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
 
+  /* Initialize the MMC counters to almost-half value */
 
+  ETH->MMCCR |= ETH_MMCCR_MCP;
 
+}
 
+
 
+ /**
 
+  * @brief  Enables or disables the MMC Counter Freeze.
 
+  * @param  NewState: new state of the MMC Counter Freeze.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MMC Counter Freeze */
 
+    ETH->MMCCR |= ETH_MMCCR_MCF;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the MMC Counter Freeze */
 
+    ETH->MMCCR &= ~ETH_MMCCR_MCF;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the MMC Reset On Read.
 
+  * @param  NewState: new state of the MMC Reset On Read.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the MMC Counter reset on read */
 
+    ETH->MMCCR |= ETH_MMCCR_ROR; 
+  }
 
+  else
 
+  {
 
+    /* Disable the MMC Counter reset on read */
 
+    ETH->MMCCR &= ~ETH_MMCCR_ROR;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the MMC Counter Stop Rollover.
 
+  * @param  NewState: new state of the MMC Counter Stop Rollover.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Disable the MMC Counter Stop Rollover  */
 
+    ETH->MMCCR &= ~ETH_MMCCR_CSR;
 
+  }
 
+  else
 
+  {
 
+    /* Enable the MMC Counter Stop Rollover */
 
+    ETH->MMCCR |= ETH_MMCCR_CSR; 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Resets the MMC Counters.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ETH_MMCCountersReset(void)
 
+{
 
+  /* Resets the MMC Counters */
 
+  ETH->MMCCR |= ETH_MMCCR_CR; 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified ETHERNET MMC interrupts.
 
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
 
+  *   This parameter can be any combination of Tx interrupt or 
+  *   any combination of Rx interrupt (but not both)of the following values: 
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
 
+  * @param  NewState: new state of the specified ETHERNET MMC interrupts.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+   
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
 
+  {
 
+    /* Remove Register mak from IT */
 
+    ETH_MMC_IT &= 0xEFFFFFFF;
 
+  
+    /* ETHERNET MMC Rx interrupts selected */
 
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the selected ETHERNET MMC interrupts */
 
+      ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
 
+    }
 
+    else
 
+    {
 
+      /* Disable the selected ETHERNET MMC interrupts */
 
+      ETH->MMCRIMR |= ETH_MMC_IT;    
+    }
 
+  }
 
+  else
 
+  {
 
+    /* ETHERNET MMC Tx interrupts selected */
 
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the selected ETHERNET MMC interrupts */
 
+      ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
 
+    }
 
+    else
 
+    {
 
+      /* Disable the selected ETHERNET MMC interrupts */
 
+      ETH->MMCTIMR |= ETH_MMC_IT;    
+    }  
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ETHERNET MMC IT is set or not.
 
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value 
+  * @retval The value of ETHERNET MMC IT (SET or RESET).
 
+  */
 
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); 
+  
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
 
+  {
 
+    /* ETHERNET MMC Rx interrupts selected */
 
+    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occurred */ 
+    if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET))
 
+    {
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    {
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    /* ETHERNET MMC Tx interrupts selected */
 
+    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occurred */  
+    if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET))
 
+    {
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    {
 
+      bitstatus = RESET;
 
+    }  
+  }    
+    
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Get the specified ETHERNET MMC register value.
 
+  * @param  ETH_MMCReg: specifies the ETHERNET MMC register.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg ETH_MMCCR      : MMC CR register 
+  *     @arg ETH_MMCRIR     : MMC RIR register 
+  *     @arg ETH_MMCTIR     : MMC TIR register 
+  *     @arg ETH_MMCRIMR    : MMC RIMR register 
+  *     @arg ETH_MMCTIMR    : MMC TIMR register 
+  *     @arg ETH_MMCTGFSCCR : MMC TGFSCCR register 
+  *     @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register  
+  *     @arg ETH_MMCTGFCR   : MMC TGFCR register
 
+  *     @arg ETH_MMCRFCECR  : MMC RFCECR register 
+  *     @arg ETH_MMCRFAECR  : MMC RFAECR register 
+  *     @arg ETH_MMCRGUFCR  : MMC RGUFCRregister 
+  * @retval The value of ETHERNET MMC Register value.
 
+  */
 
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
 
+  
+  /* Return the selected register value */
 
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
 
+}
 
+
 
+
 
+                                                   
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */

+ 1902 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth.h
Ver arquivo 

@@ -0,0 +1,1902 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4x7_eth.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.0
 
+  * @date    14-October-2011
 
+  * @brief   This file contains all the functions prototypes for the Ethernet
 
+  *          firmware driver.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  *
 
+  * <h2><center>&copy; Portions COPYRIGHT 2011 STMicroelectronics</center></h2>
 
+  ******************************************************************************
 
+  */
 
+/**
 
+  ******************************************************************************
 
+  * <h2><center>&copy; Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.</center></h2>
 
+  * @file    stm32f4x7_eth.h
 
+  * @author  CMP Team
 
+  * @version V1.0.0
 
+  * @date    28-December-2012
 
+  * @brief   This file contains all the functions prototypes for the Ethernet
 
+  *          firmware driver.     
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, Embest SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
 
+  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
 
+  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
 
+  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  ******************************************************************************
 
+  */
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4x7_ETH_H
 
+#define __STM32F4x7_ETH_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4x7_eth_conf.h"
 
+
 
+/** @addtogroup STM32F4x7_ETH_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup ETH_Exported_Types
 
+  * @{
 
+  */
 
+
 
+/** 
+  * @brief  ETH MAC Init structure definition
 
+  * @note   The user should not configure all the ETH_InitTypeDef structure's fields. 
+  *   By calling the ETH_StructInit function the structure’s fields are set to their default values.
 
+  *   Only the parameters that will be set to a non-default value should be configured.  
+  */ 
+typedef struct {
 
+/** 
+  * @brief / * MAC  
+  */ 
+  uint32_t             ETH_AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
 
+                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
 
+                                                           and the mode (half/full-duplex).
 
+                                                           This parameter can be a value of @ref ETH_AutoNegotiation */
 
+
 
+  uint32_t             ETH_Watchdog;                  /*!< Selects or not the Watchdog timer
 
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
 
+                                                           When disabled, the MAC can receive up to 16384 bytes.
 
+                                                           This parameter can be a value of @ref ETH_watchdog */  
+
 
+  uint32_t             ETH_Jabber;                    /*!< Selects or not Jabber timer
 
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
 
+                                                           When disabled, the MAC can send up to 16384 bytes.
 
+                                                           This parameter can be a value of @ref ETH_Jabber */
 
+
 
+  uint32_t             ETH_InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission
 
+                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
+
 
+  uint32_t             ETH_CarrierSense;              /*!< Selects or not the Carrier Sense
 
+                                                           This parameter can be a value of @ref ETH_Carrier_Sense */
 
+
 
+  uint32_t             ETH_Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps
 
+                                                           This parameter can be a value of @ref ETH_Speed */
 
+
 
+  uint32_t             ETH_ReceiveOwn;                /*!< Selects or not the ReceiveOwn
 
+                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
 
+                                                           in Half-Duplex mode
 
+                                                           This parameter can be a value of @ref ETH_Receive_Own */  
+
 
+  uint32_t             ETH_LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode
 
+                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
+
 
+  uint32_t             ETH_Mode;                      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
 
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */  
+
 
+  uint32_t             ETH_ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
 
+                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
+
 
+  uint32_t             ETH_RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
 
+                                                           when a collision occurs (Half-Duplex mode)
 
+                                                           This parameter can be a value of @ref ETH_Retry_Transmission */
 
+
 
+  uint32_t             ETH_AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping
 
+                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
+
 
+  uint32_t             ETH_BackOffLimit;              /*!< Selects the BackOff limit value
 
+                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */
 
+
 
+  uint32_t             ETH_DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode)
 
+                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
+
 
+  uint32_t             ETH_ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering)
 
+                                                           This parameter can be a value of @ref ETH_Receive_All */   
+
 
+  uint32_t             ETH_SourceAddrFilter;          /*!< Selects the Source Address Filter mode                                                           
+                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
+
 
+  uint32_t             ETH_PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
+                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
+
 
+  uint32_t             ETH_BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames
 
+                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
 
+
 
+  uint32_t             ETH_DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames
 
+                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
+
 
+  uint32_t             ETH_PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
 
+                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */
 
+
 
+  uint32_t             ETH_MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
 
+                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
+
 
+  uint32_t             ETH_UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
 
+                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
+
 
+  uint32_t             ETH_HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.  */    
+
 
+  uint32_t             ETH_HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.  */    
+
 
+  uint32_t             ETH_PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the
 
+                                                           transmit control frame */
 
+
 
+  uint32_t             ETH_ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
 
+                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
+
 
+  uint32_t             ETH_PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
 
+                                                           automatic retransmission of PAUSE Frame
 
+                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */
 
+                                                           
+  uint32_t             ETH_UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
 
+                                                           unicast address and unique multicast address)
 
+                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
+
 
+  uint32_t             ETH_ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
 
+                                                           disable its transmitter for a specified time (Pause Time)
 
+                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */
 
+
 
+  uint32_t             ETH_TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
 
+                                                           or the MAC back-pressure operation (Half-Duplex mode)
 
+                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
+
 
+  uint32_t             ETH_VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
 
+                                                           comparison and filtering
 
+                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
+
 
+  uint32_t             ETH_VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
 
+
 
+/** 
+  * @brief / * DMA  
+  */ 
+
 
+  uint32_t             ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
 
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+
 
+  uint32_t             ETH_ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode
 
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+
 
+  uint32_t             ETH_FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames
 
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+
 
+  uint32_t             ETH_TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode
 
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+
 
+  uint32_t             ETH_TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control
 
+                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
 
+
 
+  uint32_t             ETH_ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames
 
+                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
 
+
 
+  uint32_t             ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
 
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
 
+                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
 
+
 
+  uint32_t             ETH_ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO
 
+                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
 
+
 
+  uint32_t             ETH_SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
 
+                                                             frame of Transmit data even before obtaining the status for the first frame.
 
+                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
 
+
 
+  uint32_t             ETH_AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats
 
+                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
 
+
 
+  uint32_t             ETH_FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers
 
+                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
 
+                       
+  uint32_t             ETH_RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
 
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+
 
+  uint32_t             ETH_TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
 
+                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */                                                   
+
 
+  uint32_t             ETH_DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */                                                             
+
 
+  uint32_t             ETH_DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration
 
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+}ETH_InitTypeDef;
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                           DMA descriptors types
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+
 
+/** 
+  * @brief  ETH DMA Descriptors data structure definition
 
+  */ 
+typedef struct  {
 
+  __IO uint32_t   Status;                /*!< Status */
 
+  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
 
+  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
 
+  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
 
+/* Enhanced ETHERNET DMA PTP Descriptors */
 
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+  uint32_t   ExtendedStatus;        /* Extended status for PTP receive descriptor */
 
+  uint32_t   Reserved1;             /* Reserved */
 
+  uint32_t   TimeStampLow;          /* Time Stamp Low value for transmit and receive */
 
+  uint32_t   TimeStampHigh;         /* Time Stamp High value for transmit and receive */
 
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+} ETH_DMADESCTypeDef;
 
+
 
+
 
+typedef struct{
 
+  u32 length;
 
+  u32 buffer;
 
+  __IO ETH_DMADESCTypeDef *descriptor;
 
+}FrameTypeDef;
 
+
 
+
 
+typedef struct  {
 
+  __IO ETH_DMADESCTypeDef *FS_Rx_Desc;          /*!< First Segment Rx Desc */
 
+  __IO ETH_DMADESCTypeDef *LS_Rx_Desc;          /*!< Last Segment Rx Desc */
 
+  __IO uint32_t  Seg_Count;                     /*!< Segment count */
 
+} ETH_DMA_Rx_Frame_infos;
 
+  
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Exported_Constants
 
+  * @{
 
+  */ 
+ 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                          ETH Frames defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+
 
+/** @defgroup ENET_Buffers_setting 
+  * @{
 
+  */ 
+#define ETH_MAX_PACKET_SIZE    1524    /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
 
+#define ETH_HEADER               14    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
 
+#define ETH_CRC                   4    /*!< Ethernet CRC */
 
+#define ETH_EXTRA                 2    /*!< Extra bytes in some cases */   
+#define VLAN_TAG                  4    /*!< optional 802.1q VLAN Tag */
 
+#define MIN_ETH_PAYLOAD          46    /*!< Minimum Ethernet payload size */
 
+#define MAX_ETH_PAYLOAD        1500    /*!< Maximum Ethernet payload size */
 
+#define JUMBO_FRAME_PAYLOAD    9000    /*!< Jumbo frame payload size */      
+
 
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
 
+    an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
 
+    to the driver receive buffers memory.
 
+    
+    Depending on the size of the received ethernet packet and the size of 
+    each ethernet driver receive buffer, the received packet can take one or more
 
+    ethernet driver receive buffer. 
+    
+    In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 
+    and the total count of the driver receive buffers ETH_RXBUFNB.
 
+    
+    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 
+    example, they can be reconfigured in the application layer to fit the application 
+    needs */ 
+   
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
 
+   packet */    
+#ifndef ETH_RX_BUF_SIZE
 
+ #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE 
+#endif
 
+
 
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 
+#ifndef ETH_RXBUFNB
 
+ #define ETH_RXBUFNB             5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
 
+#endif
 
+
 
+
 
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
 
+    an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 
+    driver transmit buffers memory to the TxFIFO.
 
+    
+    Depending on the size of the Ethernet packet to be transmitted and the size of 
+    each ethernet driver transmit buffer, the packet to be transmitted can take 
+    one or more ethernet driver transmit buffer. 
+    
+    In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 
+    and the total count of the driver transmit buffers ETH_TXBUFNB.
 
+    
+    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 
+    example, they can be reconfigured in the application layer to fit the application 
+    needs */ 
+   
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
 
+   packet */  
+#ifndef ETH_TX_BUF_SIZE 
+ #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
 
+#endif
 
+
 
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 
+#ifndef ETH_TXBUFNB
 
+ #define ETH_TXBUFNB             5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
 
+#endif
 
+
 
+#define  ETH_DMARxDesc_FrameLengthShift           16
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                 Ethernet DMA descriptors registers bits definition
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+
 
+/**
 
+@code 
+   DMA Tx Desciptor
 
+  -----------------------------------------------------------------------------------------------
 
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
 
+  -----------------------------------------------------------------------------------------------
 
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
 
+  -----------------------------------------------------------------------------------------------
 
+  TDES2 |                         Buffer1 Address [31:0]                                         |
 
+  -----------------------------------------------------------------------------------------------
 
+  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
 
+  -----------------------------------------------------------------------------------------------
 
+@endcode
 
+*/
 
+
 
+/** 
+  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
 
+  */ 
+#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
 
+#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
 
+#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
 
+#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
 
+#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
 
+#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
 
+#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
 
+#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
 
+#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
+#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
+#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
 
+#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
 
+#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
 
+#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
 
+#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
 
+#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
 
+#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
 
+#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
 
+#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
 
+#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
 
+#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
 
+#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
 
+#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
 
+#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
 
+#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
 
+#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
 
+#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
 
+
 
+/** 
+  * @brief  Bit definition of TDES1 register
 
+  */ 
+#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
 
+#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
 
+
 
+/** 
+  * @brief  Bit definition of TDES2 register
 
+  */ 
+#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
 
+
 
+/** 
+  * @brief  Bit definition of TDES3 register
 
+  */ 
+#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
 
+
 
+  /*---------------------------------------------------------------------------------------------
 
+  TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
 
+  -----------------------------------------------------------------------------------------------
 
+  TDES7 |                         Transmit Time Stamp High [31:0]                                |
 
+  ----------------------------------------------------------------------------------------------*/
 
+
 
+/* Bit definition of TDES6 register */
 
+ #define ETH_DMAPTPTxDesc_TTSL  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp Low */
 
+
 
+/* Bit definition of TDES7 register */
 
+ #define ETH_DMAPTPTxDesc_TTSH  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp High */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_Rx_descriptor 
+  * @{
 
+  */
 
+
 
+/**
 
+@code 
+  DMA Rx Descriptor
 
+  --------------------------------------------------------------------------------------------------------------------
 
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+@endcode
 
+*/
 
+
 
+/** 
+  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
 
+  */ 
+#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
 
+#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
 
+#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
 
+#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
 
+#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */
 
+#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
 
+#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
 
+#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
 
+#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
 
+#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
 
+#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
+#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
+#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
 
+#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
 
+#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
 
+#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
 
+#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
 
+#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /*!< CRC error */
 
+#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
 
+
 
+/** 
+  * @brief  Bit definition of RDES1 register
 
+  */ 
+#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
 
+#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
 
+#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
 
+#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
 
+#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
 
+
 
+/** 
+  * @brief  Bit definition of RDES2 register  
+  */ 
+#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
 
+
 
+/** 
+  * @brief  Bit definition of RDES3 register  
+  */ 
+#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
 
+
 
+/*---------------------------------------------------------------------------------------------------------------------
 
+  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES5 |                                            Reserved[31:0]                                                    |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
 
+  ---------------------------------------------------------------------------------------------------------------------
 
+  RDES7 |                                       Receive Time Stamp High [31:0]                                         |
 
+  --------------------------------------------------------------------------------------------------------------------*/
 
+
 
+/* Bit definition of RDES4 register */
 
+#define ETH_DMAPTPRxDesc_PTPV     ((uint32_t)0x00002000)  /* PTP Version */
 
+#define ETH_DMAPTPRxDesc_PTPFT    ((uint32_t)0x00001000)  /* PTP Frame Type */
 
+#define ETH_DMAPTPRxDesc_PTPMT    ((uint32_t)0x00000F00)  /* PTP Message Type */
 
+  #define ETH_DMAPTPRxDesc_PTPMT_Sync                      ((uint32_t)0x00000100)  /* SYNC message (all clock types) */
 
+  #define ETH_DMAPTPRxDesc_PTPMT_FollowUp                  ((uint32_t)0x00000200)  /* FollowUp message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_DelayReq                  ((uint32_t)0x00000300)  /* DelayReq message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_DelayResp                 ((uint32_t)0x00000400)  /* DelayResp message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce        ((uint32_t)0x00000500)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag          ((uint32_t)0x00000600)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           
+#define ETH_DMAPTPRxDesc_IPV6PR   ((uint32_t)0x00000080)  /* IPv6 Packet Received */
 
+#define ETH_DMAPTPRxDesc_IPV4PR   ((uint32_t)0x00000040)  /* IPv4 Packet Received */
 
+#define ETH_DMAPTPRxDesc_IPCB  ((uint32_t)0x00000020)  /* IP Checksum Bypassed */
 
+#define ETH_DMAPTPRxDesc_IPPE  ((uint32_t)0x00000010)  /* IP Payload Error */
 
+#define ETH_DMAPTPRxDesc_IPHE  ((uint32_t)0x00000008)  /* IP Header Error */
 
+#define ETH_DMAPTPRxDesc_IPPT  ((uint32_t)0x00000007)  /* IP Payload Type */
 
+  #define ETH_DMAPTPRxDesc_IPPT_UDP                 ((uint32_t)0x00000001)  /* UDP payload encapsulated in the IP datagram */
 
+  #define ETH_DMAPTPRxDesc_IPPT_TCP                 ((uint32_t)0x00000002)  /* TCP payload encapsulated in the IP datagram */ 
+  #define ETH_DMAPTPRxDesc_IPPT_ICMP                ((uint32_t)0x00000003)  /* ICMP payload encapsulated in the IP datagram */
 
+
 
+/* Bit definition of RDES6 register */
 
+#define ETH_DMAPTPRxDesc_RTSL  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp Low */
 
+
 
+/* Bit definition of RDES7 register */
 
+#define ETH_DMAPTPRxDesc_RTSH  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp High */
 
+
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                     Description of common PHY registers
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PHY_Read_write_Timeouts 
+  * @{
 
+  */ 
+#define PHY_READ_TO                     ((uint32_t)0x0004FFFF)
 
+#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PHY_Register_address 
+  * @{
 
+  */ 
+#define PHY_BCR                          0          /*!< Transceiver Basic Control Register */
 
+#define PHY_BSR                          1          /*!< Transceiver Basic Status Register */
 
+
 
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
 
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
 
+                             ((REG) == PHY_BSR) || \
 
+                             ((REG) == PHY_SR))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PHY_basic_Control_register 
+  * @{
 
+  */ 
+#define PHY_Reset                       ((uint16_t)0x8000)      /*!< PHY Reset */
 
+#define PHY_Loopback                    ((uint16_t)0x4000)      /*!< Select loop-back mode */
 
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)      /*!< Set the full-duplex mode at 100 Mb/s */
 
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)      /*!< Set the half-duplex mode at 100 Mb/s */
 
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)      /*!< Set the full-duplex mode at 10 Mb/s */
 
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)      /*!< Set the half-duplex mode at 10 Mb/s */
 
+#define PHY_AutoNegotiation             ((uint16_t)0x1000)      /*!< Enable auto-negotiation function */
 
+#define PHY_Restart_AutoNegotiation     ((uint16_t)0x0200)      /*!< Restart auto-negotiation function */
 
+#define PHY_Powerdown                   ((uint16_t)0x0800)      /*!< Select the power down mode */
 
+#define PHY_Isolate                     ((uint16_t)0x0400)      /*!< Isolate PHY from MII */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PHY_basic_status_register 
+  * @{
 
+  */ 
+#define PHY_AutoNego_Complete           ((uint16_t)0x0020)      /*!< Auto-Negotiation process completed */
 
+#define PHY_Linked_Status               ((uint16_t)0x0004)      /*!< Valid link established */
 
+#define PHY_Jabber_detection            ((uint16_t)0x0002)      /*!< Jabber condition detected */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                                  MAC defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+
 
+/** @defgroup ETH_AutoNegotiation 
+  * @{
 
+  */ 
+#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)
 
+#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
 
+                                     ((CMD) == ETH_AutoNegotiation_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_watchdog 
+  * @{
 
+  */ 
+#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)
 
+#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)
 
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
 
+                              ((CMD) == ETH_Watchdog_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Jabber 
+  * @{
 
+  */ 
+#define ETH_Jabber_Enable    ((uint32_t)0x00000000)
 
+#define ETH_Jabber_Disable   ((uint32_t)0x00400000)
 
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
 
+                            ((CMD) == ETH_Jabber_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Inter_Frame_Gap 
+  * @{
 
+  */ 
+#define ETH_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
 
+#define ETH_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
 
+#define ETH_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
 
+#define ETH_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
 
+#define ETH_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
 
+#define ETH_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
 
+#define ETH_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
 
+#define ETH_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
 
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_88Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_80Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_72Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_64Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_56Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_48Bit) || \
 
+                                     ((GAP) == ETH_InterFrameGap_40Bit))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Carrier_Sense 
+  * @{
 
+  */ 
+#define ETH_CarrierSense_Enable   ((uint32_t)0x00000000)
 
+#define ETH_CarrierSense_Disable  ((uint32_t)0x00010000)
 
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
 
+                                   ((CMD) == ETH_CarrierSense_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Speed 
+  * @{
 
+  */ 
+#define ETH_Speed_10M        ((uint32_t)0x00000000)
 
+#define ETH_Speed_100M       ((uint32_t)0x00004000)
 
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
 
+                             ((SPEED) == ETH_Speed_100M))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Receive_Own 
+  * @{
 
+  */ 
+#define ETH_ReceiveOwn_Enable     ((uint32_t)0x00000000)
 
+#define ETH_ReceiveOwn_Disable    ((uint32_t)0x00002000)
 
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
 
+                                 ((CMD) == ETH_ReceiveOwn_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Loop_Back_Mode 
+  * @{
 
+  */ 
+#define ETH_LoopbackMode_Enable        ((uint32_t)0x00001000)
 
+#define ETH_LoopbackMode_Disable       ((uint32_t)0x00000000)
 
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
 
+                                   ((CMD) == ETH_LoopbackMode_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Duplex_Mode 
+  * @{
 
+  */ 
+#define ETH_Mode_FullDuplex       ((uint32_t)0x00000800)
 
+#define ETH_Mode_HalfDuplex       ((uint32_t)0x00000000)
 
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
 
+                                  ((MODE) == ETH_Mode_HalfDuplex))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Checksum_Offload 
+  * @{
 
+  */ 
+#define ETH_ChecksumOffload_Enable     ((uint32_t)0x00000400)
 
+#define ETH_ChecksumOffload_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
 
+                                      ((CMD) == ETH_ChecksumOffload_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Retry_Transmission 
+  * @{
 
+  */ 
+#define ETH_RetryTransmission_Enable   ((uint32_t)0x00000000)
 
+#define ETH_RetryTransmission_Disable  ((uint32_t)0x00000200)
 
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
 
+                                        ((CMD) == ETH_RetryTransmission_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Automatic_Pad_CRC_Strip 
+  * @{
 
+  */ 
+#define ETH_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
 
+#define ETH_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
 
+                                            ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Back_Off_Limit 
+  * @{
 
+  */ 
+#define ETH_BackOffLimit_10  ((uint32_t)0x00000000)
 
+#define ETH_BackOffLimit_8   ((uint32_t)0x00000020)
 
+#define ETH_BackOffLimit_4   ((uint32_t)0x00000040)
 
+#define ETH_BackOffLimit_1   ((uint32_t)0x00000060)
 
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
 
+                                     ((LIMIT) == ETH_BackOffLimit_8) || \
 
+                                     ((LIMIT) == ETH_BackOffLimit_4) || \
 
+                                     ((LIMIT) == ETH_BackOffLimit_1))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Deferral_Check 
+  * @{
 
+  */
 
+#define ETH_DeferralCheck_Enable       ((uint32_t)0x00000010)
 
+#define ETH_DeferralCheck_Disable      ((uint32_t)0x00000000)
 
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
 
+                                    ((CMD) == ETH_DeferralCheck_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Receive_All 
+  * @{
 
+  */ 
+#define ETH_ReceiveAll_Enable     ((uint32_t)0x80000000)
 
+#define ETH_ReceiveAll_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
 
+                                 ((CMD) == ETH_ReceiveAll_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Source_Addr_Filter 
+  * @{
 
+  */ 
+#define ETH_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
 
+#define ETH_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
 
+#define ETH_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
 
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
 
+                                        ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
 
+                                        ((CMD) == ETH_SourceAddrFilter_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Pass_Control_Frames 
+  * @{
 
+  */ 
+#define ETH_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
 
+#define ETH_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
 
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
 
+                                     ((PASS) == ETH_PassControlFrames_ForwardAll) || \
 
+                                     ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Broadcast_Frames_Reception 
+  * @{
 
+  */ 
+#define ETH_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
 
+#define ETH_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
 
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
 
+                                                ((CMD) == ETH_BroadcastFramesReception_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Destination_Addr_Filter 
+  * @{
 
+  */ 
+#define ETH_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
 
+#define ETH_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
 
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
 
+                                                ((FILTER) == ETH_DestinationAddrFilter_Inverse))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Promiscuous_Mode 
+  * @{
 
+  */ 
+#define ETH_PromiscuousMode_Enable     ((uint32_t)0x00000001)
 
+#define ETH_PromiscuousMode_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
 
+                                      ((CMD) == ETH_PromiscuousMode_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Multicast_Frames_Filter 
+  * @{
 
+  */ 
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
 
+#define ETH_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
 
+#define ETH_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
 
+#define ETH_MulticastFramesFilter_None                ((uint32_t)0x00000010)
 
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
 
+                                                ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
 
+                                                ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
 
+                                                ((FILTER) == ETH_MulticastFramesFilter_None))
 
+                                                     
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Unicast_Frames_Filter 
+  * @{
 
+  */ 
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
 
+#define ETH_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
 
+#define ETH_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
 
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
 
+                                              ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
 
+                                              ((FILTER) == ETH_UnicastFramesFilter_Perfect))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Pause_Time 
+  * @{
 
+  */ 
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Zero_Quanta_Pause 
+  * @{
 
+  */ 
+#define ETH_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
 
+#define ETH_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
 
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZeroQuantaPause_Enable) || \
 
+                                        ((CMD) == ETH_ZeroQuantaPause_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Pause_Low_Threshold 
+  * @{
 
+  */ 
+#define ETH_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
 
+#define ETH_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
 
+#define ETH_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
 
+#define ETH_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
 
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
 
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
 
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
 
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Unicast_Pause_Frame_Detect 
+  * @{
 
+  */ 
+#define ETH_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
 
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
 
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
 
+                                                ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Receive_Flow_Control 
+  * @{
 
+  */ 
+#define ETH_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
 
+#define ETH_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
 
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
 
+                                         ((CMD) == ETH_ReceiveFlowControl_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Transmit_Flow_Control 
+  * @{
 
+  */ 
+#define ETH_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
 
+#define ETH_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
 
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
 
+                                          ((CMD) == ETH_TransmitFlowControl_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_VLAN_Tag_Comparison 
+  * @{
 
+  */ 
+#define ETH_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
 
+#define ETH_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
 
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
 
+                                                ((COMPARISON) == ETH_VLANTagComparison_16Bit))
 
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MAC_Flags 
+  * @{
 
+  */ 
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
 
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
 
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
 
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
 
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
 
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
 
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
 
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MAC_Interrupts 
+  * @{
 
+  */ 
+#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
 
+#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
 
+#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
 
+#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
 
+#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
 
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
 
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
 
+                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
 
+                               ((IT) == ETH_MAC_IT_PMT))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MAC_addresses 
+  * @{
 
+  */ 
+#define ETH_MAC_Address0     ((uint32_t)0x00000000)
 
+#define ETH_MAC_Address1     ((uint32_t)0x00000008)
 
+#define ETH_MAC_Address2     ((uint32_t)0x00000010)
 
+#define ETH_MAC_Address3     ((uint32_t)0x00000018)
 
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
 
+                                         ((ADDRESS) == ETH_MAC_Address1) || \
 
+                                         ((ADDRESS) == ETH_MAC_Address2) || \
 
+                                         ((ADDRESS) == ETH_MAC_Address3))
 
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
 
+                                        ((ADDRESS) == ETH_MAC_Address2) || \
 
+                                        ((ADDRESS) == ETH_MAC_Address3))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames 
+  * @{
 
+  */ 
+#define ETH_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
 
+#define ETH_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
 
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
 
+                                           ((FILTER) == ETH_MAC_AddressFilter_DA))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes 
+  * @{
 
+  */ 
+#define ETH_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
 
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
 
+                                       ((MASK) == ETH_MAC_AddressMask_Byte5) || \
 
+                                       ((MASK) == ETH_MAC_AddressMask_Byte4) || \
 
+                                       ((MASK) == ETH_MAC_AddressMask_Byte3) || \
 
+                                       ((MASK) == ETH_MAC_AddressMask_Byte2) || \
 
+                                       ((MASK) == ETH_MAC_AddressMask_Byte1))
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                      Ethernet DMA Descriptors defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Tx_descriptor_flags
 
+  * @{
 
+  */ 
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_IC) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_LS) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_FS) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_DC) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_DP) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_TTSE) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_TER) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_TCH) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_TTSS) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_IHE) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_ES) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_JT) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_FF) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_PCE) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_LCA) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_NC) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_LCO) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_EC) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_VF) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_CC) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_ED) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_UF) || \
 
+                                         ((FLAG) == ETH_DMATxDesc_DB))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Tx_descriptor_segment 
+  * @{
 
+  */ 
+#define ETH_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /*!< Last Segment */
 
+#define ETH_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /*!< First Segment */
 
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
 
+                                            ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
 
+  * @{
 
+  */ 
+#define ETH_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
 
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
 
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
 
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
 
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
 
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
 
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
 
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
 
+/** 
+  * @brief  ETH DMA Tx Desciptor buffer size
 
+  */ 
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Rx_descriptor_flags
 
+  * @{
 
+  */ 
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_AFM) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_ES) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_DE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_SAF) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_LE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_OE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_VLAN) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_FS) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_LS) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_LC) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_FT) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_RWT) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_RE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_DBE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_CE) || \
 
+                                         ((FLAG) == ETH_DMARxDesc_MAMPCE))
 
+
 
+/* ETHERNET DMA PTP Rx descriptor extended flags  --------------------------------*/
 
+#define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \
 
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPPT))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ 
+  * @{
 
+  */ 
+#define ETH_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
 
+#define ETH_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
 
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
 
+                                          ((BUFFER) == ETH_DMARxDesc_Buffer2))
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                           Ethernet DMA defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 
+  * @{
 
+  */ 
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
 
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
 
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
 
+                                               ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Receive_Store_Forward 
+  * @{
 
+  */ 
+#define ETH_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
 
+#define ETH_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
 
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
 
+                                           ((CMD) == ETH_ReceiveStoreForward_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Flush_Received_Frame 
+  * @{
 
+  */ 
+#define ETH_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
 
+#define ETH_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
 
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
 
+                                         ((CMD) == ETH_FlushReceivedFrame_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Transmit_Store_Forward 
+  * @{
 
+  */ 
+#define ETH_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
 
+#define ETH_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
 
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
 
+                                            ((CMD) == ETH_TransmitStoreForward_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Transmit_Threshold_Control 
+  * @{
 
+  */ 
+#define ETH_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
 
+#define ETH_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
 
+#define ETH_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
 
+#define ETH_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
 
+#define ETH_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
 
+#define ETH_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
 
+#define ETH_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
 
+#define ETH_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
 
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
 
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Forward_Error_Frames 
+  * @{
 
+  */ 
+#define ETH_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
 
+#define ETH_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
 
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
 
+                                          ((CMD) == ETH_ForwardErrorFrames_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Forward_Undersized_Good_Frames 
+  * @{
 
+  */ 
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
 
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)     
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
 
+                                                    ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Receive_Threshold_Control 
+  * @{
 
+  */ 
+#define ETH_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
 
+#define ETH_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
 
+#define ETH_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
 
+#define ETH_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
 
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
 
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
 
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
 
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Second_Frame_Operate 
+  * @{
 
+  */ 
+#define ETH_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
 
+#define ETH_SecondFrameOperate_Disable      ((uint32_t)0x00000000)  
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
 
+                                          ((CMD) == ETH_SecondFrameOperate_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Address_Aligned_Beats 
+  * @{
 
+  */ 
+#define ETH_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
 
+#define ETH_AddressAlignedBeats_Disable     ((uint32_t)0x00000000) 
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
 
+                                           ((CMD) == ETH_AddressAlignedBeats_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Fixed_Burst 
+  * @{
 
+  */ 
+#define ETH_FixedBurst_Enable     ((uint32_t)0x00010000)
 
+#define ETH_FixedBurst_Disable    ((uint32_t)0x00000000) 
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
 
+                                 ((CMD) == ETH_FixedBurst_Disable))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Rx_DMA_Burst_Length 
+  * @{
 
+  */ 
+#define ETH_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
 
+#define ETH_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
 
+#define ETH_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
 
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
 
+
 
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
 
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
 
+ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Tx_DMA_Burst_Length 
+  * @{
 
+  */ 
+#define ETH_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
 
+#define ETH_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
 
+#define ETH_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
 
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 
+
 
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
 
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
 
+/** 
+  * @brief  ETH DMA Descriptor SkipLength  
+  */ 
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Arbitration 
+  * @{
 
+  */ 
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
 
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
 
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
 
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
 
+#define ETH_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
 
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
 
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
 
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
 
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
 
+                                                       ((RATIO) == ETH_DMAArbitration_RxPriorTx))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Flags 
+  * @{
 
+  */ 
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
 
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
 
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
 
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
 
+#define ETH_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
 
+#define ETH_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
 
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
 
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
 
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
 
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
 
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
 
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
 
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
 
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
 
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
 
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
 
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
 
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
 
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
 
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
 
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
 
+
 
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
 
+                                   ((FLAG) == ETH_DMA_FLAG_T))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_Interrupts 
+  * @{
 
+  */ 
+#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
 
+#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
 
+#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
 
+#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
 
+#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
 
+#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
 
+#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
 
+#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
 
+#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
 
+#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
 
+#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
 
+#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
 
+#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
 
+#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
 
+#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
 
+#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
 
+#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
 
+#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
 
+
 
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
 
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
 
+                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
 
+                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
 
+                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
 
+                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
 
+                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
 
+                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
 
+                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
 
+                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_transmit_process_state_ 
+  * @{
 
+  */ 
+#define ETH_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
 
+#define ETH_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
 
+#define ETH_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
 
+#define ETH_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
 
+#define ETH_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /*!< Suspended - Tx Descriptor unavailable */
 
+#define ETH_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ETH_DMA_receive_process_state_ 
+  * @{
 
+  */ 
+#define ETH_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
 
+#define ETH_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
 
+#define ETH_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
 
+#define ETH_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /*!< Suspended - Rx Descriptor unavailable */
 
+#define ETH_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
 
+#define ETH_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /*!< Running - queuing the receive frame into host memory */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_DMA_overflow_ 
+  * @{
 
+  */ 
+#define ETH_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
 
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
 
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
 
+                                           ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                           Ethernet PMT defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_PMT_Flags 
+  * @{
 
+  */ 
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Pointer Reset */
 
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
 
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
 
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
 
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                           Ethernet MMC defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MMC_Tx_Interrupts 
+  * @{
 
+  */ 
+#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
 
+#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
 
+#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MMC_Rx_Interrupts 
+  * @{
 
+  */
 
+#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
 
+#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
 
+#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
 
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
 
+                           ((IT) != 0x00))
 
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
 
+                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
 
+                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_MMC_Registers 
+  * @{
 
+  */ 
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /*!< MMC CR register */
 
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /*!< MMC RIR register */
 
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /*!< MMC TIR register */
 
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /*!< MMC RIMR register */
 
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /*!< MMC TIMR register */ 
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /*!< MMC TGFSCCR register */
 
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /*!< MMC TGFMSCCR register */ 
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /*!< MMC TGFCR register */
 
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /*!< MMC RFCECR register */
 
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /*!< MMC RFAECR register */
 
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /*!< MMC RGUFCR register */
 
+
 
+/** 
+  * @brief  ETH MMC registers  
+  */ 
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
 
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
 
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
 
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
 
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
 
+                                  ((REG) == ETH_MMCRGUFCR)) 
+
 
+/**--------------------------------------------------------------------------**/
 
+/** 
+  * @brief                           Ethernet PTP defines
 
+  */ 
+/**--------------------------------------------------------------------------**/
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_PTP_time_update_method 
+  * @{
 
+  */ 
+#define ETH_PTP_FineUpdate        ((uint32_t)0x00000001)  /*!< Fine Update method */
 
+#define ETH_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /*!< Coarse Update method */
 
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
 
+                                   ((UPDATE) == ETH_PTP_CoarseUpdate))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ETH_PTP_Flags 
+  * @{
 
+  */ 
+#define ETH_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /*!< Addend Register Update */
 
+#define ETH_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /*!< Time Stamp Interrupt Trigger */
 
+#define ETH_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /*!< Time Stamp Update */
 
+#define ETH_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /*!< Time Stamp Initialize */
 
+
 
+#define ETH_PTP_FLAG_TSTTR        ((uint32_t)0x10000002)  /* Time stamp target time reached */
 
+#define ETH_PTP_FLAG_TSSO         ((uint32_t)0x10000001)  /* Time stamp seconds overflow */
 
+
 
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
 
+                                    ((FLAG) == ETH_PTP_FLAG_TSITE) || \
 
+                                    ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
 
+                                    ((FLAG) == ETH_PTP_FLAG_TSSTI) || \
 
+                                    ((FLAG) == ETH_PTP_FLAG_TSTTR) || \
 
+                                    ((FLAG) == ETH_PTP_FLAG_TSSO)) 
+
 
+/** 
+  * @brief  ETH PTP subsecond increment  
+  */ 
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ETH_PTP_time_sign 
+  * @{
 
+  */ 
+#define ETH_PTP_PositiveTime      ((uint32_t)0x00000000)  /*!< Positive time value */
 
+#define ETH_PTP_NegativeTime      ((uint32_t)0x80000000)  /*!< Negative time value */
 
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
 
+                                    ((SIGN) == ETH_PTP_NegativeTime))
 
+
 
+/** 
+  * @brief  ETH PTP time stamp low update  
+  */ 
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
 
+
 
+/** 
+  * @brief  ETH PTP registers  
+  */ 
+#define ETH_PTPTSCR     ((uint32_t)0x00000700)  /*!< PTP TSCR register */
 
+#define ETH_PTPSSIR     ((uint32_t)0x00000704)  /*!< PTP SSIR register */
 
+#define ETH_PTPTSHR     ((uint32_t)0x00000708)  /*!< PTP TSHR register */
 
+#define ETH_PTPTSLR     ((uint32_t)0x0000070C)  /*!< PTP TSLR register */
 
+#define ETH_PTPTSHUR    ((uint32_t)0x00000710)  /*!< PTP TSHUR register */
 
+#define ETH_PTPTSLUR    ((uint32_t)0x00000714)  /*!< PTP TSLUR register */
 
+#define ETH_PTPTSAR     ((uint32_t)0x00000718)  /*!< PTP TSAR register */
 
+#define ETH_PTPTTHR     ((uint32_t)0x0000071C)  /*!< PTP TTHR register */
 
+#define ETH_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
 
+
 
+#define ETH_PTPTSSR     ((uint32_t)0x00000728)  /* PTP TSSR register */
 
+
 
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
 
+                                   ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
 
+                                   ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
 
+                                   ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
 
+                                   ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) 
+
 
+/** 
+  * @brief  ETHERNET PTP clock  
+  */ 
+#define ETH_PTP_OrdinaryClock               ((uint32_t)0x00000000)  /* Ordinary Clock */
 
+#define ETH_PTP_BoundaryClock               ((uint32_t)0x00010000)  /* Boundary Clock */
 
+#define ETH_PTP_EndToEndTransparentClock    ((uint32_t)0x00020000)  /* End To End Transparent Clock */
 
+#define ETH_PTP_PeerToPeerTransparentClock  ((uint32_t)0x00030000)  /* Peer To Peer Transparent Clock */
 
+
 
+#define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \
 
+                          ((CLOCK) == ETH_PTP_BoundaryClock) || \
 
+                          ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \
 
+                                      ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock))
 
+/** 
+  * @brief  ETHERNET snapshot
 
+  */
 
+#define ETH_PTP_SnapshotMasterMessage          ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
 
+#define ETH_PTP_SnapshotEventMessage           ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
 
+#define ETH_PTP_SnapshotIPV4Frames             ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
 
+#define ETH_PTP_SnapshotIPV6Frames             ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
 
+#define ETH_PTP_SnapshotPTPOverEthernetFrames  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
 
+#define ETH_PTP_SnapshotAllReceivedFrames      ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
 
+
 
+#define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \
 
+                           ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \
 
+                           ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \
 
+                           ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \
 
+                           ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \
 
+                           ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames))
 
+
 
+/**
 
+  * @}
 
+  */ 
+/* ETHERNET MAC address offsets */
 
+#define ETH_MAC_ADDR_HBASE   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
 
+#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
 
+
 
+/* ETHERNET MACMIIAR register Mask */
 
+#define MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
 
+
 
+/* ETHERNET MACCR register Mask */
 
+#define MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
+
 
+/* ETHERNET MACFCR register Mask */
 
+#define MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
 
+
 
+
 
+/* ETHERNET DMAOMR register Mask */
 
+#define DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
 
+
 
+
 
+/* ETHERNET Remote Wake-up frame register length */
 
+#define ETH_WAKEUP_REGISTER_LENGTH      8
 
+
 
+/* ETHERNET Missed frames counter Shift */
 
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
 
+
 
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
 
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3
 
+
 
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
 
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16
 
+
 
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
 
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16
 
+
 
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
 
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16
 
+
 
+/* ETHERNET errors */
 
+#define  ETH_ERROR              ((uint32_t)0)
 
+#define  ETH_SUCCESS            ((uint32_t)1)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Exported_Macros
 
+  * @{
 
+  */ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ETH_Exported_Functions
 
+  * @{
 
+  */ 
+void ETH_DeInit(void);
 
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress);
 
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
 
+void ETH_SoftwareReset(void);
 
+FlagStatus ETH_GetSoftwareResetStatus(void);
 
+void  ETH_Start(void);
 
+uint32_t ETH_GetRxPktSize(ETH_DMADESCTypeDef *DMARxDesc);
 
+
 
+
 
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+ void ETH_EnhancedDescriptorCmd(FunctionalState NewState);
 
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+
 
+/** 
+  * @brief  PHY  
+  */ 
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg);
 
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
 
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState);
 
+
 
+/** 
+  * @brief  MAC  
+  */ 
+void ETH_MACTransmissionCmd(FunctionalState NewState);
 
+void ETH_MACReceptionCmd(FunctionalState NewState);
 
+FlagStatus ETH_GetFlowControlBusyStatus(void);
 
+void ETH_InitiatePauseControlFrame(void);  
+void ETH_BackPressureActivationCmd(FunctionalState NewState); 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);  
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
 
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
 
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr);
 
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr);
 
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
 
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
 
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
 
+
 
+/** 
+  * @brief  DMA Tx/Rx descriptors  
+  */ 
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
 
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
 
+uint32_t ETH_CheckFrameReceived(void);
 
+uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength);
 
+FrameTypeDef ETH_Get_Received_Frame(void);
 
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
 
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
 
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
 
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
 
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
 
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
 
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
 
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
 
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
 
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
 
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
 
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
 
+ FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag);
 
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
 
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
 
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
 
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
 
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
 
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
 
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
 
+/** 
+  * @brief  DMA
 
+  */ 
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
 
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
 
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
 
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
 
+uint32_t ETH_GetTransmitProcessState(void);
 
+uint32_t ETH_GetReceiveProcessState(void);
 
+void ETH_FlushTransmitFIFO(void);
 
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
 
+void ETH_DMATransmissionCmd(FunctionalState NewState);
 
+void ETH_DMAReceptionCmd(FunctionalState NewState);
 
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
 
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
 
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
 
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
 
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
 
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
 
+uint32_t ETH_GetCurrentTxBufferAddress(void);
 
+uint32_t ETH_GetCurrentRxBufferAddress(void);
 
+void ETH_ResumeDMATransmission(void);
 
+void ETH_ResumeDMAReception(void);
 
+void ETH_SetReceiveWatchdogTimer(uint8_t Value);
 
+
 
+
 
+/** 
+  * @brief  PMT  
+  */ 
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
 
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
 
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
 
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
 
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
 
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
 
+void ETH_PowerDownCmd(FunctionalState NewState);
 
+
 
+/** 
+  * @brief  MMC  
+  */ 
+void ETH_MMCCounterFullPreset(void);
 
+void ETH_MMCCounterHalfPreset(void);
 
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
 
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
 
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
 
+void ETH_MMCCountersReset(void);
 
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
 
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
 
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4x7_ETH_H */
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/*********** Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.*****END OF FILE****/

+ 236 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth_bsp.c
Ver arquivo 

@@ -0,0 +1,236 @@
 
+/**

+  ******************************************************************************

+  * @file    stm32f4x7_eth_bsp.c

+  * @author  MCD Application Team

+  * @version V1.0.0

+  * @date    31-October-2011 

+  * @brief   STM32F4x7 Ethernet hardware configuration.

+  ******************************************************************************

+  * @attention

+  *

+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+  *

+  * <h2><center>&copy; Portions COPYRIGHT 2011 STMicroelectronics</center></h2>

+  ******************************************************************************

+  */

+/**

+  ******************************************************************************

+  * <h2><center>&copy; Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.</center></h2>

+  * @file    stm32f4x7_eth_bsp.c

+  * @author  CMP Team

+  * @version V1.0.0

+  * @date    28-December-2012

+  * @brief   STM32F4x7 Ethernet hardware configuration.      

+  *          Modified to support the STM32F4DISCOVERY, STM32F4DIS-BB and

+  *          STM32F4DIS-LCD modules. 

+  ******************************************************************************

+  * @attention

+  *

+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

+  * TIME. AS A RESULT, Embest SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT

+  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT

+  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION

+  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+  ******************************************************************************

+  */

+/* Includes ------------------------------------------------------------------*/

+#include "stm32f4x7_eth.h"

+#include "stm32f4x7_eth_bsp.h"

+#include "main.h"

+

+/* Private typedef -----------------------------------------------------------*/

+/* Private define ------------------------------------------------------------*/

+/* Private macro -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+__IO uint32_t  EthInitStatus = 0;

+

+/* Private function prototypes -----------------------------------------------*/

+static void ETH_GPIO_Config(void);

+static void ETH_MACDMA_Config(void);

+

+/* Private functions ---------------------------------------------------------*/

+

+/**

+  * @brief  ETH_BSP_Config

+  * @param  None

+  * @retval None

+  */

+void ETH_BSP_Config(void)

+{

+  /* Configure the GPIO ports for ethernet pins */

+  ETH_GPIO_Config();

+  

+  /* Config NVIC for Ethernet */

+  //ETH_NVIC_Config();

+

+  /* Configure the Ethernet MAC/DMA */

+  ETH_MACDMA_Config();

+

+  if (EthInitStatus == 0) {

+    // LCD_SetTextColor(LCD_COLOR_RED);

+    // LCD_DisplayStringLine(Line5, (uint8_t*)"   Ethernet Init   ");

+    // LCD_DisplayStringLine(Line6, (uint8_t*)"      failed      ");

+    // STM_EVAL_LEDOn(LED5);

+    while(1);

+  }

+}

+

+/**

+  * @brief  Configures the Ethernet Interface

+  * @param  None

+  * @retval None

+  */

+static void ETH_MACDMA_Config(void)

+{

+  ETH_InitTypeDef ETH_InitStructure;

+

+  /* Enable ETHERNET clock  */

+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |

+                         RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);                                             

+

+  /* Reset ETHERNET on AHB Bus */

+  ETH_DeInit();

+

+  /* Software reset */

+  ETH_SoftwareReset();

+

+  /* Wait for software reset */

+  while (ETH_GetSoftwareResetStatus() == SET);

+

+  /* ETHERNET Configuration --------------------------------------------------*/

+  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */

+  ETH_StructInit(&ETH_InitStructure);

+

+  /* Fill ETH_InitStructure parametrs */

+  /*------------------------   MAC   -----------------------------------*/

+  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;

+  //ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; 

+  //  ETH_InitStructure.ETH_Speed = ETH_Speed_10M;

+  //  ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;   

+

+  ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;

+  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;

+  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;

+  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;

+  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;

+  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;

+  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;

+  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;

+#ifdef CHECKSUM_BY_HARDWARE

+  ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;

+#endif

+

+  /*------------------------   DMA   -----------------------------------*/  

+  

+  /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 

+  the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 

+  if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */

+  ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; 

+  ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         

+  ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     

+ 

+  ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       

+  ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   

+  ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;

+  ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      

+  ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                

+  ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          

+  ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;

+  ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;

+

+  /* Configure Ethernet */

+  EthInitStatus = ETH_Init(&ETH_InitStructure, LAN8720_PHY_ADDRESS);

+

+  /* Enable the Ethernet Rx Interrupt */

+  ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);

+}

+

+

+/**

+  * @brief  Configures the different GPIO ports.

+  * @param  None

+  * @retval None

+  */

+void ETH_GPIO_Config(void)

+{

+  volatile uint32_t i;

+  GPIO_InitTypeDef GPIO_InitStructure;

+  

+  /* Enable GPIOs clocks */

+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB

+	                       | RCC_AHB1Periph_GPIOC, ENABLE);

+

+  /* Enable SYSCFG clock */

+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);  

+  

+  /* MII/RMII Media interface selection --------------------------------------*/

+  SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);

+

+

+/* Ethernet pins configuration ************************************************/

+   /*

+        ETH_MDIO --------------> PA2 +

+        ETH_MDC ---------------> PC1 +

+    

+        ETH_RMII_REF_CLK-------> PA1 +

+

+        ETH_RMII_CRS_DV -------> PA7 +

+	ETH_MII_RX_ER   -------> PB10 -

+        ETH_RMII_RXD0   -------> PC4 +

+        ETH_RMII_RXD1   -------> PC5 +

+        ETH_RMII_TX_EN  -------> PB11 + 

+        ETH_RMII_TXD0   -------> PB12 +

+        ETH_RMII_TXD1   -------> PB13 +

+

+        ETH_RST_PIN     -------> PE2  - замена на PE13

+  

+   */

+

+  /* Configure PA1,PA2 and PA7 */

+  GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;

+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;

+  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;

+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;

+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL ;

+  GPIO_Init(GPIOA, &GPIO_InitStructure);

+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);

+

+  /* Configure PB10,PB11,PB12 and PB13 */

+  GPIO_InitStructure.GPIO_Pin = /* GPIO_Pin_10 | */ GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;

+  GPIO_Init(GPIOB, &GPIO_InitStructure);

+  //GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_ETH);	

+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);

+

+  /* Configure PC1, PC4 and PC5 */

+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;

+  GPIO_Init(GPIOC, &GPIO_InitStructure);

+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);

+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);

+

+  /* Configure the PHY RST  pin */

+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;

+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;

+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;

+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;

+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

+  GPIO_Init(GPIOE, &GPIO_InitStructure);

+

+  GPIO_ResetBits(GPIOE, GPIO_Pin_13);	

+  for (i = 0; i < 20000; i++);

+  GPIO_SetBits(GPIOE, GPIO_Pin_13);

+  for (i = 0; i < 20000; i++);

+}

+

+

+/*********** Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.*****END OF FILE****/

+ 68 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth_bsp.h
Ver arquivo 

@@ -0,0 +1,68 @@
 
+/**

+  ******************************************************************************

+  * @file    stm32f4x7_eth_bsp.h

+  * @author  MCD Application Team

+  * @version V1.0.0

+  * @date    31-October-2011 

+  * @brief   Header for stm32f4x7_eth_bsp.c file.

+  ******************************************************************************

+  * @attention

+  *

+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+  *

+  * <h2><center>&copy; Portions COPYRIGHT 2011 STMicroelectronics</center></h2>

+  ******************************************************************************

+  */

+/**

+  ******************************************************************************

+  * <h2><center>&copy; Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.</center></h2>

+  * @file    stm32f4x7_eth_bsp.h

+  * @author  CMP Team

+  * @version V1.0.0

+  * @date    28-December-2012

+  * @brief   Header for stm32f4x7_eth_bsp.c file.       

+  *          Modified to support the STM32F4DISCOVERY, STM32F4DIS-BB and

+  *          STM32F4DIS-LCD modules. 

+  ******************************************************************************

+  * @attention

+  *

+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

+  * TIME. AS A RESULT, Embest SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT

+  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT

+  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION

+  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+  ******************************************************************************

+  */

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32F4x7_ETH_BSP_H

+#define __STM32F4x7_ETH_BSP_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32f4xx.h"

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+#define LAN8720_PHY_ADDRESS       0x01 /* Relative to STM324xG-EVAL Board */

+

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions ------------------------------------------------------- */

+void  ETH_BSP_Config(void);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32F4x7_ETH_BSP_H */

+

+

+/*********** Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.*****END OF FILE****/

+ 113 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth_conf.h
Ver arquivo 

@@ -0,0 +1,113 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4x7_eth_conf.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.0
 
+  * @date    31-October-2011
 
+  * @brief   Configuration file for the STM32F4x7 Ethernet driver. 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  *
 
+  * <h2><center>&copy; Portions COPYRIGHT 2011 STMicroelectronics</center></h2>
 
+  ******************************************************************************
 
+  */
 
+/**
 
+  ******************************************************************************
 
+  * <h2><center>&copy; Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.</center></h2>
 
+  * @file    stm32f4x7_eth_conf.h
 
+  * @author  CMP Team
 
+  * @version V1.0.0
 
+  * @date    28-December-2012
 
+  * @brief   Configuration file for the STM32F4x7 Ethernet driver.       
+  *          Modified to support the STM32F4DISCOVERY, STM32F4DIS-BB and
 
+  *          STM32F4DIS-LCD modules. 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, Embest SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
 
+  * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
 
+  * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
 
+  * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  ******************************************************************************
 
+  */
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4x7_ETH_CONF_H
 
+#define __STM32F4x7_ETH_CONF_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/* Uncomment the line below when using time stamping and/or IPv4 checksum offload */
 
+#define USE_ENHANCED_DMA_DESCRIPTORS
 
+
 
+/* Uncomment the line below if you want to use user defined Delay function
 
+   (for precise timing), otherwise default _eth_delay_ function defined within
 
+   the Ethernet driver is used (less precise timing) */
 
+//#define USE_Delay
 
+
 
+#ifdef USE_Delay
 
+  #include "main.h"                /* Header file where the Delay function prototype is exported */  
+  #define _eth_delay_    Delay     /* User can provide more timing precise _eth_delay_ function */
 
+#else
 
+  #define _eth_delay_    ETH_Delay /* Default _eth_delay_ function with less precise timing */
 
+#endif
 
+
 
+
 
+/* Uncomment the line below to allow custom configuration of the Ethernet driver buffers */    
+//#define CUSTOM_DRIVER_BUFFERS_CONFIG   
+
 
+#ifdef  CUSTOM_DRIVER_BUFFERS_CONFIG
 
+/* Redefinition of the Ethernet driver buffers size and count */   
+ #define ETH_RX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for receive */
 
+ #define ETH_TX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for transmit */
 
+ #define ETH_RXBUFNB        20                  /* 20 Rx buffers of size ETH_RX_BUF_SIZE */
 
+ #define ETH_TXBUFNB        5                   /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
 
+#endif
 
+
 
+
 
+/* PHY configuration section **************************************************/
 
+/* PHY Reset delay */ 
+#define PHY_RESET_DELAY    ((uint32_t)0x000FFFFF) 
+/* PHY Configuration delay */ 
+#define PHY_CONFIG_DELAY   ((uint32_t)0x00FFFFFF)
 
+
 
+/* The PHY status register value change from a PHY to another, so the user have 
+   to update this value depending on the used external PHY */
 
+#define PHY_SR    ((uint16_t)31) /* Value for DP83848 PHY */
 
+
 
+/* The Speed and Duplex mask values change from a PHY to another, so the user
 
+   have to update this value depending on the used external PHY */
 
+#define PHY_DUPLEX_SPEED_STATUS_MASK  ((uint16_t)0x001C)
 
+#define PHY_100BTX_FULL               (18)
 
+#define PHY_100BTX_HALF								(8)
 
+#define PHY_10M_FULL									(14)
 
+#define PHY_10M_HALF									(4)
 
+   
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions ------------------------------------------------------- */  
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4x7_ETH_CONF_H */
 
+
 
+
 
+/*********** Portions COPYRIGHT 2012 Embest Tech. Co., Ltd.*****END OF FILE****/
 
+

+ 92 - 0
stm32/stm32f4x7_ethernet/stm32f4x7_eth_conf_template.h
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+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4x7_eth_conf_template.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.0
 
+  * @date    14-October-2011
 
+  * @brief   Configuration file for the STM32F407xx/417xx Ethernet driver.
 
+  *          This file should be copied to the application folder and renamed to
 
+  *          stm32f4x7_eth_conf.h    
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
 
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
 
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
 
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
 
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
 
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4x7_ETH_CONF_H
 
+#define __STM32F4x7_ETH_CONF_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/* Uncomment the line below when using time stamping and/or IPv4 checksum offload */
 
+#define USE_ENHANCED_DMA_DESCRIPTORS
 
+
 
+/* Uncomment the line below if you want to use user defined Delay function
 
+   (for precise timing), otherwise default _eth_delay_ function defined within
 
+   the Ethernet driver is used (less precise timing) */
 
+//#define USE_Delay
 
+
 
+#ifdef USE_Delay
 
+  #include "main.h"                /* Header file where the Delay function prototype is exported */  
+  #define _eth_delay_    Delay     /* User can provide more timing precise _eth_delay_ function */
 
+#else
 
+  #define _eth_delay_    ETH_Delay /* Default _eth_delay_ function with less precise timing */
 
+#endif
 
+
 
+/* Uncomment the line below to allow custom configuration of the Ethernet driver buffers */    
+//#define CUSTOM_DRIVER_BUFFERS_CONFIG   
+
 
+#ifdef  CUSTOM_DRIVER_BUFFERS_CONFIG
 
+/* Redefinition of the Ethernet driver buffers size and count */   
+ #define ETH_RX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for receive */
 
+ #define ETH_TX_BUF_SIZE    ETH_MAX_PACKET_SIZE /* buffer size for transmit */
 
+ #define ETH_RXBUFNB        20                  /* 20 Rx buffers of size ETH_RX_BUF_SIZE */
 
+ #define ETH_TXBUFNB        5                   /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
 
+#endif
 
+
 
+
 
+/* PHY configuration section **************************************************/
 
+/* PHY Reset delay */ 
+#define PHY_RESET_DELAY    ((uint32_t)0x000FFFFF) 
+/* PHY Configuration delay */ 
+#define PHY_CONFIG_DELAY   ((uint32_t)0x00FFFFFF)
 
+
 
+/* The PHY status register value change from a PHY to another, so the user have 
+   to update this value depending on the used external PHY */
 
+#define PHY_SR    ((uint16_t)16) /* Value for DP83848 PHY */
 
+
 
+/* The Speed and Duplex mask values change from a PHY to another, so the user
 
+   have to update this value depending on the used external PHY */
 
+#define PHY_SPEED_STATUS            ((uint16_t)0x0002) /* Value for DP83848 PHY */
 
+#define PHY_DUPLEX_STATUS           ((uint16_t)0x0004) /* Value for DP83848 PHY */
 
+
 
+   
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions ------------------------------------------------------- */  
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4x7_ETH_CONF_H */
 
+
 
+
 
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
 
+

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stm32/stm32f4xx_spl/Release_Notes.html


+ 178 - 0
stm32/stm32f4xx_spl/inc/misc.h
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+/**
 
+  ******************************************************************************
 
+  * @file    misc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the miscellaneous
 
+  *          firmware library functions (add-on to CMSIS functions).
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __MISC_H
 
+#define __MISC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup MISC
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
 
+                                                   This parameter can be an enumerator of @ref IRQn_Type 
+                                                   enumeration (For the complete STM32 Devices IRQ Channels
 
+                                                   list, please refer to stm32f4xx.h file) */
 
+
 
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
 
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
 
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
 
+                                                   A lower priority value indicates a higher priority */
 
+
 
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
 
+                                                   in NVIC_IRQChannel. This parameter can be a value
 
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
 
+                                                   A lower priority value indicates a higher priority */
 
+
 
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
 
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
 
+ 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup MISC_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
 
+  */
 
+
 
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
 
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
 
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
 
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup MISC_System_Low_Power 
+  * @{
 
+  */
 
+
 
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
 
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
 
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
 
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
 
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
 
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
 
+  */
 
+
 
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
 
+                                                            4 bits for subpriority */
 
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
 
+                                                            3 bits for subpriority */
 
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
 
+                                                            2 bits for subpriority */
 
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
 
+                                                            1 bits for subpriority */
 
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
 
+                                                            0 bits for subpriority */
 
+
 
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
 
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
 
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
 
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
 
+                                       ((GROUP) == NVIC_PriorityGroup_4))
 
+
 
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
 
+
 
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
 
+
 
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
 
+  */
 
+
 
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
 
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
 
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
 
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+
 
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
 
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
 
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
 
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
 
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __MISC_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 649 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_adc.h
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+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_adc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_ADC_H
 
+#define __STM32F4xx_ADC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup ADC
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief   ADC Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
+                                               This parameter can be a value of @ref ADC_resolution */                                   
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
+                                               is performed in Scan (multichannels) 
+                                               or Single (one channel) mode.
 
+                                               This parameter can be set to ENABLE or DISABLE */ 
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
+                                               is performed in Continuous or Single mode.
 
+                                               This parameter can be set to ENABLE or DISABLE. */
 
+  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
 
+                                               enable the trigger of a regular group. 
+                                               This parameter can be a value of 
+                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
 
+  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
+                                               the start of conversion of a regular group.
 
+                                               This parameter can be a value of 
+                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
 
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
 
+                                               is left or right. This parameter can be 
+                                               a value of @ref ADC_data_align */
 
+  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
 
+                                               that will be done using the sequencer for
 
+                                               regular channel group.
 
+                                               This parameter must range from 1 to 16. */
 
+}ADC_InitTypeDef;
 
+  
+/** 
+  * @brief   ADC Common Init structure definition  
+  */ 
+typedef struct 
+{
 
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
+                                               independent or multi mode. 
+                                               This parameter can be a value of @ref ADC_Common_mode */                                              
+  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
+                                               to the ADC. The clock is common for all the ADCs.
 
+                                               This parameter can be a value of @ref ADC_Prescaler */
 
+  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
+                                              mode for multi ADC mode.
 
+                                               This parameter can be a value of 
+                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
 
+  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
 
+                                               This parameter can be a value of 
+                                               @ref ADC_delay_between_2_sampling_phases */
 
+  
+}ADC_CommonInitTypeDef;
 
+
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup ADC_Exported_Constants
 
+  * @{
 
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
 
+                                   ((PERIPH) == ADC2) || \
 
+                                   ((PERIPH) == ADC3))  
+
 
+/** @defgroup ADC_Common_mode 
+  * @{
 
+  */ 
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
+#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
 
+#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
 
+#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
 
+#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
 
+#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
 
+#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
 
+#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
 
+#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
 
+#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
 
+#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
 
+#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
 
+#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
 
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
 
+                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
 
+                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
 
+                           ((MODE) == ADC_DualMode_InjecSimult) || \
 
+                           ((MODE) == ADC_DualMode_RegSimult) || \
 
+                           ((MODE) == ADC_DualMode_Interl) || \
 
+                           ((MODE) == ADC_DualMode_AlterTrig) || \
 
+                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
 
+                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
 
+                           ((MODE) == ADC_TripleMode_InjecSimult) || \
 
+                           ((MODE) == ADC_TripleMode_RegSimult) || \
 
+                           ((MODE) == ADC_TripleMode_Interl) || \
 
+                           ((MODE) == ADC_TripleMode_AlterTrig))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_Prescaler 
+  * @{
 
+  */ 
+#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
 
+#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
 
+#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
 
+#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
 
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
 
+                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
 
+                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
 
+                                     ((PRESCALER) == ADC_Prescaler_Div8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
+  * @{
 
+  */ 
+#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
 
+#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
 
+#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
 
+#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
 
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
 
+                                      ((MODE) == ADC_DMAAccessMode_1) || \
 
+                                      ((MODE) == ADC_DMAAccessMode_2) || \
 
+                                      ((MODE) == ADC_DMAAccessMode_3))
 
+                                     
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_delay_between_2_sampling_phases 
+  * @{
 
+  */ 
+#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
 
+#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
 
+#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
 
+#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
 
+#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
 
+#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
 
+#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
 
+#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
 
+#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
 
+#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
 
+#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
 
+#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
 
+#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
 
+#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
 
+#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
 
+#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
 
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
 
+                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
 
+                                     
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_resolution 
+  * @{
 
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
 
+#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
 
+#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
 
+#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
 
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
 
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
 
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
 
+                                       ((RESOLUTION) == ADC_Resolution_6b))
 
+                                      
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
 
+  */ 
+#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
 
+#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
 
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
 
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
 
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
 
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
 
+                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
+  * @{
 
+  */ 
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
 
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
 
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
 
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
 
+#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
 
+#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
 
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
 
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
 
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
 
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
 
+#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
 
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
 
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
 
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
 
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
 
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
 
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_data_align 
+  * @{
 
+  */ 
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
 
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
 
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
 
+                                  ((ALIGN) == ADC_DataAlign_Left))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_channels 
+  * @{
 
+  */ 
+#define ADC_Channel_0                               ((uint8_t)0x00)
 
+#define ADC_Channel_1                               ((uint8_t)0x01)
 
+#define ADC_Channel_2                               ((uint8_t)0x02)
 
+#define ADC_Channel_3                               ((uint8_t)0x03)
 
+#define ADC_Channel_4                               ((uint8_t)0x04)
 
+#define ADC_Channel_5                               ((uint8_t)0x05)
 
+#define ADC_Channel_6                               ((uint8_t)0x06)
 
+#define ADC_Channel_7                               ((uint8_t)0x07)
 
+#define ADC_Channel_8                               ((uint8_t)0x08)
 
+#define ADC_Channel_9                               ((uint8_t)0x09)
 
+#define ADC_Channel_10                              ((uint8_t)0x0A)
 
+#define ADC_Channel_11                              ((uint8_t)0x0B)
 
+#define ADC_Channel_12                              ((uint8_t)0x0C)
 
+#define ADC_Channel_13                              ((uint8_t)0x0D)
 
+#define ADC_Channel_14                              ((uint8_t)0x0E)
 
+#define ADC_Channel_15                              ((uint8_t)0x0F)
 
+#define ADC_Channel_16                              ((uint8_t)0x10)
 
+#define ADC_Channel_17                              ((uint8_t)0x11)
 
+#define ADC_Channel_18                              ((uint8_t)0x12)
 
+
 
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
 
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
 
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
 
+
 
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
 
+                                 ((CHANNEL) == ADC_Channel_1) || \
 
+                                 ((CHANNEL) == ADC_Channel_2) || \
 
+                                 ((CHANNEL) == ADC_Channel_3) || \
 
+                                 ((CHANNEL) == ADC_Channel_4) || \
 
+                                 ((CHANNEL) == ADC_Channel_5) || \
 
+                                 ((CHANNEL) == ADC_Channel_6) || \
 
+                                 ((CHANNEL) == ADC_Channel_7) || \
 
+                                 ((CHANNEL) == ADC_Channel_8) || \
 
+                                 ((CHANNEL) == ADC_Channel_9) || \
 
+                                 ((CHANNEL) == ADC_Channel_10) || \
 
+                                 ((CHANNEL) == ADC_Channel_11) || \
 
+                                 ((CHANNEL) == ADC_Channel_12) || \
 
+                                 ((CHANNEL) == ADC_Channel_13) || \
 
+                                 ((CHANNEL) == ADC_Channel_14) || \
 
+                                 ((CHANNEL) == ADC_Channel_15) || \
 
+                                 ((CHANNEL) == ADC_Channel_16) || \
 
+                                 ((CHANNEL) == ADC_Channel_17) || \
 
+                                 ((CHANNEL) == ADC_Channel_18))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_sampling_times 
+  * @{
 
+  */ 
+#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
 
+#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
 
+#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
 
+#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
 
+#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
 
+#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
 
+#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
 
+#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
 
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_15Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_28Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_56Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_84Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_112Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_144Cycles) || \
 
+                                  ((TIME) == ADC_SampleTime_480Cycles))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
 
+  */ 
+#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
 
+#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
 
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
 
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
 
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
 
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
 
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
 
+                                            
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
+  * @{
 
+  */ 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
 
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
 
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
 
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
 
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
 
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
 
+#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
 
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
 
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_injected_channel_selection 
+  * @{
 
+  */ 
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
 
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
 
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
 
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
 
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
 
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
 
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
 
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
 
+  */ 
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
 
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
 
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
 
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
 
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
 
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
 
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
 
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
 
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_interrupts_definition 
+  * @{
 
+  */ 
+#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
+#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
+#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
+#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
 
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_flags_definition 
+  * @{
 
+  */ 
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
 
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
 
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
 
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
 
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
 
+#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
+  
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
 
+                               ((FLAG) == ADC_FLAG_EOC) || \
 
+                               ((FLAG) == ADC_FLAG_JEOC) || \
 
+                               ((FLAG)== ADC_FLAG_JSTRT) || \
 
+                               ((FLAG) == ADC_FLAG_STRT) || \
 
+                               ((FLAG)== ADC_FLAG_OVR))     
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_thresholds 
+  * @{
 
+  */ 
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_injected_offset 
+  * @{
 
+  */ 
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_injected_length 
+  * @{
 
+  */ 
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_injected_rank 
+  * @{
 
+  */ 
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_regular_length 
+  * @{
 
+  */ 
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_regular_rank 
+  * @{
 
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
 
+  */ 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/  
+
 
+/*  Function used to set the ADC configuration to the default reset state *****/  
+void ADC_DeInit(void);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
 
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
 
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
 
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
 
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+
 
+/* Analog Watchdog configuration functions ************************************/
 
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
 
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
 
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
 
+
 
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/
 
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
 
+void ADC_VBATCmd(FunctionalState NewState);
 
+
 
+/* Regular Channels Configuration functions ***********************************/
 
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
 
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
 
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
 
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
 
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
 
+uint32_t ADC_GetMultiModeConversionValue(void);
 
+
 
+/* Regular Channels DMA Configuration functions *******************************/
 
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
 
+
 
+/* Injected channels Configuration functions **********************************/
 
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
 
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
 
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
 
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
 
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
 
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
 
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
 
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
 
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
 
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
 
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
 
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
 
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_ADC_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 644 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_can.h
Ver arquivo 

@@ -0,0 +1,644 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_can.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_CAN_H
 
+#define __STM32F4xx_CAN_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup CAN
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
 
+                                   ((PERIPH) == CAN2))
 
+
 
+/** 
+  * @brief  CAN init structure definition
 
+  */
 
+typedef struct
 
+{
 
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
 
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
 
+                                 This parameter can be a value of @ref CAN_operating_mode */
 
+
 
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
 
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
 
+
 
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
 
+
 
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
 
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
 
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
 
+                                This parameter can be set either to ENABLE or DISABLE. */
 
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
 
+                                  This parameter can be set either to ENABLE or DISABLE. */
 
+
 
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
 
+
 
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
 
+                                  This parameter can be set either to ENABLE or DISABLE. */
 
+
 
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
 
+                                  This parameter can be set either to ENABLE or DISABLE. */
 
+
 
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
 
+                                  This parameter can be set either to ENABLE or DISABLE. */
 
+} CAN_InitTypeDef;
 
+
 
+/** 
+  * @brief  CAN filter init structure definition
 
+  */
 
+typedef struct
 
+{
 
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
 
+                                              configuration, first one for a 16-bit configuration).
 
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
 
+                                              configuration, second one for a 16-bit configuration).
 
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
 
+                                              according to the mode (MSBs for a 32-bit configuration,
 
+                                              first one for a 16-bit configuration).
 
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
 
+                                              according to the mode (LSBs for a 32-bit configuration,
 
+                                              second one for a 16-bit configuration).
 
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
 
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
 
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
 
+
 
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
 
+                                              This parameter can be a value of @ref CAN_filter_mode */
 
+
 
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
 
+                                              This parameter can be a value of @ref CAN_filter_scale */
 
+
 
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
 
+                                              This parameter can be set either to ENABLE or DISABLE. */
 
+} CAN_FilterInitTypeDef;
 
+
 
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
 
+typedef struct
 
+{
 
+  uint32_t StdId;  /*!< Specifies the standard identifier.
 
+                        This parameter can be a value between 0 to 0x7FF. */
 
+
 
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
 
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
 
+
 
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
 
+
 
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
 
+
 
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
 
+
 
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
 
+} CanTxMsg;
 
+
 
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
 
+typedef struct
 
+{
 
+  uint32_t StdId;  /*!< Specifies the standard identifier.
 
+                        This parameter can be a value between 0 to 0x7FF. */
 
+
 
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
 
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
 
+
 
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
 
+
 
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
 
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
 
+
 
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
 
+                        This parameter can be a value between 0 to 8 */
 
+
 
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
 
+
 
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
 
+} CanRxMsg;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup CAN_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CAN_InitStatus 
+  * @{
 
+  */
 
+
 
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
 
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
 
+
 
+
 
+/* Legacy defines */
 
+#define CANINITFAILED    CAN_InitStatus_Failed
 
+#define CANINITOK        CAN_InitStatus_Success
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_operating_mode 
+  * @{
 
+  */
 
+
 
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
 
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
 
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
 
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
 
+
 
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
 
+                           ((MODE) == CAN_Mode_LoopBack)|| \
 
+                           ((MODE) == CAN_Mode_Silent) || \
 
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+ /**
 
+  * @defgroup CAN_operating_mode 
+  * @{
 
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
 
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
 
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
 
+
 
+
 
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
 
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
 
+																		((MODE) == CAN_OperatingMode_Sleep))
 
+/**
 
+  * @}
 
+  */
 
+  
+/**
 
+  * @defgroup CAN_operating_mode_status
 
+  * @{
 
+  */  
+
 
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
 
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
 
+  */
 
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
 
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
 
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
 
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
 
+
 
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
 
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
 
+  */
 
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
 
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
 
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
 
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
 
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
 
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
 
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
 
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
 
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
 
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
 
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
 
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
 
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
 
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
 
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
 
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
 
+
 
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
 
+  */
 
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
 
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
 
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
 
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
 
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
 
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
 
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
 
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
 
+
 
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_clock_prescaler 
+  * @{
 
+  */
 
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_filter_number 
+  * @{
 
+  */
 
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_filter_mode 
+  * @{
 
+  */
 
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
 
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
 
+
 
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
 
+                                  ((MODE) == CAN_FilterMode_IdList))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_filter_scale 
+  * @{
 
+  */
 
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
 
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
 
+
 
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
 
+                                    ((SCALE) == CAN_FilterScale_32bit))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_filter_FIFO
 
+  * @{
 
+  */
 
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
 
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
 
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
 
+                                  ((FIFO) == CAN_FilterFIFO1))
 
+
 
+/* Legacy defines */
 
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
 
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
 
+  */
 
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_Tx 
+  * @{
 
+  */
 
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
 
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
 
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
 
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_identifier_type 
+  * @{
 
+  */
 
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
 
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
 
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
 
+                               ((IDTYPE) == CAN_Id_Extended))
 
+
 
+/* Legacy defines */
 
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_remote_transmission_request 
+  * @{
 
+  */
 
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
 
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
 
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
 
+
 
+/* Legacy defines */
 
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_transmit_constants 
+  * @{
 
+  */
 
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
 
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
 
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
 
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
 
+/* Legacy defines */	
+#define CANTXFAILED                  CAN_TxStatus_Failed
 
+#define CANTXOK                      CAN_TxStatus_Ok
 
+#define CANTXPENDING                 CAN_TxStatus_Pending
 
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
 
+  */
 
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
 
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
 
+
 
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_sleep_constants 
+  * @{
 
+  */
 
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
 
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
 
+
 
+/* Legacy defines */	
+#define CANSLEEPFAILED   CAN_Sleep_Failed
 
+#define CANSLEEPOK       CAN_Sleep_Ok
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_wake_up_constants 
+  * @{
 
+  */
 
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
 
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
 
+
 
+/* Legacy defines */
 
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @defgroup CAN_Error_Code_constants
 
+  * @{
 
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_flags 
+  * @{
 
+  */
 
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
 
+   and CAN_ClearFlag() functions. */
 
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
 
+
 
+/* Transmit Flags */
 
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
 
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
 
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
 
+
 
+/* Receive Flags */
 
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
 
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
 
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
 
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
 
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
 
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
 
+
 
+/* Operating Mode Flags */
 
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
 
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
 
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
 
+
 
+/* Error Flags */
 
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
 
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
 
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
 
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
 
+
 
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
 
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
 
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
 
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
 
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
 
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
 
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
 
+                               ((FLAG) == CAN_FLAG_SLAK ))
 
+
 
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
 
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
 
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
 
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
 
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
 
+/**
 
+  * @}
 
+  */
 
+
 
+  
+/** @defgroup CAN_interrupts 
+  * @{
 
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
 
+
 
+/* Receive Interrupts */
 
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
 
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
 
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
 
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
 
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
 
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
 
+
 
+/* Operating Mode Interrupts */
 
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
 
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
 
+
 
+/* Error Interrupts */
 
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
 
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
 
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
 
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
 
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
 
+
 
+/* Flags named as Interrupts : kept only for FW compatibility */
 
+#define CAN_IT_RQCP0   CAN_IT_TME
 
+#define CAN_IT_RQCP1   CAN_IT_TME
 
+#define CAN_IT_RQCP2   CAN_IT_TME
 
+
 
+
 
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
 
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
 
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
 
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
 
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
 
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
 
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
 
+
 
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
 
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
 
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
 
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
 
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
 
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/  
+
 
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
 
+
 
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
 
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
 
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
 
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
 
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
 
+
 
+/* CAN Frames Transmission functions ******************************************/
 
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
 
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
 
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
 
+
 
+/* CAN Frames Reception functions *********************************************/
 
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
 
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
 
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
 
+
 
+/* Operation modes functions **************************************************/
 
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
 
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
 
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
 
+
 
+/* CAN Bus Error management functions *****************************************/
 
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
 
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
 
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
 
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
 
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
 
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
 
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_CAN_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 83 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_crc.h
Ver arquivo 

@@ -0,0 +1,83 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_crc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_CRC_H
 
+#define __STM32F4xx_CRC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup CRC
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup CRC_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/  
+
 
+void CRC_ResetDR(void);
 
+uint32_t CRC_CalcCRC(uint32_t Data);
 
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
 
+uint32_t CRC_GetCRC(void);
 
+void CRC_SetIDRegister(uint8_t IDValue);
 
+uint8_t CRC_GetIDRegister(void);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_CRC_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 344 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_cryp.h
Ver arquivo 

@@ -0,0 +1,344 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_cryp.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the Cryptographic
 
+  *          processor(CRYP) firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_CRYP_H
 
+#define __STM32F4xx_CRYP_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup CRYP
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief   CRYP Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint16_t CRYP_AlgoDir;   /*!< Encrypt or Decrypt. This parameter can be a 
+                                value of @ref CRYP_Algorithm_Direction */
 
+  uint16_t CRYP_AlgoMode;  /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, 
+                                AES-CBC, AES-CTR, AES-Key. This parameter can be
 
+                                a value of @ref CRYP_Algorithm_Mode */
 
+  uint16_t CRYP_DataType;  /*!< 32-bit data, 16-bit data, bit data or bit-string.
 
+                                This parameter can be a value of @ref CRYP_Data_Type */ 
+  uint16_t CRYP_KeySize;   /*!< Used only in AES mode only : 128, 192 or 256 bit 
+                                key length. This parameter can be a value of 
+                                @ref CRYP_Key_Size_for_AES_only */
 
+}CRYP_InitTypeDef;
 
+
 
+/** 
+  * @brief   CRYP Key(s) structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t CRYP_Key0Left;  /*!< Key 0 Left  */
 
+  uint32_t CRYP_Key0Right; /*!< Key 0 Right */
 
+  uint32_t CRYP_Key1Left;  /*!< Key 1 left  */
 
+  uint32_t CRYP_Key1Right; /*!< Key 1 Right */
 
+  uint32_t CRYP_Key2Left;  /*!< Key 2 left  */
 
+  uint32_t CRYP_Key2Right; /*!< Key 2 Right */
 
+  uint32_t CRYP_Key3Left;  /*!< Key 3 left  */
 
+  uint32_t CRYP_Key3Right; /*!< Key 3 Right */
 
+}CRYP_KeyInitTypeDef;
 
+/** 
+  * @brief   CRYP Initialization Vectors (IV) structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t CRYP_IV0Left;  /*!< Init Vector 0 Left  */
 
+  uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
 
+  uint32_t CRYP_IV1Left;  /*!< Init Vector 1 left  */
 
+  uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
 
+}CRYP_IVInitTypeDef;
 
+
 
+/** 
+  * @brief  CRYP context swapping structure definition  
+  */ 
+typedef struct
 
+{
 
+  /*!< Configuration */
 
+  uint32_t CR_bits9to2;
 
+  /*!< KEY */
 
+  uint32_t CRYP_IV0LR;
 
+  uint32_t CRYP_IV0RR;
 
+  uint32_t CRYP_IV1LR;
 
+  uint32_t CRYP_IV1RR;
 
+  /*!< IV */
 
+  uint32_t CRYP_K0LR;
 
+  uint32_t CRYP_K0RR;
 
+  uint32_t CRYP_K1LR;
 
+  uint32_t CRYP_K1RR;
 
+  uint32_t CRYP_K2LR;
 
+  uint32_t CRYP_K2RR;
 
+  uint32_t CRYP_K3LR;
 
+  uint32_t CRYP_K3RR;
 
+}CRYP_Context;
 
+
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup CRYP_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRYP_Algorithm_Direction 
+  * @{
 
+  */
 
+#define CRYP_AlgoDir_Encrypt      ((uint16_t)0x0000)
 
+#define CRYP_AlgoDir_Decrypt      ((uint16_t)0x0004)
 
+#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
 
+                                  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
 
+
 
+/**
 
+  * @}
 
+  */ 
+ 
+/** @defgroup CRYP_Algorithm_Mode 
+  * @{
 
+  */
 
+
 
+/*!< TDES Modes */
 
+#define CRYP_AlgoMode_TDES_ECB    ((uint16_t)0x0000)
 
+#define CRYP_AlgoMode_TDES_CBC    ((uint16_t)0x0008)
 
+
 
+/*!< DES Modes */
 
+#define CRYP_AlgoMode_DES_ECB     ((uint16_t)0x0010)
 
+#define CRYP_AlgoMode_DES_CBC     ((uint16_t)0x0018)
 
+
 
+/*!< AES Modes */
 
+#define CRYP_AlgoMode_AES_ECB     ((uint16_t)0x0020)
 
+#define CRYP_AlgoMode_AES_CBC     ((uint16_t)0x0028)
 
+#define CRYP_AlgoMode_AES_CTR     ((uint16_t)0x0030)
 
+#define CRYP_AlgoMode_AES_Key     ((uint16_t)0x0038)
 
+
 
+#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
 
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_Key))
 
+/**
 
+  * @}
 
+  */ 
+ 
+/** @defgroup CRYP_Data_Type 
+  * @{
 
+  */
 
+#define CRYP_DataType_32b         ((uint16_t)0x0000)
 
+#define CRYP_DataType_16b         ((uint16_t)0x0040)
 
+#define CRYP_DataType_8b          ((uint16_t)0x0080)
 
+#define CRYP_DataType_1b          ((uint16_t)0x00C0)
 
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
 
+                                    ((DATATYPE) == CRYP_DataType_16b)|| \
 
+                                    ((DATATYPE) == CRYP_DataType_8b)|| \
 
+                                    ((DATATYPE) == CRYP_DataType_1b))  
+/**
 
+  * @}
 
+  */
 
+                                     
+/** @defgroup CRYP_Key_Size_for_AES_only 
+  * @{
 
+  */
 
+#define CRYP_KeySize_128b         ((uint16_t)0x0000)
 
+#define CRYP_KeySize_192b         ((uint16_t)0x0100)
 
+#define CRYP_KeySize_256b         ((uint16_t)0x0200)
 
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
 
+                                  ((KEYSIZE) == CRYP_KeySize_192b)|| \
 
+                                  ((KEYSIZE) == CRYP_KeySize_256b))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_flags_definition 
+  * @{
 
+  */
 
+#define CRYP_FLAG_BUSY            ((uint8_t)0x10)  /*!< The CRYP core is currently 
+                                                        processing a block of data 
+                                                        or a key preparation (for 
+                                                        AES decryption). */
 
+#define CRYP_FLAG_IFEM            ((uint8_t)0x01)  /*!< Input Fifo Empty */
 
+#define CRYP_FLAG_IFNF            ((uint8_t)0x02)  /*!< Input Fifo is Not Full */
 
+#define CRYP_FLAG_INRIS           ((uint8_t)0x22)  /*!< Raw interrupt pending */
 
+#define CRYP_FLAG_OFNE            ((uint8_t)0x04)  /*!< Input Fifo service raw 
+                                                        interrupt status */
 
+#define CRYP_FLAG_OFFU            ((uint8_t)0x08)  /*!< Output Fifo is Full */
 
+#define CRYP_FLAG_OUTRIS          ((uint8_t)0x21)  /*!< Output Fifo service raw 
+                                                        interrupt status */
 
+
 
+#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  || \
 
+                                ((FLAG) == CRYP_FLAG_IFNF)  || \
 
+                                ((FLAG) == CRYP_FLAG_OFNE)  || \
 
+                                ((FLAG) == CRYP_FLAG_OFFU)  || \
 
+                                ((FLAG) == CRYP_FLAG_BUSY)  || \
 
+                                ((FLAG) == CRYP_FLAG_OUTRIS)|| \
 
+                                ((FLAG) == CRYP_FLAG_INRIS))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_interrupts_definition 
+  * @{
 
+  */
 
+#define CRYP_IT_INI               ((uint8_t)0x01) /*!< IN Fifo Interrupt */
 
+#define CRYP_IT_OUTI              ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
 
+#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
 
+#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_Encryption_Decryption_modes_definition 
+  * @{
 
+  */
 
+#define MODE_ENCRYPT             ((uint8_t)0x01)
 
+#define MODE_DECRYPT             ((uint8_t)0x00)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_DMA_transfer_requests 
+  * @{
 
+  */
 
+#define CRYP_DMAReq_DataIN             ((uint8_t)0x01)
 
+#define CRYP_DMAReq_DataOUT            ((uint8_t)0x02)
 
+#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+
 
+/*  Function used to set the CRYP configuration to the default reset state ****/
 
+void CRYP_DeInit(void);
 
+
 
+/* CRYP Initialization and Configuration functions ****************************/
 
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
 
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
 
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
 
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
 
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
 
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
 
+void CRYP_Cmd(FunctionalState NewState);
 
+
 
+/* CRYP Data processing functions *********************************************/
 
+void CRYP_DataIn(uint32_t Data);
 
+uint32_t CRYP_DataOut(void);
 
+void CRYP_FIFOFlush(void);
 
+
 
+/* CRYP Context swapping functions ********************************************/
 
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
 
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
 
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
 
+
 
+/* CRYP's DMA interface function **********************************************/
 
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
 
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
 
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
 
+
 
+/* High Level AES functions **************************************************/
 
+ErrorStatus CRYP_AES_ECB(uint8_t Mode,
 
+                         uint8_t *Key, uint16_t Keysize,
 
+                         uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output);
 
+
 
+ErrorStatus CRYP_AES_CBC(uint8_t Mode,
 
+                         uint8_t InitVectors[16],
 
+                         uint8_t *Key, uint16_t Keysize,
 
+                         uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output);
 
+
 
+ErrorStatus CRYP_AES_CTR(uint8_t Mode,
 
+                         uint8_t InitVectors[16],
 
+                         uint8_t *Key, uint16_t Keysize,
 
+                         uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output);
 
+
 
+/* High Level TDES functions **************************************************/
 
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
 
+                           uint8_t Key[24], 
+                           uint8_t *Input, uint32_t Ilength,
 
+                           uint8_t *Output);
 
+
 
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
 
+                          uint8_t Key[24],
 
+                          uint8_t InitVectors[8],
 
+                          uint8_t *Input, uint32_t Ilength,
 
+                          uint8_t *Output);
 
+
 
+/* High Level DES functions **************************************************/
 
+ErrorStatus CRYP_DES_ECB(uint8_t Mode,
 
+                         uint8_t Key[8],
 
+                         uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output);
 
+
 
+ErrorStatus CRYP_DES_CBC(uint8_t Mode,
 
+                         uint8_t Key[8],
 
+                         uint8_t InitVectors[8],
 
+                         uint8_t *Input,uint32_t Ilength,
 
+                         uint8_t *Output);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_CRYP_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 304 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_dac.h
Ver arquivo 

@@ -0,0 +1,304 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dac.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_DAC_H
 
+#define __STM32F4xx_DAC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup DAC
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  DAC Init structure definition
 
+  */
 
+
 
+typedef struct
 
+{
 
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
 
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
 
+
 
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
 
+                                                  are generated, or whether no wave is generated.
 
+                                                  This parameter can be a value of @ref DAC_wave_generation */
 
+
 
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
 
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
 
+
 
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
 
+                                                  This parameter can be a value of @ref DAC_output_buffer */
 
+}DAC_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup DAC_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DAC_trigger_selection 
+  * @{
 
+  */
 
+
 
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
 
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
 
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
 
+
 
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
 
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
 
+                                 ((TRIGGER) == DAC_Trigger_Software))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_wave_generation 
+  * @{
 
+  */
 
+
 
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
 
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
 
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
 
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
 
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
 
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_lfsrunmask_triangleamplitude
 
+  * @{
 
+  */
 
+
 
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
 
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
 
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
 
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
 
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
 
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
 
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
 
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
 
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
 
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
 
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
 
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
 
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
 
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
 
+
 
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
 
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
 
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_output_buffer 
+  * @{
 
+  */
 
+
 
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
 
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
 
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
 
+                                           ((STATE) == DAC_OutputBuffer_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_Channel_selection 
+  * @{
 
+  */
 
+
 
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
 
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
 
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
 
+                                 ((CHANNEL) == DAC_Channel_2))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_data_alignement 
+  * @{
 
+  */
 
+
 
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
 
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
 
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
 
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
 
+                             ((ALIGN) == DAC_Align_12b_L) || \
 
+                             ((ALIGN) == DAC_Align_8b_R))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_wave_generation 
+  * @{
 
+  */
 
+
 
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
 
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
 
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
 
+                           ((WAVE) == DAC_Wave_Triangle))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_data 
+  * @{
 
+  */
 
+
 
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
 
+  */   
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup DAC_flags_definition 
+  * @{
 
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/  
+
 
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
 
+
 
+/*  DAC channels configuration: trigger, output buffer, data format functions */
 
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
 
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
 
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
 
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
 
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
 
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
 
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
 
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
 
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
 
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
 
+
 
+/* DMA management functions ***************************************************/
 
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
 
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
 
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
 
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
 
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_DAC_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 109 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_dbgmcu.h
Ver arquivo 

@@ -0,0 +1,109 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dbgmcu.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_DBGMCU_H
 
+#define __STM32F4xx_DBGMCU_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup DBGMCU
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup DBGMCU_Exported_Constants
 
+  * @{
 
+  */ 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
 
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
 
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
 
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
 
+
 
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
 
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
 
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
 
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
 
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
 
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
 
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
 
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
 
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
 
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
 
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
 
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
 
+#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
 
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
 
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
 
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
 
+
 
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
 
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
 
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
 
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+uint32_t DBGMCU_GetREVID(void);
 
+uint32_t DBGMCU_GetDEVID(void);
 
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
 
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
 
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_DBGMCU_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 312 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_dcmi.h
Ver arquivo 

@@ -0,0 +1,312 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dcmi.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the DCMI firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_DCMI_H
 
+#define __STM32F4xx_DCMI_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup DCMI
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/** 
+  * @brief   DCMI Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint16_t DCMI_CaptureMode;      /*!< Specifies the Capture Mode: Continuous or Snapshot.
 
+                                       This parameter can be a value of @ref DCMI_Capture_Mode */
 
+
 
+  uint16_t DCMI_SynchroMode;      /*!< Specifies the Synchronization Mode: Hardware or Embedded.
 
+                                       This parameter can be a value of @ref DCMI_Synchronization_Mode */
 
+
 
+  uint16_t DCMI_PCKPolarity;      /*!< Specifies the Pixel clock polarity: Falling or Rising.
 
+                                       This parameter can be a value of @ref DCMI_PIXCK_Polarity */
 
+
 
+  uint16_t DCMI_VSPolarity;       /*!< Specifies the Vertical synchronization polarity: High or Low.
 
+                                       This parameter can be a value of @ref DCMI_VSYNC_Polarity */
 
+
 
+  uint16_t DCMI_HSPolarity;       /*!< Specifies the Horizontal synchronization polarity: High or Low.
 
+                                       This parameter can be a value of @ref DCMI_HSYNC_Polarity */
 
+
 
+  uint16_t DCMI_CaptureRate;      /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
 
+                                       This parameter can be a value of @ref DCMI_Capture_Rate */
 
+
 
+  uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
 
+                                       This parameter can be a value of @ref DCMI_Extended_Data_Mode */
 
+} DCMI_InitTypeDef;
 
+
 
+/** 
+  * @brief   DCMI CROP Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint16_t DCMI_VerticalStartLine;      /*!< Specifies the Vertical start line count from which the image capture
 
+                                             will start. This parameter can be a value between 0x00 and 0x1FFF */
 
+
 
+  uint16_t DCMI_HorizontalOffsetCount;  /*!< Specifies the number of pixel clocks to count before starting a capture.
 
+                                             This parameter can be a value between 0x00 and 0x3FFF */
 
+
 
+  uint16_t DCMI_VerticalLineCount;      /*!< Specifies the number of lines to be captured from the starting point.
 
+                                             This parameter can be a value between 0x00 and 0x3FFF */
 
+
 
+  uint16_t DCMI_CaptureCount;           /*!< Specifies the number of pixel clocks to be captured from the starting
 
+                                             point on the same line.
 
+                                             This parameter can be a value between 0x00 and 0x3FFF */
 
+} DCMI_CROPInitTypeDef;
 
+
 
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
 
+  uint8_t DCMI_LineStartCode;  /*!< Specifies the code of the line start delimiter. */
 
+  uint8_t DCMI_LineEndCode;    /*!< Specifies the code of the line end delimiter. */
 
+  uint8_t DCMI_FrameEndCode;   /*!< Specifies the code of the frame end delimiter. */
 
+} DCMI_CodesInitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup DCMI_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DCMI_Capture_Mode 
+  * @{
 
+  */ 
+#define DCMI_CaptureMode_Continuous    ((uint16_t)0x0000) /*!< The received data are transferred continuously 
+                                                               into the destination memory through the DMA */
 
+#define DCMI_CaptureMode_SnapShot      ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of 
+                                                               frame and then transfers a single frame through the DMA */
 
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
 
+                                   ((MODE) == DCMI_CaptureMode_SnapShot))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_Synchronization_Mode
 
+  * @{
 
+  */ 
+#define DCMI_SynchroMode_Hardware    ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
 
+                                                             is synchronized with the HSYNC/VSYNC signals */
 
+#define DCMI_SynchroMode_Embedded    ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with 
+                                                             synchronization codes embedded in the data flow */
 
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
 
+                              ((MODE) == DCMI_SynchroMode_Embedded))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_PIXCK_Polarity 
+  * @{
 
+  */ 
+#define DCMI_PCKPolarity_Falling    ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
 
+#define DCMI_PCKPolarity_Rising     ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
 
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
 
+                                      ((POLARITY) == DCMI_PCKPolarity_Rising))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_VSYNC_Polarity 
+  * @{
 
+  */ 
+#define DCMI_VSPolarity_Low     ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
 
+#define DCMI_VSPolarity_High    ((uint16_t)0x0080) /*!< Vertical synchronization active High */
 
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
 
+                                     ((POLARITY) == DCMI_VSPolarity_High))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_HSYNC_Polarity 
+  * @{
 
+  */ 
+#define DCMI_HSPolarity_Low     ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
 
+#define DCMI_HSPolarity_High    ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
 
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
 
+                                     ((POLARITY) == DCMI_HSPolarity_High))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_Capture_Rate 
+  * @{
 
+  */ 
+#define DCMI_CaptureRate_All_Frame     ((uint16_t)0x0000) /*!< All frames are captured */
 
+#define DCMI_CaptureRate_1of2_Frame    ((uint16_t)0x0100) /*!< Every alternate frame captured */
 
+#define DCMI_CaptureRate_1of4_Frame    ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
 
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
 
+                                    ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
 
+                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_Extended_Data_Mode 
+  * @{
 
+  */ 
+#define DCMI_ExtendedDataMode_8b     ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
 
+#define DCMI_ExtendedDataMode_10b    ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
 
+#define DCMI_ExtendedDataMode_12b    ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
 
+#define DCMI_ExtendedDataMode_14b    ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
 
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
 
+                                    ((DATA) == DCMI_ExtendedDataMode_10b) ||\
 
+                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||\
 
+                                    ((DATA) == DCMI_ExtendedDataMode_14b))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_interrupt_sources 
+  * @{
 
+  */ 
+#define DCMI_IT_FRAME    ((uint16_t)0x0001)
 
+#define DCMI_IT_OVF      ((uint16_t)0x0002)
 
+#define DCMI_IT_ERR      ((uint16_t)0x0004)
 
+#define DCMI_IT_VSYNC    ((uint16_t)0x0008)
 
+#define DCMI_IT_LINE     ((uint16_t)0x0010)
 
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
 
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
 
+                            ((IT) == DCMI_IT_OVF) || \
 
+                            ((IT) == DCMI_IT_ERR) || \
 
+                            ((IT) == DCMI_IT_VSYNC) || \
 
+                            ((IT) == DCMI_IT_LINE))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DCMI_Flags 
+  * @{
 
+  */ 
+/** 
+  * @brief   DCMI SR register  
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint16_t)0x2001)
 
+#define DCMI_FLAG_VSYNC     ((uint16_t)0x2002)
 
+#define DCMI_FLAG_FNE       ((uint16_t)0x2004)
 
+/** 
+  * @brief   DCMI RISR register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint16_t)0x0001)
 
+#define DCMI_FLAG_OVFRI      ((uint16_t)0x0002)
 
+#define DCMI_FLAG_ERRRI      ((uint16_t)0x0004)
 
+#define DCMI_FLAG_VSYNCRI    ((uint16_t)0x0008)
 
+#define DCMI_FLAG_LINERI     ((uint16_t)0x0010)
 
+/** 
+  * @brief   DCMI MISR register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint16_t)0x1001)
 
+#define DCMI_FLAG_OVFMI      ((uint16_t)0x1002)
 
+#define DCMI_FLAG_ERRMI      ((uint16_t)0x1004)
 
+#define DCMI_FLAG_VSYNCMI    ((uint16_t)0x1008)
 
+#define DCMI_FLAG_LINEMI     ((uint16_t)0x1010)
 
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
 
+                                ((FLAG) == DCMI_FLAG_VSYNC) || \
 
+                                ((FLAG) == DCMI_FLAG_FNE) || \
 
+                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
 
+                                ((FLAG) == DCMI_FLAG_OVFRI) || \
 
+                                ((FLAG) == DCMI_FLAG_ERRRI) || \
 
+                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
 
+                                ((FLAG) == DCMI_FLAG_LINERI) || \
 
+                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
 
+                                ((FLAG) == DCMI_FLAG_OVFMI) || \
 
+                                ((FLAG) == DCMI_FLAG_ERRMI) || \
 
+                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
 
+                                ((FLAG) == DCMI_FLAG_LINEMI))
 
+                                
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the DCMI configuration to the default reset state ****/ 
+void DCMI_DeInit(void);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
 
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
 
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
 
+void DCMI_CROPCmd(FunctionalState NewState);
 
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
 
+void DCMI_JPEGCmd(FunctionalState NewState);
 
+
 
+/* Image capture functions ****************************************************/
 
+void DCMI_Cmd(FunctionalState NewState);
 
+void DCMI_CaptureCmd(FunctionalState NewState);
 
+uint32_t DCMI_ReadData(void);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
 
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
 
+void DCMI_ClearFlag(uint16_t DCMI_FLAG);
 
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
 
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_DCMI_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 609 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_dma.h
Ver arquivo 

@@ -0,0 +1,609 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dma.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_DMA_H
 
+#define __STM32F4xx_DMA_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup DMA
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  DMA Init structure definition
 
+  */
 
+
 
+typedef struct
 
+{
 
+  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
+                                        This parameter can be a value of @ref DMA_channel */
 
+ 
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
 
+
 
+  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
+                                        This memory is the default memory used when double buffer mode is
 
+                                        not enabled. */
 
+
 
+  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                        from memory to memory or from peripheral to memory.
 
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
 
+
 
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
 
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
 
+
 
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
 
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
 
+
 
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
 
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
 
+
 
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
 
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
 
+
 
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
 
+                                        This parameter can be a value of @ref DMA_memory_data_size */
 
+
 
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
 
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
 
+                                        @note The circular buffer mode cannot be used if the memory-to-memory
 
+                                              data transfer is configured on the selected Stream */
 
+
 
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
 
+                                        This parameter can be a value of @ref DMA_priority_level */
 
+
 
+  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
 
+                                        This parameter can be a value of @ref DMA_fifo_direct_mode
 
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                               memory-to-memory data transfer is configured on the selected Stream */
 
+
 
+  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
 
+                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
 
+
 
+  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */
 
+
 
+  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
+}DMA_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup DMA_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
 
+                                   ((PERIPH) == DMA1_Stream1) || \
 
+                                   ((PERIPH) == DMA1_Stream2) || \
 
+                                   ((PERIPH) == DMA1_Stream3) || \
 
+                                   ((PERIPH) == DMA1_Stream4) || \
 
+                                   ((PERIPH) == DMA1_Stream5) || \
 
+                                   ((PERIPH) == DMA1_Stream6) || \
 
+                                   ((PERIPH) == DMA1_Stream7) || \
 
+                                   ((PERIPH) == DMA2_Stream0) || \
 
+                                   ((PERIPH) == DMA2_Stream1) || \
 
+                                   ((PERIPH) == DMA2_Stream2) || \
 
+                                   ((PERIPH) == DMA2_Stream3) || \
 
+                                   ((PERIPH) == DMA2_Stream4) || \
 
+                                   ((PERIPH) == DMA2_Stream5) || \
 
+                                   ((PERIPH) == DMA2_Stream6) || \
 
+                                   ((PERIPH) == DMA2_Stream7))
 
+
 
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
 
+                                           ((CONTROLLER) == DMA2))
 
+
 
+/** @defgroup DMA_channel 
+  * @{
 
+  */ 
+#define DMA_Channel_0                     ((uint32_t)0x00000000)
 
+#define DMA_Channel_1                     ((uint32_t)0x02000000)
 
+#define DMA_Channel_2                     ((uint32_t)0x04000000)
 
+#define DMA_Channel_3                     ((uint32_t)0x06000000)
 
+#define DMA_Channel_4                     ((uint32_t)0x08000000)
 
+#define DMA_Channel_5                     ((uint32_t)0x0A000000)
 
+#define DMA_Channel_6                     ((uint32_t)0x0C000000)
 
+#define DMA_Channel_7                     ((uint32_t)0x0E000000)
 
+
 
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
 
+                                 ((CHANNEL) == DMA_Channel_1) || \
 
+                                 ((CHANNEL) == DMA_Channel_2) || \
 
+                                 ((CHANNEL) == DMA_Channel_3) || \
 
+                                 ((CHANNEL) == DMA_Channel_4) || \
 
+                                 ((CHANNEL) == DMA_Channel_5) || \
 
+                                 ((CHANNEL) == DMA_Channel_6) || \
 
+                                 ((CHANNEL) == DMA_Channel_7))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_data_transfer_direction 
+  * @{
 
+  */ 
+#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
 
+#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
+#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
 
+
 
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
 
+                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
 
+                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_data_buffer_size 
+  * @{
 
+  */ 
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
 
+  */ 
+#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
 
+#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
 
+
 
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
 
+                                            ((STATE) == DMA_PeripheralInc_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
 
+  */ 
+#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
 
+#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
 
+
 
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
 
+                                        ((STATE) == DMA_MemoryInc_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_peripheral_data_size 
+  * @{
 
+  */ 
+#define DMA_PeripheralDataSize_Byte       ((uint32_t)0x00000000) 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
+#define DMA_PeripheralDataSize_Word       ((uint32_t)0x00001000)
 
+
 
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
 
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
 
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_memory_data_size 
+  * @{
 
+  */ 
+#define DMA_MemoryDataSize_Byte           ((uint32_t)0x00000000) 
+#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
+#define DMA_MemoryDataSize_Word           ((uint32_t)0x00004000)
 
+
 
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
 
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
 
+                                       ((SIZE) == DMA_MemoryDataSize_Word ))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_circular_normal_mode 
+  * @{
 
+  */ 
+#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
+#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
 
+
 
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
 
+                           ((MODE) == DMA_Mode_Circular)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_priority_level 
+  * @{
 
+  */ 
+#define DMA_Priority_Low                  ((uint32_t)0x00000000)
 
+#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
+#define DMA_Priority_High                 ((uint32_t)0x00020000)
 
+#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
 
+
 
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
 
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
 
+                                   ((PRIORITY) == DMA_Priority_High)   || \
 
+                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_fifo_direct_mode 
+  * @{
 
+  */ 
+#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
+#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
 
+
 
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
 
+                                       ((STATE) == DMA_FIFOMode_Enable)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_fifo_threshold_level 
+  * @{
 
+  */ 
+#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
 
+#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
 
+#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
 
+
 
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
 
+                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
 
+                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
 
+                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_memory_burst 
+  * @{
 
+  */ 
+#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
 
+#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
+#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
 
+#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
 
+
 
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
 
+                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
 
+                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
 
+                                    ((BURST) == DMA_MemoryBurst_INC16))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_peripheral_burst 
+  * @{
 
+  */ 
+#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
 
+#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
+#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
 
+#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
 
+
 
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
 
+                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
 
+                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
 
+                                        ((BURST) == DMA_PeripheralBurst_INC16))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_fifo_status_level 
+  * @{
 
+  */
 
+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
 
+#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
 
+#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
+#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
 
+#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
 
+#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
 
+
 
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
 
+                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
 
+                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
 
+                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
 
+                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
 
+                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup DMA_flags_definition 
+  * @{
 
+  */
 
+#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
 
+#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
 
+#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
 
+#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
 
+#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
 
+#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
 
+#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
 
+#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
 
+#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
 
+#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
 
+#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
 
+#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
 
+#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
 
+#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
 
+#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
 
+#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
 
+#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
 
+#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
 
+#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
 
+#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
 
+#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
 
+#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
 
+#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
 
+#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
 
+#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
 
+#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
 
+#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
 
+#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
 
+#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
 
+#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
 
+#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
 
+#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
 
+#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
 
+#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
 
+#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
 
+#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
 
+#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
 
+#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
 
+#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
 
+#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
 
+
 
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
 
+                                 (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
 
+
 
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
 
+                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
 
+                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
 
+                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
 
+                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
 
+                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
 
+                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
 
+                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
 
+                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
 
+                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
 
+                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
 
+                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
 
+                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
 
+                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
 
+                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
 
+                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
 
+                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
 
+                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
 
+                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
 
+                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_interrupt_enable_definitions 
+  * @{
 
+  */ 
+#define DMA_IT_TC                         ((uint32_t)0x00000010)
 
+#define DMA_IT_HT                         ((uint32_t)0x00000008)
 
+#define DMA_IT_TE                         ((uint32_t)0x00000004)
 
+#define DMA_IT_DME                        ((uint32_t)0x00000002)
 
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
 
+
 
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_interrupts_definitions 
+  * @{
 
+  */ 
+#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
 
+#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
 
+#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
 
+#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
 
+#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
 
+#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
 
+#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
 
+#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
 
+#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
 
+#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
 
+#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
 
+#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
 
+#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
 
+#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
 
+#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
 
+#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
 
+#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
 
+#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
 
+#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
 
+#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
 
+#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
 
+#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
 
+#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
 
+#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
 
+#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
 
+#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
 
+#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
 
+#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
 
+#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
 
+#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
 
+#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
 
+#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
 
+#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
 
+#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
 
+#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
 
+#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
 
+#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
 
+#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
 
+#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
 
+#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
 
+
 
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
 
+                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
 
+                             (((IT) & 0x40820082) == 0x00))
 
+
 
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
 
+                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
 
+                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
 
+                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
 
+                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
 
+                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
 
+                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
 
+                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
 
+                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
 
+                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
 
+                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
 
+                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
 
+                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
 
+                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
 
+                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
 
+                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
 
+                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
 
+                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
 
+                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
 
+                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_peripheral_increment_offset 
+  * @{
 
+  */ 
+#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
 
+#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
 
+
 
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
 
+                                  ((SIZE) == DMA_PINCOS_WordAligned))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_flow_controller_definitions 
+  * @{
 
+  */ 
+#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
 
+#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
 
+
 
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
 
+                                ((CTRL) == DMA_FlowCtrl_Peripheral))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup DMA_memory_targets_definitions 
+  * @{
 
+  */ 
+#define DMA_Memory_0                      ((uint32_t)0x00000000)
 
+#define DMA_Memory_1                      ((uint32_t)0x00080000)
 
+
 
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the DMA configuration to the default reset state *****/ 
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
 
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
 
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
 
+
 
+/* Optional Configuration functions *******************************************/
 
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
 
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
 
+
 
+/* Data Counter functions *****************************************************/
 
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
 
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
 
+
 
+/* Double Buffer mode functions ***********************************************/
 
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
 
+                                uint32_t DMA_CurrentMemory);
 
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
 
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
 
+                            uint32_t DMA_MemoryTarget);
 
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
 
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
 
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
 
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
 
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
 
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
 
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_DMA_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 183 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_exti.h
Ver arquivo 

@@ -0,0 +1,183 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_exti.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_EXTI_H
 
+#define __STM32F4xx_EXTI_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup EXTI
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  EXTI mode enumeration  
+  */
 
+
 
+typedef enum
 
+{
 
+  EXTI_Mode_Interrupt = 0x00,
 
+  EXTI_Mode_Event = 0x04
 
+}EXTIMode_TypeDef;
 
+
 
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
 
+
 
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
 
+
 
+typedef enum
 
+{
 
+  EXTI_Trigger_Rising = 0x08,
 
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
 
+}EXTITrigger_TypeDef;
 
+
 
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
 
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
 
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
 
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
 
+                                         This parameter can be any combination value of @ref EXTI_Lines */
 
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
 
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
 
+
 
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
 
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
 
+
 
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
 
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup EXTI_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup EXTI_Lines 
+  * @{
 
+  */
 
+
 
+#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
 
+#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
 
+#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
 
+#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
 
+#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
 
+#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
 
+#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
 
+#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
 
+#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
 
+#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
 
+#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
 
+#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
 
+#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
 
+#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
 
+#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
 
+#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
 
+#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
 
+#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
 
+#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
 
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
 
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */                                               
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
 
+
 
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
 
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
 
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
 
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
 
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
 
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
 
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
 
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
 
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
 
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
 
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
 
+                                ((LINE) == EXTI_Line22))
 
+                    
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+
 
+/*  Function used to set the EXTI configuration to the default reset state *****/
 
+void EXTI_DeInit(void);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
 
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
 
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
 
+void EXTI_ClearFlag(uint32_t EXTI_Line);
 
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
 
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_EXTI_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 340 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_flash.h
Ver arquivo 

@@ -0,0 +1,340 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_flash.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_FLASH_H
 
+#define __STM32F4xx_FLASH_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup FLASH
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/** 
+  * @brief FLASH Status  
+  */ 
+typedef enum
 
+{ 
+  FLASH_BUSY = 1,
 
+  FLASH_ERROR_PGS,
 
+  FLASH_ERROR_PGP,
 
+  FLASH_ERROR_PGA,
 
+  FLASH_ERROR_WRP,
 
+  FLASH_ERROR_PROGRAM,
 
+  FLASH_ERROR_OPERATION,
 
+  FLASH_COMPLETE
 
+}FLASH_Status;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup FLASH_Exported_Constants
 
+  * @{
 
+  */  
+
 
+/** @defgroup Flash_Latency 
+  * @{
 
+  */ 
+#define FLASH_Latency_0                ((uint8_t)0x0000)  /*!< FLASH Zero Latency cycle */
 
+#define FLASH_Latency_1                ((uint8_t)0x0001)  /*!< FLASH One Latency cycle */
 
+#define FLASH_Latency_2                ((uint8_t)0x0002)  /*!< FLASH Two Latency cycles */
 
+#define FLASH_Latency_3                ((uint8_t)0x0003)  /*!< FLASH Three Latency cycles */
 
+#define FLASH_Latency_4                ((uint8_t)0x0004)  /*!< FLASH Four Latency cycles */
 
+#define FLASH_Latency_5                ((uint8_t)0x0005)  /*!< FLASH Five Latency cycles */
 
+#define FLASH_Latency_6                ((uint8_t)0x0006)  /*!< FLASH Six Latency cycles */
 
+#define FLASH_Latency_7                ((uint8_t)0x0007)  /*!< FLASH Seven Latency cycles */
 
+
 
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
 
+                                   ((LATENCY) == FLASH_Latency_1) || \
 
+                                   ((LATENCY) == FLASH_Latency_2) || \
 
+                                   ((LATENCY) == FLASH_Latency_3) || \
 
+                                   ((LATENCY) == FLASH_Latency_4) || \
 
+                                   ((LATENCY) == FLASH_Latency_5) || \
 
+                                   ((LATENCY) == FLASH_Latency_6) || \
 
+                                   ((LATENCY) == FLASH_Latency_7))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Voltage_Range 
+  * @{
 
+  */ 
+#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
 
+#define VoltageRange_2        ((uint8_t)0x01)  /*!<Device operating range: 2.1V to 2.7V */
 
+#define VoltageRange_3        ((uint8_t)0x02)  /*!<Device operating range: 2.7V to 3.6V */
 
+#define VoltageRange_4        ((uint8_t)0x03)  /*!<Device operating range: 2.7V to 3.6V + External Vpp */
 
+
 
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
 
+                               ((RANGE) == VoltageRange_2) || \
 
+                               ((RANGE) == VoltageRange_3) || \
 
+                               ((RANGE) == VoltageRange_4))                                                                                                               
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Sectors
 
+  * @{
 
+  */ 
+#define FLASH_Sector_0     ((uint16_t)0x0000) /*!< Sector Number 0 */
 
+#define FLASH_Sector_1     ((uint16_t)0x0008) /*!< Sector Number 1 */
 
+#define FLASH_Sector_2     ((uint16_t)0x0010) /*!< Sector Number 2 */
 
+#define FLASH_Sector_3     ((uint16_t)0x0018) /*!< Sector Number 3 */
 
+#define FLASH_Sector_4     ((uint16_t)0x0020) /*!< Sector Number 4 */
 
+#define FLASH_Sector_5     ((uint16_t)0x0028) /*!< Sector Number 5 */
 
+#define FLASH_Sector_6     ((uint16_t)0x0030) /*!< Sector Number 6 */
 
+#define FLASH_Sector_7     ((uint16_t)0x0038) /*!< Sector Number 7 */
 
+#define FLASH_Sector_8     ((uint16_t)0x0040) /*!< Sector Number 8 */
 
+#define FLASH_Sector_9     ((uint16_t)0x0048) /*!< Sector Number 9 */
 
+#define FLASH_Sector_10    ((uint16_t)0x0050) /*!< Sector Number 10 */
 
+#define FLASH_Sector_11    ((uint16_t)0x0058) /*!< Sector Number 11 */
 
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
 
+                                 ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
 
+                                 ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
 
+                                 ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
 
+                                 ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
 
+                                 ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
 
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
 
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))  
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
 
+  */ 
+#define OB_WRP_Sector_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
 
+#define OB_WRP_Sector_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
 
+#define OB_WRP_Sector_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
 
+#define OB_WRP_Sector_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
 
+#define OB_WRP_Sector_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
 
+#define OB_WRP_Sector_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
 
+#define OB_WRP_Sector_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
 
+#define OB_WRP_Sector_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
 
+#define OB_WRP_Sector_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
 
+#define OB_WRP_Sector_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
 
+#define OB_WRP_Sector_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
 
+#define OB_WRP_Sector_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
 
+#define OB_WRP_Sector_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
 
+
 
+#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Option_Bytes_Read_Protection 
+  * @{
 
+  */
 
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
 
+#define OB_RDP_Level_1   ((uint8_t)0x55)
 
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
+                                                  it's no more possible to go back to level 1 or 0 */
 
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
 
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
 
+                          ((LEVEL) == OB_RDP_Level_2))*/
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Option_Bytes_IWatchdog 
+  * @{
 
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
 
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
 
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Option_Bytes_nRST_STOP 
+  * @{
 
+  */ 
+#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
 
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
 
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
+  * @{
 
+  */ 
+#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
 
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
 
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup FLASH_BOR_Reset_Level 
+  * @{
 
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
 
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
 
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
 
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
 
+#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
 
+                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Interrupts 
+  * @{
 
+  */ 
+#define FLASH_IT_EOP                   ((uint32_t)0x01000000)  /*!< End of FLASH Operation Interrupt source */
 
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source */
 
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Flags 
+  * @{
 
+  */ 
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000001)  /*!< FLASH End of Operation flag */
 
+#define FLASH_FLAG_OPERR               ((uint32_t)0x00000002)  /*!< FLASH operation Error flag */
 
+#define FLASH_FLAG_WRPERR              ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
 
+#define FLASH_FLAG_PGAERR              ((uint32_t)0x00000020)  /*!< FLASH Programming Alignment error flag */
 
+#define FLASH_FLAG_PGPERR              ((uint32_t)0x00000040)  /*!< FLASH Programming Parallelism error flag  */
 
+#define FLASH_FLAG_PGSERR              ((uint32_t)0x00000080)  /*!< FLASH Programming Sequence error flag  */
 
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00010000)  /*!< FLASH Busy flag */ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
 
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
 
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
 
+                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
 
+                                  ((FLAG) == FLASH_FLAG_BSY))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Program_Parallelism   
+  * @{
 
+  */
 
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
 
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
 
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
 
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
 
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup FLASH_Keys 
+  * @{
 
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
 
+#define FLASH_KEY1               ((uint32_t)0x45670123)
 
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
 
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
 
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** 
+  * @brief   ACR register byte 0 (Bits[8:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
+/** 
+  * @brief   OPTCR register byte 3 (Bits[24:16]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
 
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
 
+#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+ 
+/* FLASH Interface configuration functions ************************************/
 
+void FLASH_SetLatency(uint32_t FLASH_Latency);
 
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
 
+void FLASH_InstructionCacheCmd(FunctionalState NewState);
 
+void FLASH_DataCacheCmd(FunctionalState NewState);
 
+void FLASH_InstructionCacheReset(void);
 
+void FLASH_DataCacheReset(void);
 
+
 
+/* FLASH Memory Programming functions *****************************************/   
+void FLASH_Unlock(void);
 
+void FLASH_Lock(void);
 
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
 
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
 
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
 
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
 
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
 
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
 
+
 
+/* Option Bytes Programming functions *****************************************/ 
+void FLASH_OB_Unlock(void);
 
+void FLASH_OB_Lock(void);
 
+void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
 
+void FLASH_OB_RDPConfig(uint8_t OB_RDP);
 
+void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
 
+void FLASH_OB_BORConfig(uint8_t OB_BOR);
 
+FLASH_Status FLASH_OB_Launch(void);
 
+uint8_t FLASH_OB_GetUser(void);
 
+uint16_t FLASH_OB_GetWRP(void);
 
+FlagStatus FLASH_OB_GetRDP(void);
 
+uint8_t FLASH_OB_GetBOR(void);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
 
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
 
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
 
+FLASH_Status FLASH_GetStatus(void);
 
+FLASH_Status FLASH_WaitForLastOperation(void);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_FLASH_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 675 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_fsmc.h
Ver arquivo 

@@ -0,0 +1,675 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_fsmc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_FSMC_H
 
+#define __STM32F4xx_FSMC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup FSMC
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
 
+typedef struct
 
+{
 
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
 
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
 
+                                             @note This parameter is not used with synchronous NOR Flash memories. */
 
+
 
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
 
+                                             the duration of the address hold time.
 
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note This parameter is not used with synchronous NOR Flash memories.*/
 
+
 
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
 
+                                             the duration of the data setup time.
 
+                                             This parameter can be a value between 0 and 0xFF.
 
+                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
 
+
 
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
 
+                                             the duration of the bus turnaround.
 
+                                             This parameter can be a value between 0 and 0xF.
 
+                                             @note This parameter is only used for multiplexed NOR Flash memories. */
 
+
 
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
 
+                                             This parameter can be a value between 1 and 0xF.
 
+                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
 
+
 
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
 
+                                             to the memory before getting the first data.
 
+                                             The parameter value depends on the memory type as shown below:
 
+                                              - It must be set to 0 in case of a CRAM
 
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
 
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
 
+                                                with synchronous burst mode enable */
 
+
 
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
 
+}FSMC_NORSRAMTimingInitTypeDef;
 
+
 
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
 
+  */
 
+typedef struct
 
+{
 
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
 
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
 
+
 
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
 
+                                          multiplexed on the databus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
 
+
 
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
 
+                                          the corresponding memory bank.
 
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
 
+
 
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
 
+                                          This parameter can be a value of @ref FSMC_Data_Width */
 
+
 
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
 
+                                          valid only with synchronous burst Flash memories.
 
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
 
+
 
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
 
+                                          valid only with asynchronous Flash memories.
 
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
+
 
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
 
+                                          the Flash memory in burst mode.
 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
 
+
 
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
 
+                                          memory, valid only when accessing Flash memories in burst mode.
 
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
 
+
 
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
 
+                                          clock cycle before the wait state or during the wait state,
 
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
 
+
 
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
 
+
 
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
 
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
 
+
 
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
 
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
 
+
 
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
 
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
 
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
+
 
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
+}FSMC_NORSRAMInitTypeDef;
 
+
 
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
 
+  */
 
+typedef struct
 
+{
 
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
 
+                                     the command assertion for NAND-Flash read or write access
 
+                                     to common/Attribute or I/O memory space (depending on
 
+                                     the memory space timing to be configured).
 
+                                     This parameter can be a value between 0 and 0xFF.*/
 
+
 
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
 
+                                     command for NAND-Flash read or write access to
 
+                                     common/Attribute or I/O memory space (depending on the
 
+                                     memory space timing to be configured). 
+                                     This parameter can be a number between 0x00 and 0xFF */
 
+
 
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
 
+                                     (and data for write access) after the command deassertion
 
+                                     for NAND-Flash read or write access to common/Attribute
 
+                                     or I/O memory space (depending on the memory space timing
 
+                                     to be configured).
 
+                                     This parameter can be a number between 0x00 and 0xFF */
 
+
 
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
 
+                                     databus is kept in HiZ after the start of a NAND-Flash
 
+                                     write access to common/Attribute or I/O memory space (depending
 
+                                     on the memory space timing to be configured).
 
+                                     This parameter can be a number between 0x00 and 0xFF */
 
+}FSMC_NAND_PCCARDTimingInitTypeDef;
 
+
 
+/** 
+  * @brief  FSMC NAND Init structure definition
 
+  */
 
+typedef struct
 
+{
 
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
 
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
 
+
 
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
 
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
 
+
 
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
 
+                                       This parameter can be any value of @ref FSMC_Data_Width */
 
+
 
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
 
+                                       This parameter can be any value of @ref FSMC_ECC */
 
+
 
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
 
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
 
+
 
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
 
+                                       delay between CLE low and RE low.
 
+                                       This parameter can be a value between 0 and 0xFF. */
 
+
 
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
 
+                                       delay between ALE low and RE low.
 
+                                       This parameter can be a number between 0x0 and 0xFF */ 
+
 
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
+
 
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
 
+}FSMC_NANDInitTypeDef;
 
+
 
+/** 
+  * @brief  FSMC PCCARD Init structure definition
 
+  */
 
+
 
+typedef struct
 
+{
 
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
 
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
 
+
 
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
 
+                                     delay between CLE low and RE low.
 
+                                     This parameter can be a value between 0 and 0xFF. */
 
+
 
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
 
+                                     delay between ALE low and RE low.
 
+                                     This parameter can be a number between 0x0 and 0xFF */ 
+
 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
 
+
 
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
+}FSMC_PCCARDInitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup FSMC_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
 
+  */
 
+#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
 
+#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
 
+#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
 
+#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_NAND_Bank 
+  * @{
 
+  */  
+#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
 
+#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_PCCARD_Bank 
+  * @{
 
+  */    
+#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
 
+/**
 
+  * @}
 
+  */
 
+
 
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
 
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
 
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
 
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
 
+
 
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 
+                                 ((BANK) == FSMC_Bank3_NAND))
 
+
 
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 
+                                    ((BANK) == FSMC_Bank3_NAND) || \
 
+                                    ((BANK) == FSMC_Bank4_PCCARD))
 
+
 
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 
+                               ((BANK) == FSMC_Bank3_NAND) || \
 
+                               ((BANK) == FSMC_Bank4_PCCARD))
 
+
 
+/** @defgroup FSMC_NOR_SRAM_Controller 
+  * @{
 
+  */
 
+
 
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
 
+  */
 
+
 
+#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
 
+#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
 
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
 
+                          ((MUX) == FSMC_DataAddressMux_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Memory_Type 
+  * @{
 
+  */
 
+
 
+#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
 
+#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
 
+#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
 
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
 
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
 
+                                ((MEMORY) == FSMC_MemoryType_NOR))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Data_Width 
+  * @{
 
+  */
 
+
 
+#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
 
+#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
 
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
 
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
 
+  */
 
+
 
+#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
 
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
 
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
 
+/**
 
+  * @}
 
+  */
 
+    
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
 
+  */
 
+#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
 
+#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
 
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
 
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
 
+  */
 
+#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
 
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
 
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
 
+  */
 
+#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
 
+#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
 
+                                 ((MODE) == FSMC_WrapMode_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Wait_Timing 
+  * @{
 
+  */
 
+#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
 
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Write_Operation 
+  * @{
 
+  */
 
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
 
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
 
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
 
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Wait_Signal 
+  * @{
 
+  */
 
+#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
 
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Extended_Mode 
+  * @{
 
+  */
 
+#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
 
+#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
 
+
 
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
 
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Write_Burst 
+  * @{
 
+  */
 
+
 
+#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
 
+#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
 
+                                    ((BURST) == FSMC_WriteBurst_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
 
+  */
 
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_CLK_Division 
+  * @{
 
+  */
 
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Data_Latency 
+  * @{
 
+  */
 
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Access_Mode 
+  * @{
 
+  */
 
+#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
 
+#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
 
+#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
 
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
 
+                                   ((MODE) == FSMC_AccessMode_B) || \
 
+                                   ((MODE) == FSMC_AccessMode_C) || \
 
+                                   ((MODE) == FSMC_AccessMode_D))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup FSMC_NAND_PCCARD_Controller 
+  * @{
 
+  */
 
+
 
+/** @defgroup FSMC_Wait_feature 
+  * @{
 
+  */
 
+#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
 
+#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
 
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
 
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup FSMC_ECC 
+  * @{
 
+  */
 
+#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
 
+#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
 
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
 
+                                  ((STATE) == FSMC_ECC_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
 
+  */
 
+#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
 
+#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
 
+#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
 
+#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
 
+#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
 
+#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
 
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
 
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
 
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
 
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
 
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
 
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
 
+  */
 
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
 
+  */
 
+#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
 
+#define FSMC_IT_Level                            ((uint32_t)0x00000010)
 
+#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
 
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
 
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
 
+                            ((IT) == FSMC_IT_Level) || \
 
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Flags 
+  * @{
 
+  */
 
+#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
 
+#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
 
+#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
 
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
 
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
 
+                                ((FLAG) == FSMC_FLAG_Level) || \
 
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
 
+                                ((FLAG) == FSMC_FLAG_FEMPT))
 
+
 
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/* NOR/SRAM Controller functions **********************************************/
 
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
 
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
 
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
 
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 
+
 
+/* NAND Controller functions **************************************************/
 
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
 
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
 
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
 
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
 
+
 
+/* PCCARD Controller functions ************************************************/
 
+void FSMC_PCCARDDeInit(void);
 
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
 
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
 
+void FSMC_PCCARDCmd(FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
 
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
 
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
 
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
 
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_FSMC_H */
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 412 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_gpio.h
Ver arquivo 

@@ -0,0 +1,412 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_gpio.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the GPIO firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_GPIO_H
 
+#define __STM32F4xx_GPIO_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup GPIO
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
 
+                                    ((PERIPH) == GPIOB) || \
 
+                                    ((PERIPH) == GPIOC) || \
 
+                                    ((PERIPH) == GPIOD) || \
 
+                                    ((PERIPH) == GPIOE) || \
 
+                                    ((PERIPH) == GPIOF) || \
 
+                                    ((PERIPH) == GPIOG) || \
 
+                                    ((PERIPH) == GPIOH) || \
 
+                                    ((PERIPH) == GPIOI))
 
+                                                                
+/** 
+  * @brief  GPIO Configuration Mode enumeration 
+  */   
+typedef enum
 
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
 
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
 
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
 
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
 
+}GPIOMode_TypeDef;
 
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
 
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
 
+
 
+/** 
+  * @brief  GPIO Output type enumeration 
+  */  
+typedef enum
 
+{ 
+  GPIO_OType_PP = 0x00,
 
+  GPIO_OType_OD = 0x01
 
+}GPIOOType_TypeDef;
 
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
 
+
 
+
 
+/** 
+  * @brief  GPIO Output Maximum frequency enumeration 
+  */  
+typedef enum
 
+{ 
+  GPIO_Speed_2MHz   = 0x00, /*!< Low speed */
 
+  GPIO_Speed_25MHz  = 0x01, /*!< Medium speed */
 
+  GPIO_Speed_50MHz  = 0x02, /*!< Fast speed */
 
+  GPIO_Speed_100MHz = 0x03  /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
 
+}GPIOSpeed_TypeDef;
 
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
 
+                              ((SPEED) == GPIO_Speed_50MHz)||  ((SPEED) == GPIO_Speed_100MHz)) 
+
 
+/** 
+  * @brief  GPIO Configuration PullUp PullDown enumeration 
+  */ 
+typedef enum
 
+{ 
+  GPIO_PuPd_NOPULL = 0x00,
 
+  GPIO_PuPd_UP     = 0x01,
 
+  GPIO_PuPd_DOWN   = 0x02
 
+}GPIOPuPd_TypeDef;
 
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
 
+                            ((PUPD) == GPIO_PuPd_DOWN))
 
+
 
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */ 
+typedef enum
 
+{ 
+  Bit_RESET = 0,
 
+  Bit_SET
 
+}BitAction;
 
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
 
+
 
+
 
+/** 
+  * @brief   GPIO Init structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
 
+                                       This parameter can be any value of @ref GPIO_pins_define */
 
+
 
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
 
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */
 
+
 
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
 
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
 
+
 
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
 
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */
 
+
 
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
 
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
 
+}GPIO_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup GPIO_Exported_Constants
 
+  * @{
 
+  */ 
+
 
+/** @defgroup GPIO_pins_define 
+  * @{
 
+  */ 
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
 
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
 
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
 
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
 
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
 
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
 
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
 
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
 
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
 
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
 
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
 
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
 
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
 
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
 
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
 
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
 
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
 
+
 
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
 
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
 
+                              ((PIN) == GPIO_Pin_1) || \
 
+                              ((PIN) == GPIO_Pin_2) || \
 
+                              ((PIN) == GPIO_Pin_3) || \
 
+                              ((PIN) == GPIO_Pin_4) || \
 
+                              ((PIN) == GPIO_Pin_5) || \
 
+                              ((PIN) == GPIO_Pin_6) || \
 
+                              ((PIN) == GPIO_Pin_7) || \
 
+                              ((PIN) == GPIO_Pin_8) || \
 
+                              ((PIN) == GPIO_Pin_9) || \
 
+                              ((PIN) == GPIO_Pin_10) || \
 
+                              ((PIN) == GPIO_Pin_11) || \
 
+                              ((PIN) == GPIO_Pin_12) || \
 
+                              ((PIN) == GPIO_Pin_13) || \
 
+                              ((PIN) == GPIO_Pin_14) || \
 
+                              ((PIN) == GPIO_Pin_15))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup GPIO_Pin_sources 
+  * @{
 
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
 
+#define GPIO_PinSource1            ((uint8_t)0x01)
 
+#define GPIO_PinSource2            ((uint8_t)0x02)
 
+#define GPIO_PinSource3            ((uint8_t)0x03)
 
+#define GPIO_PinSource4            ((uint8_t)0x04)
 
+#define GPIO_PinSource5            ((uint8_t)0x05)
 
+#define GPIO_PinSource6            ((uint8_t)0x06)
 
+#define GPIO_PinSource7            ((uint8_t)0x07)
 
+#define GPIO_PinSource8            ((uint8_t)0x08)
 
+#define GPIO_PinSource9            ((uint8_t)0x09)
 
+#define GPIO_PinSource10           ((uint8_t)0x0A)
 
+#define GPIO_PinSource11           ((uint8_t)0x0B)
 
+#define GPIO_PinSource12           ((uint8_t)0x0C)
 
+#define GPIO_PinSource13           ((uint8_t)0x0D)
 
+#define GPIO_PinSource14           ((uint8_t)0x0E)
 
+#define GPIO_PinSource15           ((uint8_t)0x0F)
 
+
 
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
 
+                                       ((PINSOURCE) == GPIO_PinSource15))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup GPIO_Alternat_function_selection_define 
+  * @{
 
+  */ 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
 
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
 
+#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
 
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
 
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
 
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
 
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
 
+#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
 
+#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
 
+#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
 
+#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
 
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
 
+#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping */
 
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
 
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
 
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
 
+#define GPIO_AF_I2S3ext       ((uint8_t)0x07)  /* I2S3ext Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping */
 
+#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping */
 
+#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping */
 
+#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping */
 
+#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
 
+#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
 
+#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
 
+#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF_FSMC            ((uint8_t)0xC)  /* FSMC Alternate Function mapping */
 
+#define GPIO_AF_OTG_HS_FS       ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
 
+#define GPIO_AF_SDIO            ((uint8_t)0xC)  /* SDIO Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
 
+
 
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
 
+
 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)  || \
 
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER) || \
 
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)  || \
 
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)   || \
 
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)   || \
 
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)   || \
 
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)   || \
 
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)   || \
 
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)  || \
 
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)  || \
 
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2) || \
 
+                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)  || \
 
+                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6) || \
 
+                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)   || \
 
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS) || \
 
+                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_FSMC)   || \
 
+                          ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO)   || \
 
+                          ((AF) == GPIO_AF_DCMI)      || ((AF) == GPIO_AF_EVENTOUT))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup GPIO_Legacy 
+  * @{
 
+  */
 
+    
+#define GPIO_Mode_AIN           GPIO_Mode_AN
 
+
 
+#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
 
+#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
 
+#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the GPIO configuration to the default reset state ****/
 
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
 
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
 
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+
 
+/* GPIO Read and Write functions **********************************************/
 
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
 
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
 
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
 
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
 
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 
+
 
+/* GPIO Alternate functions configuration function ****************************/
 
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_GPIO_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 250 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_hash.h
Ver arquivo 

@@ -0,0 +1,250 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_hash.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the HASH 
+  *          firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_HASH_H
 
+#define __STM32F4xx_HASH_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup HASH
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief   HASH Init structure definition
 
+  */ 
+typedef struct
 
+{
 
+  uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value 
+                                    of @ref HASH_Algo_Selection */
 
+  uint32_t HASH_AlgoMode;      /*!< HASH or HMAC. This parameter can be a value 
+                                    of @ref HASH_processor_Algorithm_Mode */
 
+  uint32_t HASH_DataType;      /*!< 32-bit data, 16-bit data, 8-bit data or 
+                                    bit-string. This parameter can be a value of
 
+                                    @ref HASH_Data_Type */
 
+  uint32_t HASH_HMACKeyType;   /*!< HMAC Short key or HMAC Long Key. This parameter
 
+                                    can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
 
+}HASH_InitTypeDef;
 
+
 
+/** 
+  * @brief  HASH message digest result structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t Data[5];      /*!< Message digest result : 5x 32bit words for SHA1 or 
+                                                      4x 32bit words for MD5  */
 
+} HASH_MsgDigest; 
+
 
+/** 
+  * @brief  HASH context swapping structure definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t HASH_IMR; 
+  uint32_t HASH_STR;      
+  uint32_t HASH_CR;     
+  uint32_t HASH_CSR[51];       
+}HASH_Context;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup HASH_Exported_Constants
 
+  * @{
 
+  */ 
+
 
+/** @defgroup HASH_Algo_Selection 
+  * @{
 
+  */ 
+#define HASH_AlgoSelection_SHA1    ((uint16_t)0x0000) /*!< HASH function is SHA1 */
 
+#define HASH_AlgoSelection_MD5     ((uint16_t)0x0080) /*!< HASH function is MD5 */
 
+
 
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
 
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_processor_Algorithm_Mode 
+  * @{
 
+  */ 
+#define HASH_AlgoMode_HASH         ((uint16_t)0x0000) /*!< Algorithm is HASH */ 
+#define HASH_AlgoMode_HMAC         ((uint16_t)0x0040) /*!< Algorithm is HMAC */
 
+
 
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
 
+                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_Data_Type  
+  * @{
 
+  */  
+#define HASH_DataType_32b          ((uint16_t)0x0000)
 
+#define HASH_DataType_16b          ((uint16_t)0x0010)
 
+#define HASH_DataType_8b           ((uint16_t)0x0020)
 
+#define HASH_DataType_1b           ((uint16_t)0x0030)
 
+
 
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
 
+                                    ((DATATYPE) == HASH_DataType_16b)|| \
 
+                                    ((DATATYPE) == HASH_DataType_8b)|| \
 
+                                    ((DATATYPE) == HASH_DataType_1b))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode  
+  * @{
 
+  */ 
+#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
 
+#define HASH_HMACKeyType_LongKey       ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */
 
+
 
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
 
+                                  ((KEYTYPE) == HASH_HMACKeyType_LongKey))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup Number_of_valid_bits_in_last_word_of_the_message   
+  * @{
 
+  */  
+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_interrupts_definition   
+  * @{
 
+  */  
+#define HASH_IT_DINI               ((uint8_t)0x01)  /*!< A new block can be entered into the input buffer (DIN)*/
 
+#define HASH_IT_DCI                ((uint8_t)0x02)  /*!< Digest calculation complete */
 
+
 
+#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
 
+#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
 
+				   
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_flags_definition   
+  * @{
 
+  */  
+#define HASH_FLAG_DINIS            ((uint16_t)0x0001)  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/
 
+#define HASH_FLAG_DCIS             ((uint16_t)0x0002)  /*!< Digest calculation complete */
 
+#define HASH_FLAG_DMAS             ((uint16_t)0x0004)  /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
 
+#define HASH_FLAG_BUSY             ((uint16_t)0x0008)  /*!< The hash core is Busy : processing a block of data */
 
+#define HASH_FLAG_DINNE            ((uint16_t)0x1000)  /*!< DIN not empty : The input buffer contains at least one word of data */
 
+
 
+#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
 
+                                ((FLAG) == HASH_FLAG_DCIS)  || \
 
+                                ((FLAG) == HASH_FLAG_DMAS)  || \
 
+                                ((FLAG) == HASH_FLAG_BUSY)  || \
 
+                                ((FLAG) == HASH_FLAG_DINNE)) 
+
 
+#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
 
+                                 ((FLAG) == HASH_FLAG_DCIS))                                 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+  
+/*  Function used to set the HASH configuration to the default reset state ****/
 
+void HASH_DeInit(void);
 
+
 
+/* HASH Configuration function ************************************************/
 
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
 
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
 
+void HASH_Reset(void);
 
+
 
+/* HASH Message Digest generation functions ***********************************/
 
+void HASH_DataIn(uint32_t Data);
 
+uint8_t HASH_GetInFIFOWordsNbr(void);
 
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
 
+void HASH_StartDigest(void);
 
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
 
+
 
+/* HASH Context swapping functions ********************************************/
 
+void HASH_SaveContext(HASH_Context* HASH_ContextSave);
 
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
 
+
 
+/* HASH's DMA interface function **********************************************/
 
+void HASH_DMACmd(FunctionalState NewState);
 
+
 
+/* HASH Interrupts and flags management functions *****************************/
 
+void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);
 
+FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);
 
+void HASH_ClearFlag(uint16_t HASH_FLAG);
 
+ITStatus HASH_GetITStatus(uint8_t HASH_IT);
 
+void HASH_ClearITPendingBit(uint8_t HASH_IT);
 
+
 
+/* High Level SHA1 functions **************************************************/
 
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
 
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
 
+                      uint8_t *Input, uint32_t Ilen,
 
+                      uint8_t Output[20]);
 
+
 
+/* High Level MD5 functions ***************************************************/
 
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
 
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
 
+                     uint8_t *Input, uint32_t Ilen,
 
+                     uint8_t Output[16]);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_HASH_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 698 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_i2c.h
Ver arquivo 

@@ -0,0 +1,698 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_i2c.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_I2C_H
 
+#define __STM32F4xx_I2C_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup I2C
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  I2C Init structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
 
+                                         This parameter must be set to a value lower than 400kHz */
 
+
 
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
 
+                                         This parameter can be a value of @ref I2C_mode */
 
+
 
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
 
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
 
+
 
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
 
+                                         This parameter can be a 7-bit or 10-bit address. */
 
+
 
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
 
+                                         This parameter can be a value of @ref I2C_acknowledgement */
 
+
 
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
 
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
 
+}I2C_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+
 
+/** @defgroup I2C_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
 
+                                   ((PERIPH) == I2C2) || \
 
+                                   ((PERIPH) == I2C3))
 
+/** @defgroup I2C_mode 
+  * @{
 
+  */
 
+
 
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
 
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
 
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
 
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
 
+                           ((MODE) == I2C_Mode_SMBusHost))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
 
+  */
 
+
 
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
 
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
 
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
 
+                                  ((CYCLE) == I2C_DutyCycle_2))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup I2C_acknowledgement
 
+  * @{
 
+  */
 
+
 
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
 
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
 
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
 
+                                 ((STATE) == I2C_Ack_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_transfer_direction 
+  * @{
 
+  */
 
+
 
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
 
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
 
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
 
+                                     ((DIRECTION) == I2C_Direction_Receiver))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_acknowledged_address 
+  * @{
 
+  */
 
+
 
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
 
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
 
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
 
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup I2C_registers 
+  * @{
 
+  */
 
+
 
+#define I2C_Register_CR1                ((uint8_t)0x00)
 
+#define I2C_Register_CR2                ((uint8_t)0x04)
 
+#define I2C_Register_OAR1               ((uint8_t)0x08)
 
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
 
+#define I2C_Register_DR                 ((uint8_t)0x10)
 
+#define I2C_Register_SR1                ((uint8_t)0x14)
 
+#define I2C_Register_SR2                ((uint8_t)0x18)
 
+#define I2C_Register_CCR                ((uint8_t)0x1C)
 
+#define I2C_Register_TRISE              ((uint8_t)0x20)
 
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
 
+                                   ((REGISTER) == I2C_Register_CR2) || \
 
+                                   ((REGISTER) == I2C_Register_OAR1) || \
 
+                                   ((REGISTER) == I2C_Register_OAR2) || \
 
+                                   ((REGISTER) == I2C_Register_DR) || \
 
+                                   ((REGISTER) == I2C_Register_SR1) || \
 
+                                   ((REGISTER) == I2C_Register_SR2) || \
 
+                                   ((REGISTER) == I2C_Register_CCR) || \
 
+                                   ((REGISTER) == I2C_Register_TRISE))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_NACK_position 
+  * @{
 
+  */
 
+
 
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
 
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
 
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
 
+                                         ((POSITION) == I2C_NACKPosition_Current))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
 
+  */
 
+
 
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
 
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
 
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
 
+                                   ((ALERT) == I2C_SMBusAlert_High))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_PEC_position 
+  * @{
 
+  */
 
+
 
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
 
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
 
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
 
+                                       ((POSITION) == I2C_PECPosition_Current))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup I2C_interrupts_definition 
+  * @{
 
+  */
 
+
 
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
 
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
 
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
 
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup I2C_interrupts_definition 
+  * @{
 
+  */
 
+
 
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
 
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
 
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
 
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
 
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
 
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
 
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
 
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
 
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
 
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
 
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
 
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
 
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
 
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
 
+
 
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
 
+
 
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
 
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
 
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
 
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
 
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
 
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
 
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_flags_definition 
+  * @{
 
+  */
 
+
 
+/** 
+  * @brief  SR2 register flags  
+  */
 
+
 
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
 
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
 
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
 
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
 
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
 
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
 
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
 
+
 
+/** 
+  * @brief  SR1 register flags  
+  */
 
+
 
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
 
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
 
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
 
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
 
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
 
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
 
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
 
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
 
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
 
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
 
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
 
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
 
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
 
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
 
+
 
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
+
 
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
 
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
 
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
 
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
 
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
 
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
 
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
 
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
 
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
 
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
 
+                               ((FLAG) == I2C_FLAG_SB))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_Events 
+  * @{
 
+  */
 
+
 
+/**
 
+ ===============================================================================
 
+               I2C Master Events (Events grouped in order of communication)
 
+ ===============================================================================
 
+ */
 
+
 
+/** 
+  * @brief  Communication start
 
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
 
+  * 
+  */
 
+/* --EV5 */
 
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
 
+
 
+/** 
+  * @brief  Address Acknowledge
 
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
 
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
 
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
 
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
 
+
 
+/* --EV6 */
 
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
 
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
 
+/* --EV9 */
 
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
 
+
 
+/** 
+  * @brief Communication events
 
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
 
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
 
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
 
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
 
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
 
+  *     In most cases, using EV8 is sufficient for the application.
 
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
 
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
 
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *        managed before the current byte end of transfer, then user may check on EV7 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
 
+  *        In this case the communication may be slower.
 
+  * 
+  */
 
+
 
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
 
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
 
+
 
+/* Master TRANSMITTER mode --------------------------*/
 
+/* --EV8 */
 
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
 
+/* --EV8_2 */
 
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
 
+
 
+
 
+/**
 
+ ===============================================================================
 
+               I2C Slave Events (Events grouped in order of communication)
 
+ ===============================================================================
 
+ */
 
+
 
+
 
+/** 
+  * @brief  Communication start events
 
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
 
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
 
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
 
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
 
+
 
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
 
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
 
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
 
+
 
+/* 2) Case of Dual address managed by the slave */
 
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
 
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
 
+
 
+/* 3) Case of General Call enabled for the slave */
 
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
 
+
 
+/** 
+  * @brief  Communication events
 
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
 
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
 
+  *    
+  * - Slave Transmitter mode:
 
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
 
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
 
+  *      current byte end of transfer.
 
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
 
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *        managed before the current byte end of transfer, then user may check on EV2 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
 
+  *        In this case the communication may be slower.
 
+  *
 
+  */
 
+
 
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
 
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
 
+/* --EV4  */
 
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
 
+
 
+/* Slave TRANSMITTER mode -----------------------*/
 
+/* --EV3 */
 
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
 
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
 
+/* --EV3_2 */
 
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
 
+
 
+/*
 
+ ===============================================================================
 
+                          End of Events Description
 
+ ===============================================================================
 
+ */
 
+
 
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
 
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
 
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
 
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
 
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
 
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
 
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_own_address1 
+  * @{
 
+  */
 
+
 
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_clock_speed 
+  * @{
 
+  */
 
+
 
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the I2C configuration to the default reset state *****/
 
+void I2C_DeInit(I2C_TypeDef* I2Cx);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
 
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
 
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
 
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
 
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
 
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
 
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
 
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+
 
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
 
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
 
+
 
+/* PEC management functions ***************************************************/ 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
 
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
 
+
 
+/* DMA transfers management functions *****************************************/
 
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
 
+
 
+/* Interrupts, events and flags management functions **************************/
 
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
 
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
 
+
 
+/* 
+ ===============================================================================
 
+                          I2C State Monitoring Functions
 
+ ===============================================================================
 
+  This I2C driver provides three different ways for I2C state monitoring
 
+  depending on the application requirements and constraints:
 
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
 
+     -----------------------------------------------------------
 
+        It compares the status registers (SR1 and SR2) content to a given event
 
+        (can be the combination of one or more flags).
 
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
 
+
 
+          - When to use
 
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
 
+             - It is also suitable for users who need to define their own events.
 
+
 
+          - Limitations
 
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
 
+         
+     Note 
+         For error management, it is advised to use the following functions:
 
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
 
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
 
+             Where x is the peripheral instance (I2C1, I2C2 ...)
 
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
 
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
 
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
 
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
 
+
 
+          - When to use
 
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
 
+             - The returned value could be compared to events already defined in 
+               this file or to custom values defined by user.
 
+               This function is suitable when multiple flags are monitored at the 
+               same time.
 
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
 
+
 
+          - Limitations
 
+             - User may need to define his own events.
 
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
 
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
 
+     -----------------------------------------------------------------------
 
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
 
+          - When to use
 
+             - This function could be used for specific applications or in debug 
+               phase.
 
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
 
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
 
+             - Function may need to be called twice or more in order to monitor 
+               one single event.           
+ */
 
+
 
+/*
 
+ ===============================================================================
 
+                          1. Basic state monitoring
 
+ ===============================================================================
 
+ */
 
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
 
+/*
 
+ ===============================================================================
 
+                          2. Advanced state monitoring
 
+ ===============================================================================
 
+ */
 
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
 
+/*
 
+ ===============================================================================
 
+                          3. Flag-based state monitoring
 
+ ===============================================================================
 
+ */
 
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
 
+
 
+
 
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
 
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
 
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_I2C_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 131 - 0
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@@ -0,0 +1,131 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_iwdg.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_IWDG_H
 
+#define __STM32F4xx_IWDG_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup IWDG
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup IWDG_Exported_Constants
 
+  * @{
 
+  */
 
+  
+/** @defgroup IWDG_WriteAccess
 
+  * @{
 
+  */
 
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
 
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
 
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
 
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup IWDG_prescaler 
+  * @{
 
+  */
 
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
 
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
 
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
 
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
 
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
 
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
 
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
 
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
 
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
 
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
 
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
 
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
 
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
 
+                                      ((PRESCALER) == IWDG_Prescaler_256))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup IWDG_Flag 
+  * @{
 
+  */
 
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
 
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
 
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
 
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+
 
+/* Prescaler and Counter configuration functions ******************************/
 
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
 
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
 
+void IWDG_SetReload(uint16_t Reload);
 
+void IWDG_ReloadCounter(void);
 
+
 
+/* IWDG activation function ***************************************************/
 
+void IWDG_Enable(void);
 
+
 
+/* Flag management function ***************************************************/
 
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_IWDG_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 185 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_pwr.h
Ver arquivo 

@@ -0,0 +1,185 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_pwr.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_PWR_H
 
+#define __STM32F4xx_PWR_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup PWR
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup PWR_Exported_Constants
 
+  * @{
 
+  */ 
+
 
+/** @defgroup PWR_PVD_detection_level 
+  * @{
 
+  */ 
+
 
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
 
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
 
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
 
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
 
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
 
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
 
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
 
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
 
+
 
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
 
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
 
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
 
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
 
+/**
 
+  * @}
 
+  */
 
+
 
+  
+/** @defgroup PWR_Regulator_state_in_STOP_mode 
+  * @{
 
+  */
 
+
 
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
 
+#define PWR_Regulator_LowPower          PWR_CR_LPDS
 
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
 
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
 
+  */
 
+
 
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
 
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
 
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
 
+
 
+/** @defgroup PWR_Regulator_Voltage_Scale 
+  * @{
 
+  */
 
+
 
+#define PWR_Regulator_Voltage_Scale1    ((uint32_t)0x00004000)
 
+#define PWR_Regulator_Voltage_Scale2    ((uint32_t)0x00000000)
 
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
 
+ 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Flag 
+  * @{
 
+  */
 
+
 
+#define PWR_FLAG_WU                     PWR_CSR_WUF
 
+#define PWR_FLAG_SB                     PWR_CSR_SBF
 
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
 
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
 
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
 
+
 
+/** @defgroup PWR_Flag_Legacy 
+  * @{
 
+  */
 
+#define PWR_FLAG_REGRDY                  PWR_FLAG_VOSRDY               
+/**
 
+  * @}
 
+  */
 
+
 
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
 
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
 
+                               ((FLAG) == PWR_FLAG_VOSRDY))
 
+
 
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
 
+
 
+/* Backup Domain Access function **********************************************/ 
+void PWR_BackupAccessCmd(FunctionalState NewState);
 
+
 
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
 
+void PWR_PVDCmd(FunctionalState NewState);
 
+
 
+/* WakeUp pins configuration functions ****************************************/ 
+void PWR_WakeUpPinCmd(FunctionalState NewState);
 
+
 
+/* Main and Backup Regulators configuration functions *************************/ 
+void PWR_BackupRegulatorCmd(FunctionalState NewState);
 
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
 
+
 
+/* FLASH Power Down configuration functions ***********************************/ 
+void PWR_FlashPowerDownCmd(FunctionalState NewState);
 
+
 
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
 
+void PWR_EnterSTANDBYMode(void);
 
+
 
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
 
+void PWR_ClearFlag(uint32_t PWR_FLAG);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_PWR_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 516 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_rcc.h
Ver arquivo 

@@ -0,0 +1,516 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rcc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the RCC firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_RCC_H
 
+#define __STM32F4xx_RCC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup RCC
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+typedef struct
 
+{
 
+  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
 
+  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz */
 
+  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz */
 
+  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz */
 
+}RCC_ClocksTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup RCC_Exported_Constants
 
+  * @{
 
+  */
 
+  
+/** @defgroup RCC_HSE_configuration 
+  * @{
 
+  */
 
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
 
+#define RCC_HSE_ON                       ((uint8_t)0x01)
 
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
 
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
 
+                         ((HSE) == RCC_HSE_Bypass))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
 
+  */
 
+#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
 
+#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
 
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
 
+                                   ((SOURCE) == RCC_PLLSource_HSE))
 
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
 
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
 
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
 
+ 
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))   
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_System_Clock_Source 
+  * @{
 
+  */
 
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
 
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
 
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
 
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
 
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
 
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_AHB_Clock_Source
 
+  * @{
 
+  */
 
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
 
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
 
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
 
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
 
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
 
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
 
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
 
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
 
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
 
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
 
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
 
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
 
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
 
+                           ((HCLK) == RCC_SYSCLK_Div512))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_APB1_APB2_Clock_Source
 
+  * @{
 
+  */
 
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
 
+#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
 
+#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
 
+#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
 
+#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
 
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
 
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
 
+                           ((PCLK) == RCC_HCLK_Div16))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_Interrupt_Source 
+  * @{
 
+  */
 
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
 
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
 
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
 
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
 
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
 
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
 
+#define RCC_IT_CSS                       ((uint8_t)0x80)
 
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
 
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
 
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
 
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
 
+                           ((IT) == RCC_IT_PLLI2SRDY))
 
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_LSE_Configuration 
+  * @{
 
+  */
 
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
 
+#define RCC_LSE_ON                       ((uint8_t)0x01)
 
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
 
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
 
+                         ((LSE) == RCC_LSE_Bypass))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_RTC_Clock_Source
 
+  * @{
 
+  */
 
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
 
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
 
+#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
 
+#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
 
+#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
 
+#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
 
+#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
 
+#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
 
+#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
 
+#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
 
+#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
 
+#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
 
+#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
 
+#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
 
+#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
 
+#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
 
+#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
 
+#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
 
+#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
 
+#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
 
+#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
 
+#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
 
+#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
 
+#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
 
+#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
 
+#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
 
+#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
 
+#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
 
+#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
 
+#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
 
+#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
 
+#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
 
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
 
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_I2S_Clock_Source
 
+  * @{
 
+  */
 
+#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
 
+#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
 
+
 
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_AHB1_Peripherals 
+  * @{
 
+  */ 
+#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
 
+#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
 
+#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
 
+#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
 
+#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
 
+#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
 
+#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
 
+#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
 
+#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100)
 
+#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
 
+#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
 
+#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
 
+#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
 
+#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
 
+#define RCC_AHB1Periph_CCMDATARAMEN      ((uint32_t)0x00100000)
 
+#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
 
+#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
 
+#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
 
+#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
 
+#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
 
+#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
 
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_AHB2_Peripherals 
+  * @{
 
+  */  
+#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
 
+#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
 
+#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
 
+#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
 
+#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
 
+#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_AHB3_Peripherals 
+  * @{
 
+  */ 
+#define RCC_AHB3Periph_FSMC               ((uint32_t)0x00000001)
 
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_APB1_Peripherals 
+  * @{
 
+  */ 
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
 
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
 
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
 
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
 
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
 
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
 
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
 
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
 
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
 
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
 
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
 
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
 
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
 
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
 
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
 
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
 
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
 
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
 
+#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
 
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
 
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
 
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
 
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
 
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_APB2_Peripherals 
+  * @{
 
+  */ 
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
 
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
 
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
 
+#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
 
+#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
 
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
 
+#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
 
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
 
+#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
 
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
 
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
 
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
 
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_MCO1_Clock_Source_Prescaler
 
+  * @{
 
+  */
 
+#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
 
+#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
 
+#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
 
+#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
 
+#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
 
+#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
 
+#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
 
+#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
 
+#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
 
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
 
+                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
 
+                                   
+#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
 
+                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
 
+                             ((DIV) == RCC_MCO1Div_5)) 
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_MCO2_Clock_Source_Prescaler
 
+  * @{
 
+  */
 
+#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
 
+#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
 
+#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
 
+#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
 
+#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
 
+#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
 
+#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
 
+#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
 
+#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
 
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
 
+                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
 
+                                   
+#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
 
+                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
 
+                             ((DIV) == RCC_MCO2Div_5))                             
+/**
 
+  * @}
 
+  */ 
+  
+/** @defgroup RCC_Flag 
+  * @{
 
+  */
 
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
 
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
 
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
 
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
 
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
 
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
 
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
 
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
 
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
 
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
 
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
 
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
 
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
 
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
 
+                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
 
+                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
 
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
 
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
 
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
 
+                           ((FLAG) == RCC_FLAG_PLLI2SRDY))
 
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/* Function used to set the RCC clock configuration to the default reset state */
 
+void RCC_DeInit(void);
 
+
 
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
 
+void RCC_HSEConfig(uint8_t RCC_HSE);
 
+ErrorStatus RCC_WaitForHSEStartUp(void);
 
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
 
+void RCC_HSICmd(FunctionalState NewState);
 
+void RCC_LSEConfig(uint8_t RCC_LSE);
 
+void RCC_LSICmd(FunctionalState NewState);
 
+
 
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
 
+void RCC_PLLCmd(FunctionalState NewState);
 
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
 
+void RCC_PLLI2SCmd(FunctionalState NewState);
 
+
 
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
 
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
 
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
 
+
 
+/* System, AHB and APB busses clocks configuration functions ******************/
 
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
 
+uint8_t RCC_GetSYSCLKSource(void);
 
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
 
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
 
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
 
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
 
+
 
+/* Peripheral clocks configuration functions **********************************/
 
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
 
+void RCC_RTCCLKCmd(FunctionalState NewState);
 
+void RCC_BackupResetCmd(FunctionalState NewState);
 
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 
+
 
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
 
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
 
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
 
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
 
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
 
+
 
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
 
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
 
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
 
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
 
+
 
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
 
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
 
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
 
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
 
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
 
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
 
+void RCC_ClearFlag(void);
 
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
 
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_RCC_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 120 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_rng.h
Ver arquivo 

@@ -0,0 +1,120 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rng.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the Random 
+  *          Number Generator(RNG) firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_RNG_H
 
+#define __STM32F4xx_RNG_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup RNG
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/ 
+
 
+/** @defgroup RNG_Exported_Constants
 
+  * @{
 
+  */
 
+  
+/** @defgroup RNG_flags_definition  
+  * @{
 
+  */ 
+#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /*!< Data ready */
 
+#define RNG_FLAG_CECS               ((uint8_t)0x0002) /*!< Clock error current status */
 
+#define RNG_FLAG_SECS               ((uint8_t)0x0004) /*!< Seed error current status */
 
+
 
+#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
 
+                                   ((RNG_FLAG) == RNG_FLAG_CECS) || \
 
+                                   ((RNG_FLAG) == RNG_FLAG_SECS))
 
+#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
 
+                                    ((RNG_FLAG) == RNG_FLAG_SECS))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RNG_interrupts_definition   
+  * @{
 
+  */  
+#define RNG_IT_CEI                  ((uint8_t)0x20) /*!< Clock error interrupt */
 
+#define RNG_IT_SEI                  ((uint8_t)0x40) /*!< Seed error interrupt */
 
+
 
+#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
 
+#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the RNG configuration to the default reset state *****/ 
+void RNG_DeInit(void);
 
+
 
+/* Configuration function *****************************************************/
 
+void RNG_Cmd(FunctionalState NewState);
 
+
 
+/* Get 32 bit Random number function ******************************************/
 
+uint32_t RNG_GetRandomNumber(void);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void RNG_ITConfig(FunctionalState NewState);
 
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
 
+void RNG_ClearFlag(uint8_t RNG_FLAG);
 
+ITStatus RNG_GetITStatus(uint8_t RNG_IT);
 
+void RNG_ClearITPendingBit(uint8_t RNG_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_RNG_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 881 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_rtc.h
Ver arquivo 

@@ -0,0 +1,881 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rtc.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the RTC firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_RTC_H
 
+#define __STM32F4xx_RTC_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup RTC
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
 
+{
 
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
 
+                             This parameter can be a value of @ref RTC_Hour_Formats */
 
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
 
+                             This parameter must be set to a value lower than 0x7F */
 
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
 
+                             This parameter must be set to a value lower than 0x7FFF */
 
+}RTC_InitTypeDef;
 
+
 
+/** 
+  * @brief  RTC Time structure definition  
+  */
 
+typedef struct
 
+{
 
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
 
+                        This parameter must be set to a value in the 0-12 range
 
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
 
+                        the RTC_HourFormat_24 is selected. */
 
+
 
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
 
+                        This parameter must be set to a value in the 0-59 range. */
 
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
 
+                        This parameter must be set to a value in the 0-59 range. */
 
+
 
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
 
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
 
+}RTC_TimeTypeDef; 
+
 
+/** 
+  * @brief  RTC Date structure definition  
+  */
 
+typedef struct
 
+{
 
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
 
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
 
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
 
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
 
+
 
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
 
+                        This parameter must be set to a value in the 1-31 range. */
 
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
 
+                        This parameter must be set to a value in the 0-99 range. */
 
+}RTC_DateTypeDef;
 
+
 
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
 
+typedef struct
 
+{
 
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
 
+
 
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
 
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
 
+
 
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
 
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
 
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
 
+                                     If the Alarm Date is selected, this parameter
 
+                                     must be set to a value in the 1-31 range.
 
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
 
+}RTC_AlarmTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup RTC_Exported_Constants
 
+  * @{
 
+  */ 
+
 
+
 
+/** @defgroup RTC_Hour_Formats 
+  * @{
 
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
 
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
 
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
 
+                                        ((FORMAT) == RTC_HourFormat_24))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
 
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
 
+ 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
 
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Time_Definitions 
+  * @{
 
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
 
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
 
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
 
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
 
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
 
+#define RTC_H12_PM                     ((uint8_t)0x40)
 
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
 
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
 
+  */ 
+
 
+/* Coded in BCD format */
 
+#define RTC_Month_January              ((uint8_t)0x01)
 
+#define RTC_Month_February             ((uint8_t)0x02)
 
+#define RTC_Month_March                ((uint8_t)0x03)
 
+#define RTC_Month_April                ((uint8_t)0x04)
 
+#define RTC_Month_May                  ((uint8_t)0x05)
 
+#define RTC_Month_June                 ((uint8_t)0x06)
 
+#define RTC_Month_July                 ((uint8_t)0x07)
 
+#define RTC_Month_August               ((uint8_t)0x08)
 
+#define RTC_Month_September            ((uint8_t)0x09)
 
+#define RTC_Month_October              ((uint8_t)0x10)
 
+#define RTC_Month_November             ((uint8_t)0x11)
 
+#define RTC_Month_December             ((uint8_t)0x12)
 
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
 
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
 
+  */ 
+  
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
 
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
 
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
 
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
 
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
 
+#define RTC_Weekday_Saturday           ((uint8_t)0x06)
 
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
 
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
 
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup RTC_Alarm_Definitions
 
+  * @{
 
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
 
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
 
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
 
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
 
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
 
+
 
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
 
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
 
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
 
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
 
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
 
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
 
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
 
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
 
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
 
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
 
+#define RTC_Alarm_B                       ((uint32_t)0x00000200)
 
+#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
 
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
 
+  * @{
 
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
 
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
 
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
 
+#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
 
+#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
 
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
 
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
 
+  * @{
 
+  */ 
+
 
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
 
+  */ 
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
 
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
 
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
 
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
 
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
 
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
 
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
 
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
 
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
 
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
 
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
 
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
 
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
 
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
 
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
 
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
 
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
 
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
 
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
 
+#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
 
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
 
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
 
+                               ((OUTPUT) == RTC_Output_AlarmA) || \
 
+                               ((OUTPUT) == RTC_Output_AlarmB) || \
 
+                               ((OUTPUT) == RTC_Output_WakeUp))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
 
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
 
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
 
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
 
+                                ((POL) == RTC_OutputPolarity_Low))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
 
+  */ 
+#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
+#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
 
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
 
+                                 ((SIGN) == RTC_CalibSign_Negative))
 
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
 
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
 
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
 
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
 
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
 
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
 
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
 
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
 
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
 
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
 
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
 
+                                          
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
 
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
 
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
 
+                                                                 during a 32-second window =   CALM[8:0]. */
 
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
 
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
 
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
 
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
 
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
 
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
 
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
 
+
 
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
 
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
 
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
 
+                                           ((OPERATION) == RTC_StoreOperation_Set))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
 
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
 
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
 
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
 
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
 
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
 
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
 
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
 
+
 
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
 
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
 
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
 
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
 
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
 
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
 
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
 
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 32768 */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
 
+                                                                            with a frequency =  RTCCLK / 16384 */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 8192  */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 4096  */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 2048  */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 1024  */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 512   */
 
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
 
+                                                                           with a frequency =  RTCCLK / 256   */
 
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
 
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
 
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
 
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
 
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
 
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
 
+
 
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
 
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
 
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
 
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
 
+  */ 
+#define RTC_Tamper_1                    RTC_TAFCR_TAMP1E
 
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Tamper_Pin_Selection 
+  * @{
 
+  */ 
+#define RTC_TamperPin_PC13                 ((uint32_t)0x00000000)
 
+#define RTC_TamperPin_PI8                  ((uint32_t)0x00010000)
 
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
 
+                                ((PIN) == RTC_TamperPin_PI8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_TimeStamp_Pin_Selection 
+  * @{
 
+  */ 
+#define RTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
 
+#define RTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
 
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
 
+                                   ((PIN) == RTC_TimeStampPin_PI8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
 
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
 
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
 
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
 
+                                  ((TYPE) == RTC_OutputType_PushPull))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
 
+  * @{
 
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
 
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
 
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
 
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
 
+  * @{
 
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
 
+  */
 
+
 
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
 
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
 
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
 
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
 
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
 
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
 
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
 
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
 
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
 
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
 
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
 
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
 
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
 
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
 
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
 
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
 
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
 
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
 
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
 
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
 
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
 
+                                           ((BKP) == RTC_BKP_DR1) || \
 
+                                           ((BKP) == RTC_BKP_DR2) || \
 
+                                           ((BKP) == RTC_BKP_DR3) || \
 
+                                           ((BKP) == RTC_BKP_DR4) || \
 
+                                           ((BKP) == RTC_BKP_DR5) || \
 
+                                           ((BKP) == RTC_BKP_DR6) || \
 
+                                           ((BKP) == RTC_BKP_DR7) || \
 
+                                           ((BKP) == RTC_BKP_DR8) || \
 
+                                           ((BKP) == RTC_BKP_DR9) || \
 
+                                           ((BKP) == RTC_BKP_DR10) || \
 
+                                           ((BKP) == RTC_BKP_DR11) || \
 
+                                           ((BKP) == RTC_BKP_DR12) || \
 
+                                           ((BKP) == RTC_BKP_DR13) || \
 
+                                           ((BKP) == RTC_BKP_DR14) || \
 
+                                           ((BKP) == RTC_BKP_DR15) || \
 
+                                           ((BKP) == RTC_BKP_DR16) || \
 
+                                           ((BKP) == RTC_BKP_DR17) || \
 
+                                           ((BKP) == RTC_BKP_DR18) || \
 
+                                           ((BKP) == RTC_BKP_DR19))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
 
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
 
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
 
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Flags_Definitions 
+  * @{
 
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
 
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
 
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
 
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
 
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
 
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
 
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
 
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
 
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
 
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
 
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
 
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
 
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
 
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
 
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
 
+                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
 
+                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
 
+                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
 
+                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
 
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
 
+                                ((FLAG) == RTC_FLAG_SHPF))
 
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
 
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
 
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
 
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
 
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
 
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
 
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
 
+
 
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
 
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
 
+                           ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
 
+                           ((IT) == RTC_IT_TAMP1))
 
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup RTC_Legacy 
+  * @{
 
+  */ 
+#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
 
+#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the RTC configuration to the default reset state *****/
 
+ErrorStatus RTC_DeInit(void);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
 
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
 
+void RTC_WriteProtectionCmd(FunctionalState NewState);
 
+ErrorStatus RTC_EnterInitMode(void);
 
+void RTC_ExitInitMode(void);
 
+ErrorStatus RTC_WaitForSynchro(void);
 
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
 
+void RTC_BypassShadowCmd(FunctionalState NewState);
 
+
 
+/* Time and Date configuration functions **************************************/
 
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
 
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
 
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
 
+uint32_t RTC_GetSubSecond(void);
 
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
 
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
 
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
 
+
 
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
 
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
 
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
 
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
 
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
 
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
 
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
 
+
 
+/* WakeUp Timer configuration functions ***************************************/
 
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
 
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
 
+uint32_t RTC_GetWakeUpCounter(void);
 
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
 
+
 
+/* Daylight Saving configuration functions ************************************/
 
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
 
+uint32_t RTC_GetStoreOperation(void);
 
+
 
+/* Output pin Configuration function ******************************************/
 
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
 
+
 
+/* Digital Calibration configuration functions *********************************/
 
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
 
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
 
+void RTC_CalibOutputCmd(FunctionalState NewState);
 
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
 
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
 
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
 
+
 
+/* TimeStamp configuration functions ******************************************/
 
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
 
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
 
+                                      RTC_DateTypeDef* RTC_StampDateStruct);
 
+uint32_t RTC_GetTimeStampSubSecond(void);
 
+
 
+/* Tampers configuration functions ********************************************/
 
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
 
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
 
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
 
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
 
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
 
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
 
+void RTC_TamperPullUpCmd(FunctionalState NewState);
 
+
 
+/* Backup Data Registers configuration functions ******************************/
 
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
 
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
 
+
 
+/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
 
+   functions ******************************************************************/
 
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
 
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
 
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
 
+
 
+/* RTC_Shift_control_synchonisation_functions *********************************/
 
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
 
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
 
+void RTC_ClearFlag(uint32_t RTC_FLAG);
 
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
 
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_RTC_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 536 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_sdio.h
Ver arquivo 

@@ -0,0 +1,536 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_sdio.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_SDIO_H
 
+#define __STM32F4xx_SDIO_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup SDIO
 
+  * @{
 
+  */
 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+typedef struct
 
+{
 
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
 
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
 
+
 
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
 
+                                           enabled or disabled.
 
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
 
+
 
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
 
+                                           disabled when the bus is idle.
 
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
 
+
 
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
 
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
 
+
 
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
 
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
 
+
 
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
 
+                                           This parameter can be a value between 0x00 and 0xFF. */
 
+                                           
+} SDIO_InitTypeDef;
 
+
 
+typedef struct
 
+{
 
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
 
+                                to a card as part of a command message. If a command
 
+                                contains an argument, it must be loaded into this register
 
+                                before writing the command to the command register */
 
+
 
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
 
+
 
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
 
+                                This parameter can be a value of @ref SDIO_Response_Type */
 
+
 
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
 
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
 
+
 
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
 
+                                is enabled or disabled.
 
+                                This parameter can be a value of @ref SDIO_CPSM_State */
 
+} SDIO_CmdInitTypeDef;
 
+
 
+typedef struct
 
+{
 
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
 
+
 
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
 
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
 
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
 
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
 
+                                     is a read or write.
 
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
 
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
 
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
 
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
 
+                                     is enabled or disabled.
 
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
 
+} SDIO_DataInitTypeDef;
 
+
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup SDIO_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SDIO_Clock_Edge 
+  * @{
 
+  */
 
+
 
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
 
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
 
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
 
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
 
+  */
 
+
 
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
 
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
 
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
 
+  */
 
+
 
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
 
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
 
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Bus_Wide 
+  * @{
 
+  */
 
+
 
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
 
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
 
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
 
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
 
+                                ((WIDE) == SDIO_BusWide_8b))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
 
+  */
 
+
 
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
 
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
 
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
 
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Power_State 
+  * @{
 
+  */
 
+
 
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
 
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
 
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup SDIO_Interrupt_sources
 
+  * @{
 
+  */
 
+
 
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
 
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
 
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
 
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
 
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
 
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
 
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
 
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
 
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
 
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
 
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
 
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
 
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
 
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
 
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
 
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
 
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
 
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
 
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
 
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
 
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
 
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
 
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
 
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
 
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SDIO_Command_Index
 
+  * @{
 
+  */
 
+
 
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Response_Type
 
+  * @{
 
+  */
 
+
 
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
 
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
 
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
 
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
 
+                                    ((RESPONSE) == SDIO_Response_Short) || \
 
+                                    ((RESPONSE) == SDIO_Response_Long))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Wait_Interrupt_State
 
+  * @{
 
+  */
 
+
 
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
 
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
 
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
 
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
 
+                            ((WAIT) == SDIO_Wait_Pend))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_CPSM_State
 
+  * @{
 
+  */
 
+
 
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
 
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
 
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SDIO_Response_Registers
 
+  * @{
 
+  */
 
+
 
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
 
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
 
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
 
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
 
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
 
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Data_Length 
+  * @{
 
+  */
 
+
 
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
 
+  */
 
+
 
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
 
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
 
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
 
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
 
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
 
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
 
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
 
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
 
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
 
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
 
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
 
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
 
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
 
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
 
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
 
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
 
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
 
+  */
 
+
 
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
 
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
 
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
 
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Transfer_Type 
+  * @{
 
+  */
 
+
 
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
 
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
 
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
 
+                                     ((MODE) == SDIO_TransferMode_Block))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_DPSM_State 
+  * @{
 
+  */
 
+
 
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
 
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
 
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Flags 
+  * @{
 
+  */
 
+
 
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
 
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
 
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
 
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
 
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
 
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
 
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
 
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
 
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
 
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
 
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
 
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
 
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
 
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
 
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
 
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
 
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
 
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
 
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
 
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
 
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
 
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
 
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
 
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
 
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
 
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
 
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
 
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
 
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
 
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
 
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
 
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
 
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
 
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
 
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
 
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
 
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
 
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
 
+
 
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
 
+
 
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
 
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
 
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
 
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
 
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
 
+                            ((IT)  == SDIO_IT_RXOVERR) || \
 
+                            ((IT)  == SDIO_IT_CMDREND) || \
 
+                            ((IT)  == SDIO_IT_CMDSENT) || \
 
+                            ((IT)  == SDIO_IT_DATAEND) || \
 
+                            ((IT)  == SDIO_IT_STBITERR) || \
 
+                            ((IT)  == SDIO_IT_DBCKEND) || \
 
+                            ((IT)  == SDIO_IT_CMDACT) || \
 
+                            ((IT)  == SDIO_IT_TXACT) || \
 
+                            ((IT)  == SDIO_IT_RXACT) || \
 
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
 
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
 
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
 
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
 
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
 
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
 
+                            ((IT)  == SDIO_IT_TXDAVL) || \
 
+                            ((IT)  == SDIO_IT_RXDAVL) || \
 
+                            ((IT)  == SDIO_IT_SDIOIT) || \
 
+                            ((IT)  == SDIO_IT_CEATAEND))
 
+
 
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
 
+  */
 
+
 
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000000)
 
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000001)
 
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
 
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+/*  Function used to set the SDIO configuration to the default reset state ****/
 
+void SDIO_DeInit(void);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
 
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
 
+void SDIO_ClockCmd(FunctionalState NewState);
 
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
 
+uint32_t SDIO_GetPowerState(void);
 
+
 
+/* Command path state machine (CPSM) management functions *********************/
 
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
 
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
 
+uint8_t SDIO_GetCommandResponse(void);
 
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
 
+
 
+/* Data path state machine (DPSM) management functions ************************/
 
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
 
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
 
+uint32_t SDIO_GetDataCounter(void);
 
+uint32_t SDIO_ReadData(void);
 
+void SDIO_WriteData(uint32_t Data);
 
+uint32_t SDIO_GetFIFOCount(void);
 
+
 
+/* SDIO IO Cards mode management functions ************************************/
 
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
 
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
 
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
 
+void SDIO_SetSDIOOperation(FunctionalState NewState);
 
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
 
+
 
+/* CE-ATA mode management functions *******************************************/
 
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
 
+void SDIO_CEATAITCmd(FunctionalState NewState);
 
+void SDIO_SendCEATACmd(FunctionalState NewState);
 
+
 
+/* DMA transfers management functions *****************************************/
 
+void SDIO_DMACmd(FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
 
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
 
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
 
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
 
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_SDIO_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 543 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_spi.h
Ver arquivo 

@@ -0,0 +1,543 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_spi.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_SPI_H
 
+#define __STM32F4xx_SPI_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup SPI
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  SPI Init structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
 
+                                         This parameter can be a value of @ref SPI_data_direction */
 
+
 
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
 
+                                         This parameter can be a value of @ref SPI_mode */
 
+
 
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
 
+                                         This parameter can be a value of @ref SPI_data_size */
 
+
 
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
 
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
 
+
 
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
 
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
 
+
 
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
 
+                                         hardware (NSS pin) or by software using the SSI bit.
 
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
 
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
 
+                                         used to configure the transmit and receive SCK clock.
 
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
 
+                                         @note The communication clock is derived from the master
 
+                                               clock. The slave clock does not need to be set. */
 
+
 
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
 
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
 
+
 
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
 
+}SPI_InitTypeDef;
 
+
 
+/** 
+  * @brief  I2S Init structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+
 
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
 
+                                  This parameter can be a value of @ref I2S_Mode */
 
+
 
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
 
+                                  This parameter can be a value of @ref I2S_Standard */
 
+
 
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
 
+                                  This parameter can be a value of @ref I2S_Data_Format */
 
+
 
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
 
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
 
+
 
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
 
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
 
+
 
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
 
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
 
+}I2S_InitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup SPI_Exported_Constants
 
+  * @{
 
+  */
 
+
 
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
 
+                                   ((PERIPH) == SPI2) || \
 
+                                   ((PERIPH) == SPI3))
 
+
 
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
 
+                                       ((PERIPH) == SPI2) || \
 
+                                       ((PERIPH) == SPI3) || \
 
+                                       ((PERIPH) == I2S2ext) || \
 
+                                       ((PERIPH) == I2S3ext))
 
+
 
+#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
 
+                                   ((PERIPH) == SPI3))
 
+
 
+#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2) || \
 
+                                       ((PERIPH) == SPI3) || \
 
+                                       ((PERIPH) == I2S2ext) || \
 
+                                       ((PERIPH) == I2S3ext))
 
+
 
+#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) || \
 
+                                    ((PERIPH) == I2S3ext))
 
+
 
+
 
+/** @defgroup SPI_data_direction 
+  * @{
 
+  */
 
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
 
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
 
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
 
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
 
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
 
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
 
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
 
+                                     ((MODE) == SPI_Direction_1Line_Tx))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_mode 
+  * @{
 
+  */
 
+
 
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
 
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
 
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
 
+                           ((MODE) == SPI_Mode_Slave))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_data_size 
+  * @{
 
+  */
 
+
 
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
 
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
 
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
 
+                                   ((DATASIZE) == SPI_DataSize_8b))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SPI_Clock_Polarity 
+  * @{
 
+  */
 
+
 
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
 
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
 
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
 
+                           ((CPOL) == SPI_CPOL_High))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Clock_Phase 
+  * @{
 
+  */
 
+
 
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
 
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
 
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
 
+                           ((CPHA) == SPI_CPHA_2Edge))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Slave_Select_management 
+  * @{
 
+  */
 
+
 
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
 
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
 
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
 
+                         ((NSS) == SPI_NSS_Hard))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
 
+  */
 
+
 
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
 
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
 
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
 
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
 
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
 
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
 
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
 
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
 
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
 
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
 
+  */
 
+
 
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
 
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
 
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
 
+                               ((BIT) == SPI_FirstBit_LSB))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_Mode 
+  * @{
 
+  */
 
+
 
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
 
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
 
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
 
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
 
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
 
+                           ((MODE) == I2S_Mode_SlaveRx) || \
 
+                           ((MODE) == I2S_Mode_MasterTx)|| \
 
+                           ((MODE) == I2S_Mode_MasterRx))
 
+/**
 
+  * @}
 
+  */
 
+  
+
 
+/** @defgroup SPI_I2S_Standard 
+  * @{
 
+  */
 
+
 
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
 
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
 
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
 
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
 
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
 
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
 
+                                   ((STANDARD) == I2S_Standard_MSB) || \
 
+                                   ((STANDARD) == I2S_Standard_LSB) || \
 
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
 
+                                   ((STANDARD) == I2S_Standard_PCMLong))
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
 
+  */
 
+
 
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
 
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
 
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
 
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
 
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
 
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
 
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
 
+                                    ((FORMAT) == I2S_DataFormat_32b))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
 
+  */
 
+
 
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
 
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
 
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
 
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
 
+  */
 
+
 
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
 
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
 
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
 
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
 
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
 
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
 
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
 
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
 
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
 
+#define I2S_AudioFreq_Default            ((uint32_t)2)
 
+
 
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
 
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
 
+                                 ((FREQ) == I2S_AudioFreq_Default))
 
+/**
 
+  * @}
 
+  */
 
+            
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
 
+  */
 
+
 
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
 
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
 
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
 
+                           ((CPOL) == I2S_CPOL_High))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
 
+  */
 
+
 
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
 
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
 
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
 
+  */
 
+
 
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
 
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
 
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
 
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
 
+  */
 
+
 
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
 
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
 
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
 
+  */
 
+
 
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
 
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
 
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
 
+                                     ((DIRECTION) == SPI_Direction_Tx))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
 
+  */
 
+
 
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
 
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
 
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
 
+#define I2S_IT_UDR                      ((uint8_t)0x53)
 
+#define SPI_I2S_IT_TIFRFE               ((uint8_t)0x58)
 
+
 
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
 
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
 
+                                  ((IT) == SPI_I2S_IT_ERR))
 
+
 
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
 
+#define SPI_IT_MODF                     ((uint8_t)0x55)
 
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
 
+
 
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
 
+
 
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
 
+                               ((IT) == SPI_IT_CRCERR)  || ((IT) == SPI_IT_MODF) || \
 
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
 
+                               ((IT) == SPI_I2S_IT_TIFRFE))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
 
+  */
 
+
 
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
 
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
 
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
 
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
 
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
 
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
 
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
 
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
 
+#define SPI_I2S_FLAG_TIFRFE             ((uint16_t)0x0100)
 
+
 
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
 
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
 
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
 
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
 
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
 
+                                   ((FLAG) == SPI_I2S_FLAG_TIFRFE))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_CRC_polynomial 
+  * @{
 
+  */
 
+
 
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_I2S_Legacy 
+  * @{
 
+  */
 
+
 
+#define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
 
+#define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
 
+#define SPI_IT_TXE                   SPI_I2S_IT_TXE
 
+#define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
 
+#define SPI_IT_ERR                   SPI_I2S_IT_ERR
 
+#define SPI_IT_OVR                   SPI_I2S_IT_OVR
 
+#define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
 
+#define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
 
+#define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
 
+#define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
 
+#define SPI_DeInit                   SPI_I2S_DeInit
 
+#define SPI_ITConfig                 SPI_I2S_ITConfig
 
+#define SPI_DMACmd                   SPI_I2S_DMACmd
 
+#define SPI_SendData                 SPI_I2S_SendData
 
+#define SPI_ReceiveData              SPI_I2S_ReceiveData
 
+#define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
 
+#define SPI_ClearFlag                SPI_I2S_ClearFlag
 
+#define SPI_GetITStatus              SPI_I2S_GetITStatus
 
+#define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
 
+/**
 
+  * @}
 
+  */
 
+  
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/*  Function used to set the SPI configuration to the default reset state *****/ 
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
 
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
 
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
 
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
 
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
 
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
 
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
 
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
 
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
 
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
 
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
 
+
 
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
 
+
 
+/* Data transfers functions ***************************************************/ 
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
 
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
 
+
 
+/* Hardware CRC Calculation functions *****************************************/
 
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
 
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
 
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
 
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
 
+
 
+/* DMA transfers management functions *****************************************/
 
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
 
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
 
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
 
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
 
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_SPI_H */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 179 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_syscfg.h
Ver arquivo 

@@ -0,0 +1,179 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_syscfg.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_SYSCFG_H
 
+#define __STM32F4xx_SYSCFG_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup SYSCFG
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+  
+/** @defgroup SYSCFG_Exported_Constants 
+  * @{
 
+  */ 
+
 
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
 
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
 
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
 
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
 
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
 
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
 
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
 
+#define EXTI_PortSourceGPIOG       ((uint8_t)0x06)
 
+#define EXTI_PortSourceGPIOH       ((uint8_t)0x07)
 
+#define EXTI_PortSourceGPIOI       ((uint8_t)0x08)
 
+                                      
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
 
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOI)) 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup SYSCFG_EXTI_Pin_Sources 
+  * @{
 
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
 
+#define EXTI_PinSource1            ((uint8_t)0x01)
 
+#define EXTI_PinSource2            ((uint8_t)0x02)
 
+#define EXTI_PinSource3            ((uint8_t)0x03)
 
+#define EXTI_PinSource4            ((uint8_t)0x04)
 
+#define EXTI_PinSource5            ((uint8_t)0x05)
 
+#define EXTI_PinSource6            ((uint8_t)0x06)
 
+#define EXTI_PinSource7            ((uint8_t)0x07)
 
+#define EXTI_PinSource8            ((uint8_t)0x08)
 
+#define EXTI_PinSource9            ((uint8_t)0x09)
 
+#define EXTI_PinSource10           ((uint8_t)0x0A)
 
+#define EXTI_PinSource11           ((uint8_t)0x0B)
 
+#define EXTI_PinSource12           ((uint8_t)0x0C)
 
+#define EXTI_PinSource13           ((uint8_t)0x0D)
 
+#define EXTI_PinSource14           ((uint8_t)0x0E)
 
+#define EXTI_PinSource15           ((uint8_t)0x0F)
 
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
 
+                                       ((PINSOURCE) == EXTI_PinSource15))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
 
+  */ 
+#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)
 
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
 
+#define SYSCFG_MemoryRemap_FSMC        ((uint8_t)0x02)
 
+#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)
 
+   
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
 
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
 
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
 
+                                                     ((REMAP) == SYSCFG_MemoryRemap_FSMC))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup SYSCFG_ETHERNET_Media_Interface 
+  * @{
 
+  */ 
+#define SYSCFG_ETH_MediaInterface_MII    ((uint32_t)0x00000000) 
+#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)                                       
+
 
+#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
 
+                                                ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+ 
+void SYSCFG_DeInit(void);
 
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
 
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
 
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); 
+void SYSCFG_CompensationCellCmd(FunctionalState NewState); 
+FlagStatus SYSCFG_GetCompensationCellStatus(void);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_SYSCFG_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1150 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_tim.h
Ver arquivo 

@@ -0,0 +1,1150 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_tim.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the TIM firmware 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_TIM_H
 
+#define __STM32F4xx_TIM_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup TIM
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+
 
+/** 
+  * @brief  TIM Time Base Init structure definition  
+  * @note   This structure is used with all TIMx except for TIM6 and TIM7.  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
 
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
 
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
 
+
 
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
 
+                                       Auto-Reload Register at the next update event.
 
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
 
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
 
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
 
+
 
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
 
+                                       reaches zero, an update event is generated and counting restarts
 
+                                       from the RCR value (N).
 
+                                       This means in PWM mode that (N+1) corresponds to:
 
+                                          - the number of PWM periods in edge-aligned mode
 
+                                          - the number of half PWM period in center-aligned mode
 
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM1 and TIM8. */
 
+} TIM_TimeBaseInitTypeDef; 
+
 
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
 
+
 
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_State */
 
+
 
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_State
 
+                                   @note This parameter is valid only for TIM1 and TIM8. */
 
+
 
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF */
 
+
 
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
 
+
 
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
 
+                                   @note This parameter is valid only for TIM1 and TIM8. */
 
+
 
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
 
+                                   @note This parameter is valid only for TIM1 and TIM8. */
 
+
 
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
 
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
 
+                                   @note This parameter is valid only for TIM1 and TIM8. */
 
+} TIM_OCInitTypeDef;
 
+
 
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
 
+
 
+typedef struct
 
+{
 
+
 
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
 
+                                  This parameter can be a value of @ref TIM_Channel */
 
+
 
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
 
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
 
+
 
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
 
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
 
+
 
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
 
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
 
+
 
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
 
+                                  This parameter can be a number between 0x0 and 0xF */
 
+} TIM_ICInitTypeDef;
 
+
 
+/** 
+  * @brief  BDTR structure definition 
+  * @note   This structure is used only with TIM1 and TIM8.    
+  */
 
+
 
+typedef struct
 
+{
 
+
 
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
 
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
 
+
 
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
 
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
 
+
 
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
 
+                                      This parameter can be a value of @ref TIM_Lock_level */ 
+
 
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
 
+                                      switching-on of the outputs.
 
+                                      This parameter can be a number between 0x00 and 0xFF  */
 
+
 
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
 
+
 
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
 
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
 
+
 
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
 
+} TIM_BDTRInitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup TIM_Exported_constants 
+  * @{
 
+  */
 
+
 
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                   ((PERIPH) == TIM2) || \
 
+                                   ((PERIPH) == TIM3) || \
 
+                                   ((PERIPH) == TIM4) || \
 
+                                   ((PERIPH) == TIM5) || \
 
+                                   ((PERIPH) == TIM6) || \
 
+                                   ((PERIPH) == TIM7) || \
 
+                                   ((PERIPH) == TIM8) || \
 
+                                   ((PERIPH) == TIM9) || \
 
+                                   ((PERIPH) == TIM10) || \
 
+                                   ((PERIPH) == TIM11) || \
 
+                                   ((PERIPH) == TIM12) || \
 
+                                   (((PERIPH) == TIM13) || \
 
+                                   ((PERIPH) == TIM14)))
 
+/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */                                         
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                     ((PERIPH) == TIM2) || \
 
+                                     ((PERIPH) == TIM3) || \
 
+                                     ((PERIPH) == TIM4) || \
 
+                                     ((PERIPH) == TIM5) || \
 
+                                     ((PERIPH) == TIM8) || \
 
+                                     ((PERIPH) == TIM9) || \
 
+                                     ((PERIPH) == TIM10) || \
 
+                                     ((PERIPH) == TIM11) || \
 
+                                     ((PERIPH) == TIM12) || \
 
+                                     ((PERIPH) == TIM13) || \
 
+                                     ((PERIPH) == TIM14))
 
+                                     
+/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
 
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                     ((PERIPH) == TIM2) || \
 
+                                     ((PERIPH) == TIM3) || \
 
+                                     ((PERIPH) == TIM4) || \
 
+                                     ((PERIPH) == TIM5) || \
 
+                                     ((PERIPH) == TIM8) || \
 
+                                     ((PERIPH) == TIM9) || \
 
+                                     ((PERIPH) == TIM12))
 
+/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
 
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                     ((PERIPH) == TIM2) || \
 
+                                     ((PERIPH) == TIM3) || \
 
+                                     ((PERIPH) == TIM4) || \
 
+                                     ((PERIPH) == TIM5) || \
 
+                                     ((PERIPH) == TIM8))
 
+/* LIST4: TIM1 and TIM8 */
 
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                     ((PERIPH) == TIM8))
 
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
 
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
 
+                                     ((PERIPH) == TIM2) || \
 
+                                     ((PERIPH) == TIM3) || \
 
+                                     ((PERIPH) == TIM4) || \
 
+                                     ((PERIPH) == TIM5) || \
 
+                                     ((PERIPH) == TIM6) || \
 
+                                     ((PERIPH) == TIM7) || \
 
+                                     ((PERIPH) == TIM8))
 
+/* LIST6: TIM2, TIM5 and TIM11 */                               
+#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
 
+                                 ((TIMx) == TIM5) || \
 
+                                 ((TIMx) == TIM11))
 
+
 
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
 
+  */
 
+
 
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
 
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
 
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
 
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
 
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
 
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
 
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
 
+                              ((MODE) == TIM_OCMode_Active) || \
 
+                              ((MODE) == TIM_OCMode_Inactive) || \
 
+                              ((MODE) == TIM_OCMode_Toggle)|| \
 
+                              ((MODE) == TIM_OCMode_PWM1) || \
 
+                              ((MODE) == TIM_OCMode_PWM2))
 
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
 
+                          ((MODE) == TIM_OCMode_Active) || \
 
+                          ((MODE) == TIM_OCMode_Inactive) || \
 
+                          ((MODE) == TIM_OCMode_Toggle)|| \
 
+                          ((MODE) == TIM_OCMode_PWM1) || \
 
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
 
+                          ((MODE) == TIM_ForcedAction_Active) || \
 
+                          ((MODE) == TIM_ForcedAction_InActive))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
 
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
 
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
 
+                               ((MODE) == TIM_OPMode_Repetitive))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Channel 
+  * @{
 
+  */
 
+
 
+#define TIM_Channel_1                      ((uint16_t)0x0000)
 
+#define TIM_Channel_2                      ((uint16_t)0x0004)
 
+#define TIM_Channel_3                      ((uint16_t)0x0008)
 
+#define TIM_Channel_4                      ((uint16_t)0x000C)
 
+                                 
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
 
+                                 ((CHANNEL) == TIM_Channel_2) || \
 
+                                 ((CHANNEL) == TIM_Channel_3) || \
 
+                                 ((CHANNEL) == TIM_Channel_4))
 
+                                 
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
 
+                                      ((CHANNEL) == TIM_Channel_2))
 
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
 
+                                               ((CHANNEL) == TIM_Channel_2) || \
 
+                                               ((CHANNEL) == TIM_Channel_3))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
 
+  */
 
+
 
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
 
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
 
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
 
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
 
+                             ((DIV) == TIM_CKD_DIV2) || \
 
+                             ((DIV) == TIM_CKD_DIV4))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Counter_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
 
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
 
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
 
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
 
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
 
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
 
+                                   ((MODE) == TIM_CounterMode_Down) || \
 
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
 
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
 
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
 
+  */
 
+
 
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
 
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
 
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
 
+                                      ((POLARITY) == TIM_OCPolarity_Low))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
 
+  */
 
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
 
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
 
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
 
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Output_Compare_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
 
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
 
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
 
+                                    ((STATE) == TIM_OutputState_Enable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_N_State
 
+  * @{
 
+  */
 
+
 
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
 
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
 
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
 
+                                     ((STATE) == TIM_OutputNState_Enable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Capture_Compare_State
 
+  * @{
 
+  */
 
+
 
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
 
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
 
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
 
+                         ((CCX) == TIM_CCx_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Capture_Compare_N_State
 
+  * @{
 
+  */
 
+
 
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
 
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
 
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
 
+                           ((CCXN) == TIM_CCxN_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Break_Input_enable_disable 
+  * @{
 
+  */
 
+
 
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
 
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
 
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
 
+                                   ((STATE) == TIM_Break_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Break_Polarity 
+  * @{
 
+  */
 
+
 
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
 
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
 
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
 
+                                         ((POLARITY) == TIM_BreakPolarity_High))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
 
+  */
 
+
 
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
 
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
 
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
 
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Lock_level
 
+  * @{
 
+  */
 
+
 
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
 
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
 
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
 
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
 
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
 
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
 
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
 
+                                  ((LEVEL) == TIM_LOCKLevel_3))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
 
+  */
 
+
 
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
 
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
 
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
 
+                                  ((STATE) == TIM_OSSIState_Disable))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
 
+  * @{
 
+  */
 
+
 
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
 
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
 
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
 
+                                  ((STATE) == TIM_OSSRState_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
 
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
 
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
 
+                                    ((STATE) == TIM_OCIdleState_Reset))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
 
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
 
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
 
+                                     ((STATE) == TIM_OCNIdleState_Reset))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
 
+  */
 
+
 
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
 
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
 
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
 
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
 
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
 
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
 
+  */
 
+
 
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
 
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
 
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
 
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
 
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
 
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
 
+                                        ((SELECTION) == TIM_ICSelection_TRC))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
 
+  */
 
+
 
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
 
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
 
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
 
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
 
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
 
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
 
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
 
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_interrupt_sources 
+  * @{
 
+  */
 
+
 
+#define TIM_IT_Update                      ((uint16_t)0x0001)
 
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
 
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
 
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
 
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
 
+#define TIM_IT_COM                         ((uint16_t)0x0020)
 
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
 
+#define TIM_IT_Break                       ((uint16_t)0x0080)
 
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
 
+
 
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
 
+                           ((IT) == TIM_IT_CC1) || \
 
+                           ((IT) == TIM_IT_CC2) || \
 
+                           ((IT) == TIM_IT_CC3) || \
 
+                           ((IT) == TIM_IT_CC4) || \
 
+                           ((IT) == TIM_IT_COM) || \
 
+                           ((IT) == TIM_IT_Trigger) || \
 
+                           ((IT) == TIM_IT_Break))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_DMA_Base_address 
+  * @{
 
+  */
 
+
 
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
 
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
 
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
 
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
 
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
 
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
 
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
 
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
 
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
 
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
 
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
 
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
 
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
 
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
 
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
 
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
 
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
 
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
 
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
 
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
 
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
 
+                               ((BASE) == TIM_DMABase_CR2) || \
 
+                               ((BASE) == TIM_DMABase_SMCR) || \
 
+                               ((BASE) == TIM_DMABase_DIER) || \
 
+                               ((BASE) == TIM_DMABase_SR) || \
 
+                               ((BASE) == TIM_DMABase_EGR) || \
 
+                               ((BASE) == TIM_DMABase_CCMR1) || \
 
+                               ((BASE) == TIM_DMABase_CCMR2) || \
 
+                               ((BASE) == TIM_DMABase_CCER) || \
 
+                               ((BASE) == TIM_DMABase_CNT) || \
 
+                               ((BASE) == TIM_DMABase_PSC) || \
 
+                               ((BASE) == TIM_DMABase_ARR) || \
 
+                               ((BASE) == TIM_DMABase_RCR) || \
 
+                               ((BASE) == TIM_DMABase_CCR1) || \
 
+                               ((BASE) == TIM_DMABase_CCR2) || \
 
+                               ((BASE) == TIM_DMABase_CCR3) || \
 
+                               ((BASE) == TIM_DMABase_CCR4) || \
 
+                               ((BASE) == TIM_DMABase_BDTR) || \
 
+                               ((BASE) == TIM_DMABase_DCR) || \
 
+                               ((BASE) == TIM_DMABase_OR))                     
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
 
+  */
 
+
 
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
 
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
 
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
 
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
 
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
 
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
 
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
 
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
 
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
 
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
 
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
 
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
 
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
 
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
 
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
 
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
 
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
 
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
 
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
 
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_DMA_sources 
+  * @{
 
+  */
 
+
 
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
 
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
 
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
 
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
 
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
 
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
 
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
 
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
 
+  */
 
+
 
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
 
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
 
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
 
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
 
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
 
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
 
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
 
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
 
+  */
 
+
 
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
 
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
 
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
 
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
 
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
 
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
 
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
 
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
 
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
 
+                                             ((SELECTION) == TIM_TS_ITR1) || \
 
+                                             ((SELECTION) == TIM_TS_ITR2) || \
 
+                                             ((SELECTION) == TIM_TS_ITR3) || \
 
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
 
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
 
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
 
+                                             ((SELECTION) == TIM_TS_ETRF))
 
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
 
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
 
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
 
+                                                      ((SELECTION) == TIM_TS_ITR3))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
 
+  */
 
+
 
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
 
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
 
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
 
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
 
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
 
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
 
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
 
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
 
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
 
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Forced_Action 
+  * @{
 
+  */
 
+
 
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
 
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
 
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
 
+                                      ((ACTION) == TIM_ForcedAction_InActive))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Encoder_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
 
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
 
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
 
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
 
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
 
+                                   ((MODE) == TIM_EncoderMode_TI12))
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/** @defgroup TIM_Event_Source 
+  * @{
 
+  */
 
+
 
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
 
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
 
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
 
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
 
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
 
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
 
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
 
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
 
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))                                          
+  
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Update_Source 
+  * @{
 
+  */
 
+
 
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
 
+                                                                   or the setting of UG bit, or an update generation
 
+                                                                   through the slave mode controller. */
 
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
 
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
 
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
 
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
 
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
 
+                                       ((STATE) == TIM_OCPreload_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
 
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
 
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
 
+                                    ((STATE) == TIM_OCFast_Disable))
 
+                                     
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
 
+  */
 
+
 
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
 
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
 
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
 
+                                     ((STATE) == TIM_OCClear_Disable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
 
+  */
 
+
 
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
 
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
 
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
 
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
 
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
 
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
 
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
 
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
 
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
 
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Slave_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
 
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
 
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
 
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
 
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
 
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
 
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
 
+                                 ((MODE) == TIM_SlaveMode_External1))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
 
+  */
 
+
 
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
 
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
 
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
 
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
 
+/**
 
+  * @}
 
+  */ 
+/** @defgroup TIM_Remap 
+  * @{
 
+  */
 
+
 
+#define TIM2_TIM8_TRGO                     ((uint16_t)0x0000)
 
+#define TIM2_ETH_PTP                       ((uint16_t)0x0400)
 
+#define TIM2_USBFS_SOF                     ((uint16_t)0x0800)
 
+#define TIM2_USBHS_SOF                     ((uint16_t)0x0C00)
 
+
 
+#define TIM5_GPIO                          ((uint16_t)0x0000)
 
+#define TIM5_LSI                           ((uint16_t)0x0040)
 
+#define TIM5_LSE                           ((uint16_t)0x0080)
 
+#define TIM5_RTC                           ((uint16_t)0x00C0)
 
+
 
+#define TIM11_GPIO                         ((uint16_t)0x0000)
 
+#define TIM11_HSE                          ((uint16_t)0x0002)
 
+
 
+#define IS_TIM_REMAP(TIM_REMAP)	 (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
 
+                                  ((TIM_REMAP) == TIM2_ETH_PTP)||\
 
+                                  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
 
+                                  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
 
+                                  ((TIM_REMAP) == TIM5_GPIO)||\
 
+                                  ((TIM_REMAP) == TIM5_LSI)||\
 
+                                  ((TIM_REMAP) == TIM5_LSE)||\
 
+                                  ((TIM_REMAP) == TIM5_RTC)||\
 
+                                  ((TIM_REMAP) == TIM11_GPIO)||\
 
+                                  ((TIM_REMAP) == TIM11_HSE))
 
+
 
+/**
 
+  * @}
 
+  */ 
+/** @defgroup TIM_Flags 
+  * @{
 
+  */
 
+
 
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
 
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
 
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
 
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
 
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
 
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
 
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
 
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
 
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
 
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
 
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
 
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
 
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
 
+                               ((FLAG) == TIM_FLAG_CC1) || \
 
+                               ((FLAG) == TIM_FLAG_CC2) || \
 
+                               ((FLAG) == TIM_FLAG_CC3) || \
 
+                               ((FLAG) == TIM_FLAG_CC4) || \
 
+                               ((FLAG) == TIM_FLAG_COM) || \
 
+                               ((FLAG) == TIM_FLAG_Trigger) || \
 
+                               ((FLAG) == TIM_FLAG_Break) || \
 
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
 
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
 
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
 
+                               ((FLAG) == TIM_FLAG_CC4OF))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
 
+  */
 
+
 
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
 
+  */
 
+
 
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup TIM_Legacy 
+  * @{
 
+  */
 
+
 
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
 
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
 
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
 
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
 
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
 
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
 
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
 
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
 
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
 
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
 
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
 
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
 
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
 
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
 
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
 
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
 
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
 
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/ 
+
 
+/* TimeBase management ********************************************************/
 
+void TIM_DeInit(TIM_TypeDef* TIMx);
 
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
 
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
 
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
 
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
 
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
 
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
 
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
 
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
 
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
 
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
 
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
 
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+
 
+/* Output Compare management **************************************************/
 
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
 
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
 
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
 
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
 
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
 
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
 
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
 
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
 
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
 
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
 
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
 
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
 
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
 
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
 
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
 
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
 
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
 
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
 
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
 
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
 
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
 
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
 
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
 
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
 
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
 
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
 
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
 
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
 
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
 
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
 
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
 
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
 
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
 
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
 
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
 
+
 
+/* Input Capture management ***************************************************/
 
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
 
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
 
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
 
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
 
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
 
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
 
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
 
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
 
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
 
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
 
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
 
+
 
+/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
 
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
 
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
 
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+
 
+/* Interrupts, DMA and flags management ***************************************/
 
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
 
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
 
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
 
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
 
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
 
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
 
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
 
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
 
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+
 
+/* Clocks management **********************************************************/
 
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
 
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
 
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
 
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
 
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
 
+                             uint16_t ExtTRGFilter);
 
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
 
+
 
+/* Synchronization management *************************************************/
 
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
 
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
 
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
 
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
 
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
 
+                   uint16_t ExtTRGFilter);
 
+
 
+/* Specific interface management **********************************************/   
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
 
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
 
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
 
+
 
+/* Specific remapping management **********************************************/
 
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /*__STM32F4xx_TIM_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 429 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_usart.h
Ver arquivo 

@@ -0,0 +1,429 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_usart.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_USART_H
 
+#define __STM32F4xx_USART_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup USART
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/ 
+
 
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
 
+{
 
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
 
+                                           The baud rate is computed using the following formula:
 
+                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
 
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
 
+
 
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
 
+                                           This parameter can be a value of @ref USART_Word_Length */
 
+
 
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
 
+                                           This parameter can be a value of @ref USART_Stop_Bits */
 
+
 
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
 
+                                           This parameter can be a value of @ref USART_Parity
 
+                                           @note When parity is enabled, the computed parity is inserted
 
+                                                 at the MSB position of the transmitted data (9th bit when
 
+                                                 the word length is set to 9 data bits; 8th bit when the
 
+                                                 word length is set to 8 data bits). */
 
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
 
+                                           This parameter can be a value of @ref USART_Mode */
 
+
 
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
 
+                                           or disabled.
 
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
 
+} USART_InitTypeDef;
 
+
 
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
 
+{
 
+
 
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
 
+                               This parameter can be a value of @ref USART_Clock */
 
+
 
+  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
 
+                               This parameter can be a value of @ref USART_Clock_Polarity */
 
+
 
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
 
+                               This parameter can be a value of @ref USART_Clock_Phase */
 
+
 
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
 
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
 
+                               This parameter can be a value of @ref USART_Last_Bit */
 
+} USART_ClockInitTypeDef;
 
+
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup USART_Exported_Constants
 
+  * @{
 
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
 
+                                     ((PERIPH) == USART2) || \
 
+                                     ((PERIPH) == USART3) || \
 
+                                     ((PERIPH) == UART4)  || \
 
+                                     ((PERIPH) == UART5)  || \
 
+                                     ((PERIPH) == USART6))
 
+
 
+#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
 
+                                      ((PERIPH) == USART2) || \
 
+                                      ((PERIPH) == USART3) || \
 
+                                      ((PERIPH) == USART6))
 
+
 
+/** @defgroup USART_Word_Length 
+  * @{
 
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
 
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
 
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
 
+                                      ((LENGTH) == USART_WordLength_9b))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Stop_Bits 
+  * @{
 
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
 
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
 
+#define USART_StopBits_2                     ((uint16_t)0x2000)
 
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
 
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
 
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
 
+                                     ((STOPBITS) == USART_StopBits_2) || \
 
+                                     ((STOPBITS) == USART_StopBits_1_5))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Parity 
+  * @{
 
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
 
+#define USART_Parity_Even                    ((uint16_t)0x0400)
 
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
 
+                                 ((PARITY) == USART_Parity_Even) || \
 
+                                 ((PARITY) == USART_Parity_Odd))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Mode 
+  * @{
 
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
 
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
 
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
 
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
 
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
 
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
 
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
 
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
 
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
 
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
 
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
 
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Clock 
+  * @{
 
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
 
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
 
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
 
+                               ((CLOCK) == USART_Clock_Enable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Clock_Polarity 
+  * @{
 
+  */
 
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
 
+#define USART_CPOL_High                      ((uint16_t)0x0400)
 
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Clock_Phase
 
+  * @{
 
+  */
 
+
 
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
 
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
 
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Last_Bit
 
+  * @{
 
+  */
 
+
 
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
 
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
 
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
 
+                                   ((LASTBIT) == USART_LastBit_Enable))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Interrupt_definition 
+  * @{
 
+  */
 
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
 
+#define USART_IT_TXE                         ((uint16_t)0x0727)
 
+#define USART_IT_TC                          ((uint16_t)0x0626)
 
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
 
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
 
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
 
+#define USART_IT_LBD                         ((uint16_t)0x0846)
 
+#define USART_IT_CTS                         ((uint16_t)0x096A)
 
+#define USART_IT_ERR                         ((uint16_t)0x0060)
 
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
 
+#define USART_IT_NE                          ((uint16_t)0x0260)
 
+#define USART_IT_FE                          ((uint16_t)0x0160)
 
+
 
+/** @defgroup USART_Legacy 
+  * @{
 
+  */
 
+#define USART_IT_ORE                          USART_IT_ORE_ER               
+/**
 
+  * @}
 
+  */
 
+
 
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
 
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
 
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
 
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
 
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
 
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
 
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
 
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
 
+                             ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
 
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
 
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
 
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_DMA_Requests 
+  * @{
 
+  */
 
+
 
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
 
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
 
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_WakeUp_methods
 
+  * @{
 
+  */
 
+
 
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
 
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
 
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
 
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
 
+  */
 
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
 
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
 
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
 
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
 
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
 
+  */
 
+
 
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
 
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
 
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
 
+                                  ((MODE) == USART_IrDAMode_Normal))
 
+/**
 
+  * @}
 
+  */ 
+
 
+/** @defgroup USART_Flags 
+  * @{
 
+  */
 
+
 
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
 
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
 
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
 
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
 
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
 
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
 
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
 
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
 
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
 
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
 
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
 
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
 
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
 
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
 
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
 
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
+
 
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
 
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
 
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/  
+
 
+/*  Function used to set the USART configuration to the default reset state ***/ 
+void USART_DeInit(USART_TypeDef* USARTx);
 
+
 
+/* Initialization and Configuration functions *********************************/
 
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
 
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
 
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
 
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
 
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
 
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+
 
+/* Data transfers functions ***************************************************/ 
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
 
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
 
+
 
+/* Multi-Processor Communication functions ************************************/
 
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
 
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
 
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+
 
+/* LIN mode functions *********************************************************/
 
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
 
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+void USART_SendBreak(USART_TypeDef* USARTx);
 
+
 
+/* Half-duplex mode function **************************************************/
 
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+
 
+/* Smartcard mode functions ***************************************************/
 
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
 
+
 
+/* IrDA mode functions ********************************************************/
 
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
 
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
 
+
 
+/* DMA transfers management functions *****************************************/
 
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
 
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
 
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
 
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
 
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_USART_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 111 - 0
stm32/stm32f4xx_spl/inc/stm32f4xx_wwdg.h
Ver arquivo 

@@ -0,0 +1,111 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_wwdg.h
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
 
+  *          library.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Define to prevent recursive inclusion -------------------------------------*/
 
+#ifndef __STM32F4xx_WWDG_H
 
+#define __STM32F4xx_WWDG_H
 
+
 
+#ifdef __cplusplus
 
+ extern "C" {
 
+#endif
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @addtogroup WWDG
 
+  * @{
 
+  */ 
+
 
+/* Exported types ------------------------------------------------------------*/
 
+/* Exported constants --------------------------------------------------------*/
 
+
 
+/** @defgroup WWDG_Exported_Constants
 
+  * @{
 
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
 
+  */
 
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
 
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
 
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
 
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
 
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
 
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
 
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
 
+                                      ((PRESCALER) == WWDG_Prescaler_8))
 
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
 
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/* Exported macro ------------------------------------------------------------*/
 
+/* Exported functions --------------------------------------------------------*/
 
+  
+/*  Function used to set the WWDG configuration to the default reset state ****/  
+void WWDG_DeInit(void);
 
+
 
+/* Prescaler, Refresh window and Counter configuration functions **************/
 
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
 
+void WWDG_SetWindowValue(uint8_t WindowValue);
 
+void WWDG_EnableIT(void);
 
+void WWDG_SetCounter(uint8_t Counter);
 
+
 
+/* WWDG activation function ***************************************************/
 
+void WWDG_Enable(uint8_t Counter);
 
+
 
+/* Interrupts and flags management functions **********************************/
 
+FlagStatus WWDG_GetFlagStatus(void);
 
+void WWDG_ClearFlag(void);
 
+
 
+#ifdef __cplusplus
 
+}
 
+#endif
 
+
 
+#endif /* __STM32F4xx_WWDG_H */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 249 - 0
stm32/stm32f4xx_spl/src/misc.c
Ver arquivo 

@@ -0,0 +1,249 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    misc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
 
+  *          to CMSIS functions).
 
+  *          
+  *  @verbatim   
+  *                               
+  *          ===================================================================      
+  *                        How to configure Interrupts using driver 
+  *          ===================================================================      
+  * 
+  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
 
+  *            The Cortex-M4 exceptions are managed by CMSIS functions.
 
+  *
 
+  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
 
+  *                function according to the following table.
 
+ 
+  *  The table below gives the allowed values of the pre-emption priority and subpriority according
 
+  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
 
+  *    ==========================================================================================================================
 
+  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
 
+  *    ==========================================================================================================================
 
+  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
 
+  *                           |                                   |                             | 4 bits for subpriority
 
+  *    --------------------------------------------------------------------------------------------------------------------------
 
+  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
 
+  *                           |                                   |                             | 3 bits for subpriority
 
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
 
+  *                           |                                   |                             | 2 bits for subpriority
 
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
 
+  *                           |                                   |                             | 1 bits for subpriority
 
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
 
+  *                           |                                   |                             | 0 bits for subpriority                       
+  *    ==========================================================================================================================     
+  *
 
+  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+  *
 
+  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *        The pending IRQ priority will be managed only by the subpriority.
 
+  *
 
+  * @note  IRQ priority order (sorted by highest to lowest priority):
 
+  *         - Lowest pre-emption priority
 
+  *         - Lowest subpriority
 
+  *         - Lowest hardware priority (IRQ number)
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "misc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup MISC 
+  * @brief MISC driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup MISC_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
 
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
 
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
 
+  *                                4 bits for subpriority
 
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
 
+  *                                3 bits for subpriority
 
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
 
+  *                                2 bits for subpriority
 
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
 
+  *                                1 bits for subpriority
 
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
 
+  *                                0 bits for subpriority
 
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
 
+  */
 
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
 
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
 
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the NVIC peripheral according to the specified
 
+  *         parameters in the NVIC_InitStruct.
 
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
 
+  *         function should be called before. 
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
 
+  *         the configuration information for the specified NVIC peripheral.
 
+  * @retval None
 
+  */
 
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
 
+{
 
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
 
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
 
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
 
+  {
 
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
 
+    tmppre = (0x4 - tmppriority);
 
+    tmpsub = tmpsub >> tmppriority;
 
+
 
+    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
 
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
 
+        
+    tmppriority = tmppriority << 0x04;
 
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
 
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
 
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
 
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Selected IRQ Channels -------------------------------------*/
 
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
 
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets the vector table location and Offset.
 
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
 
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
 
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
 
+  * @retval None
 
+  */
 
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
 
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
 
+}
 
+
 
+/**
 
+  * @brief  Selects the condition for the system to enter low power mode.
 
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
 
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
 
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
 
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_NVIC_LP(LowPowerMode));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
 
+  {
 
+    SCB->SCR |= LowPowerMode;
 
+  }
 
+  else
 
+  {
 
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the SysTick clock source.
 
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
 
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
 
+  * @retval None
 
+  */
 
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
 
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
 
+  {
 
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
 
+  }
 
+  else
 
+  {
 
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1748 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_adc.c
Ver arquivo 

@@ -0,0 +1,1748 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_adc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
 
+  *           - Initialization and Configuration (in addition to ADC multi mode 
+  *             selection)
 
+  *           - Analog Watchdog configuration
 
+  *           - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
 
+  *             management 
+  *           - Regular Channels Configuration
 
+  *           - Regular Channels DMA Configuration
 
+  *           - Injected channels Configuration
 
+  *           - Interrupts and flags management
 
+  *         
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+
 
+  *          1.  Enable the ADC interface clock using 
+  *                  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); 
+  *     
+  *          2. ADC pins configuration
 
+  *               - Enable the clock for the ADC GPIOs using the following function:
 
+  *                   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+  *                - Configure these ADC pins in analog mode using GPIO_Init();  
+  *
 
+  *          3. Configure the ADC Prescaler, conversion resolution and data 
+  *              alignment using the ADC_Init() function.
 
+  *          4. Activate the ADC peripheral using ADC_Cmd() function.
 
+  *
 
+  *          Regular channels group configuration
 
+  *          ====================================    
+  *            - To configure the ADC regular channels group features, use 
+  *              ADC_Init() and ADC_RegularChannelConfig() functions.
 
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
 
+  *              function.
 
+  *            - To configurate and activate the Discontinuous mode, use the 
+  *              ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
 
+  *            - To read the ADC converted values, use the ADC_GetConversionValue()
 
+  *              function.
 
+  *
 
+  *          Multi mode ADCs Regular channels configuration
 
+  *          ===============================================
 
+  *            - Refer to "Regular channels group configuration" description to
 
+  *              configure the ADC1, ADC2 and ADC3 regular channels.        
+  *            - Select the Multi mode ADC regular channels features (dual or 
+  *              triple mode) using ADC_CommonInit() function and configure 
+  *              the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() 
+  *              functions.        
+  *            - Read the ADCs converted values using the 
+  *              ADC_GetMultiModeConversionValue() function.
 
+  *
 
+  *          DMA for Regular channels group features configuration
 
+  *          ====================================================== 
+  *           - To enable the DMA mode for regular channels group, use the 
+  *             ADC_DMACmd() function.
 
+  *           - To enable the generation of DMA requests continuously at the end
 
+  *             of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() 
+  *             function.
 
+  *
 
+  *          Injected channels group configuration
 
+  *          =====================================    
+  *            - To configure the ADC Injected channels group features, use 
+  *              ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
 
+  *              functions.
 
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
 
+  *              function.
 
+  *            - To activate the Injected Discontinuous mode, use the 
+  *              ADC_InjectedDiscModeCmd() function.  
+  *            - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+  *              function.        
+  *            - To read the ADC converted values, use the ADC_GetInjectedConversionValue() 
+  *              function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_adc.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup ADC 
+  * @brief ADC driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/ 
+
 
+/* ADC DISCNUM mask */
 
+#define CR1_DISCNUM_RESET         ((uint32_t)0xFFFF1FFF)
 
+
 
+/* ADC AWDCH mask */
 
+#define CR1_AWDCH_RESET           ((uint32_t)0xFFFFFFE0)   
+
 
+/* ADC Analog watchdog enable mode mask */
 
+#define CR1_AWDMode_RESET         ((uint32_t)0xFF3FFDFF)   
+
 
+/* CR1 register Mask */
 
+#define CR1_CLEAR_MASK            ((uint32_t)0xFCFFFEFF)
 
+
 
+/* ADC EXTEN mask */
 
+#define CR2_EXTEN_RESET           ((uint32_t)0xCFFFFFFF)  
+
 
+/* ADC JEXTEN mask */
 
+#define CR2_JEXTEN_RESET          ((uint32_t)0xFFCFFFFF)  
+
 
+/* ADC JEXTSEL mask */
 
+#define CR2_JEXTSEL_RESET         ((uint32_t)0xFFF0FFFF)  
+
 
+/* CR2 register Mask */
 
+#define CR2_CLEAR_MASK            ((uint32_t)0xC0FFF7FD)
 
+
 
+/* ADC SQx mask */
 
+#define SQR3_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR2_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR1_SQ_SET               ((uint32_t)0x0000001F)  
+
 
+/* ADC L Mask */
 
+#define SQR1_L_RESET              ((uint32_t)0xFF0FFFFF) 
+
 
+/* ADC JSQx mask */
 
+#define JSQR_JSQ_SET              ((uint32_t)0x0000001F) 
+
 
+/* ADC JL mask */
 
+#define JSQR_JL_SET               ((uint32_t)0x00300000) 
+#define JSQR_JL_RESET             ((uint32_t)0xFFCFFFFF) 
+
 
+/* ADC SMPx mask */
 
+#define SMPR1_SMP_SET             ((uint32_t)0x00000007)  
+#define SMPR2_SMP_SET             ((uint32_t)0x00000007) 
+
 
+/* ADC JDRx registers offset */
 
+#define JDR_OFFSET                ((uint8_t)0x28) 
+
 
+/* ADC CDR register base address */
 
+#define CDR_ADDRESS               ((uint32_t)0x40012308)   
+
 
+/* ADC CCR register Mask */
 
+#define CR_CLEAR_MASK             ((uint32_t)0xFFFC30E0)  
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup ADC_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup ADC_Group1 Initialization and Configuration functions
 
+ *  @brief    Initialization and Configuration functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Initialization and Configuration functions
 
+ ===============================================================================  
+  This section provides functions allowing to:
 
+   - Initialize and configure the ADC Prescaler
 
+   - ADC Conversion Resolution (12bit..6bit)
 
+   - Scan Conversion Mode (multichannels or one channel) for regular group
 
+   - ADC Continuous Conversion Mode (Continuous or Single conversion) for 
+     regular group
 
+   - External trigger Edge and source of regular group, 
+   - Converted data alignment (left or right)
 
+   - The number of ADC conversions that will be done using the sequencer for 
+     regular channel group
 
+   - Multi ADC mode selection
 
+   - Direct memory access mode selection for multi ADC mode  
+   - Delay between 2 sampling phases (used in dual or triple interleaved modes)
 
+   - Enable or disable the ADC peripheral
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes all ADCs peripherals registers to their default reset 
+  *         values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void ADC_DeInit(void)
 
+{
 
+  /* Enable all ADCs reset state */
 
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
 
+  
+  /* Release all ADCs from reset state */
 
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct.
 
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
 
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).  
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
 
+  *         the configuration information for the specified ADC peripheral.
 
+  * @retval None
 
+  */
 
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
 
+{
 
+  uint32_t tmpreg1 = 0;
 
+  uint8_t tmpreg2 = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); 
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
 
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); 
+  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); 
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));    
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
 
+  
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
 
+  /* Get the ADCx CR1 value */
 
+  tmpreg1 = ADCx->CR1;
 
+  
+  /* Clear RES and SCAN bits */
 
+  tmpreg1 &= CR1_CLEAR_MASK;
 
+  
+  /* Configure ADCx: scan conversion mode and resolution */
 
+  /* Set SCAN bit according to ADC_ScanConvMode value */
 
+  /* Set RES bit according to ADC_Resolution value */ 
+  tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
 
+                                   ADC_InitStruct->ADC_Resolution);
 
+  /* Write to ADCx CR1 */
 
+  ADCx->CR1 = tmpreg1;
 
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
 
+  /* Get the ADCx CR2 value */
 
+  tmpreg1 = ADCx->CR2;
 
+  
+  /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
 
+  tmpreg1 &= CR2_CLEAR_MASK;
 
+  
+  /* Configure ADCx: external trigger event and edge, data alignment and 
+     continuous conversion mode */
 
+  /* Set ALIGN bit according to ADC_DataAlign value */
 
+  /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ 
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
 
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
 
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
 
+                        ADC_InitStruct->ADC_ExternalTrigConv | 
+                        ADC_InitStruct->ADC_ExternalTrigConvEdge | \
 
+                        ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
 
+                        
+  /* Write to ADCx CR2 */
 
+  ADCx->CR2 = tmpreg1;
 
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
 
+  /* Get the ADCx SQR1 value */
 
+  tmpreg1 = ADCx->SQR1;
 
+  
+  /* Clear L bits */
 
+  tmpreg1 &= SQR1_L_RESET;
 
+  
+  /* Configure ADCx: regular channel sequence length */
 
+  /* Set L bits according to ADC_NbrOfConversion value */
 
+  tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
 
+  tmpreg1 |= ((uint32_t)tmpreg2 << 20);
 
+  
+  /* Write to ADCx SQR1 */
 
+  ADCx->SQR1 = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each ADC_InitStruct member with its default value.
 
+  * @note   This function is used to initialize the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
 
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).  
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
 
+{
 
+  /* Initialize the ADC_Mode member */
 
+  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
 
+
 
+  /* initialize the ADC_ScanConvMode member */
 
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
 
+
 
+  /* Initialize the ADC_ContinuousConvMode member */
 
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
 
+
 
+  /* Initialize the ADC_ExternalTrigConvEdge member */
 
+  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
 
+
 
+  /* Initialize the ADC_ExternalTrigConv member */
 
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
 
+
 
+  /* Initialize the ADC_DataAlign member */
 
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 
+
 
+  /* Initialize the ADC_NbrOfConversion member */
 
+  ADC_InitStruct->ADC_NbrOfConversion = 1;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the ADCs peripherals according to the specified parameters 
+  *         in the ADC_CommonInitStruct.
 
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure 
+  *         that contains the configuration information for  All ADCs peripherals.
 
+  * @retval None
 
+  */
 
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
 
+{
 
+  uint32_t tmpreg1 = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
 
+  assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
 
+  assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
 
+  assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
 
+  /*---------------------------- ADC CCR Configuration -----------------*/
 
+  /* Get the ADC CCR value */
 
+  tmpreg1 = ADC->CCR;
 
+  
+  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
 
+  tmpreg1 &= CR_CLEAR_MASK;
 
+  
+  /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
 
+     and DMA access mode for multimode */
 
+  /* Set MULTI bits according to ADC_Mode value */
 
+  /* Set ADCPRE bits according to ADC_Prescaler value */
 
+  /* Set DMA bits according to ADC_DMAAccessMode value */
 
+  /* Set DELAY bits according to ADC_TwoSamplingDelay value */    
+  tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | 
+                        ADC_CommonInitStruct->ADC_Prescaler | 
+                        ADC_CommonInitStruct->ADC_DMAAccessMode | 
+                        ADC_CommonInitStruct->ADC_TwoSamplingDelay);
 
+                        
+  /* Write to ADC CCR */
 
+  ADC->CCR = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each ADC_CommonInitStruct member with its default value.
 
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
 
+{
 
+  /* Initialize the ADC_Mode member */
 
+  ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
 
+
 
+  /* initialize the ADC_Prescaler member */
 
+  ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
 
+
 
+  /* Initialize the ADC_DMAAccessMode member */
 
+  ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
 
+
 
+  /* Initialize the ADC_TwoSamplingDelay member */
 
+  ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified ADC peripheral.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the ADCx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the ADON bit to wake up the ADC from power down mode */
 
+    ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC peripheral */
 
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
 
+ *  @brief    Analog Watchdog configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Analog Watchdog configuration functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the Analog Watchdog
 
+  (AWD) feature in the ADC.
 
+  
+  A typical configuration Analog Watchdog is done following these steps :
 
+   1. the ADC guarded channel(s) is (are) selected using the 
+      ADC_AnalogWatchdogSingleChannelConfig() function.
 
+   2. The Analog watchdog lower and higher threshold are configured using the  
+     ADC_AnalogWatchdogThresholdsConfig() function.
 
+   3. The Analog watchdog is enabled and configured to enable the check, on one
 
+      or more channels, using the  ADC_AnalogWatchdogCmd() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Enables or disables the analog watchdog on single/all regular or 
+  *         injected channels
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
 
+  *         This parameter can be one of the following values:
 
+  *            @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
 
+  *            @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
 
+  *            @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
 
+  *            @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
 
+  *            @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
 
+  *            @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
 
+  *            @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
 
+  * @retval None	  
+  */
 
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
 
+  
+  /* Get the old register value */
 
+  tmpreg = ADCx->CR1;
 
+  
+  /* Clear AWDEN, JAWDEN and AWDSGL bits */
 
+  tmpreg &= CR1_AWDMode_RESET;
 
+  
+  /* Set the analog watchdog enable mode */
 
+  tmpreg |= ADC_AnalogWatchdog;
 
+  
+  /* Store the new register value */
 
+  ADCx->CR1 = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the high and low thresholds of the analog watchdog.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
 
+  *          This parameter must be a 12-bit value.
 
+  * @param  LowThreshold:  the ADC analog watchdog Low threshold value.
 
+  *          This parameter must be a 12-bit value.
 
+  * @retval None
 
+  */
 
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
 
+                                        uint16_t LowThreshold)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
 
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
 
+  
+  /* Set the ADCx high threshold */
 
+  ADCx->HTR = HighThreshold;
 
+  
+  /* Set the ADCx low threshold */
 
+  ADCx->LTR = LowThreshold;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the analog watchdog guarded single channel
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_Channel_0: ADC Channel0 selected
 
+  *            @arg ADC_Channel_1: ADC Channel1 selected
 
+  *            @arg ADC_Channel_2: ADC Channel2 selected
 
+  *            @arg ADC_Channel_3: ADC Channel3 selected
 
+  *            @arg ADC_Channel_4: ADC Channel4 selected
 
+  *            @arg ADC_Channel_5: ADC Channel5 selected
 
+  *            @arg ADC_Channel_6: ADC Channel6 selected
 
+  *            @arg ADC_Channel_7: ADC Channel7 selected
 
+  *            @arg ADC_Channel_8: ADC Channel8 selected
 
+  *            @arg ADC_Channel_9: ADC Channel9 selected
 
+  *            @arg ADC_Channel_10: ADC Channel10 selected
 
+  *            @arg ADC_Channel_11: ADC Channel11 selected
 
+  *            @arg ADC_Channel_12: ADC Channel12 selected
 
+  *            @arg ADC_Channel_13: ADC Channel13 selected
 
+  *            @arg ADC_Channel_14: ADC Channel14 selected
 
+  *            @arg ADC_Channel_15: ADC Channel15 selected
 
+  *            @arg ADC_Channel_16: ADC Channel16 selected
 
+  *            @arg ADC_Channel_17: ADC Channel17 selected
 
+  *            @arg ADC_Channel_18: ADC Channel18 selected
 
+  * @retval None
 
+  */
 
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
 
+  
+  /* Get the old register value */
 
+  tmpreg = ADCx->CR1;
 
+  
+  /* Clear the Analog watchdog channel select bits */
 
+  tmpreg &= CR1_AWDCH_RESET;
 
+  
+  /* Set the Analog watchdog channel */
 
+  tmpreg |= ADC_Channel;
 
+  
+  /* Store the new register value */
 
+  ADCx->CR1 = tmpreg;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) 
+ *            and VBAT (Voltage BATtery) management functions
 
+ *  @brief   Temperature Sensor, Vrefint and VBAT management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+               Temperature Sensor, Vrefint and VBAT management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to enable/ disable the internal 
+  connections between the ADC and the Temperature Sensor, the Vrefint and the
 
+  Vbat sources.
 
+     
+  A typical configuration to get the Temperature sensor and Vrefint channels 
+  voltages is done following these steps :
 
+   1. Enable the internal connection of Temperature sensor and Vrefint sources 
+      with the ADC channels using ADC_TempSensorVrefintCmd() function. 
+   2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using 
+      ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions 
+   3. Get the voltage values, using ADC_GetConversionValue() or  
+      ADC_GetInjectedConversionValue().
 
+
 
+  A typical configuration to get the VBAT channel voltage is done following 
+  these steps :
 
+   1. Enable the internal connection of VBAT source with the ADC channel using 
+      ADC_VBATCmd() function. 
+   2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or  
+      ADC_InjectedChannelConfig() functions 
+   3. Get the voltage value, using ADC_GetConversionValue() or  
+      ADC_GetInjectedConversionValue().
 
+ 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+  
+/**
 
+  * @brief  Enables or disables the temperature sensor and Vrefint channels.
 
+  * @param  NewState: new state of the temperature sensor and Vrefint channels.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)                
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the temperature sensor and Vrefint channel*/
 
+    ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the temperature sensor and Vrefint channel*/
 
+    ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the VBAT (Voltage Battery) channel.
 
+  * @param  NewState: new state of the VBAT channel.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_VBATCmd(FunctionalState NewState)                             
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the VBAT channel*/
 
+    ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the VBAT channel*/
 
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group4 Regular Channels Configuration functions
 
+ *  @brief   Regular Channels Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Regular Channels Configuration functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to manage the ADC's regular channels,
 
+  it is composed of 2 sub sections : 
+  
+  1. Configuration and management functions for regular channels: This subsection 
+     provides functions allowing to configure the ADC regular channels :    
+          - Configure the rank in the regular group sequencer for each channel
 
+          - Configure the sampling time for each channel
 
+          - select the conversion Trigger for regular channels
 
+          - select the desired EOC event behavior configuration
 
+          - Activate the continuous Mode  (*)
 
+          - Activate the Discontinuous Mode 
+     Please Note that the following features for regular channels are configurated
 
+     using the ADC_Init() function : 
+          - scan mode activation 
+          - continuous mode activation (**) 
+          - External trigger source  
+          - External trigger edge 
+          - number of conversion in the regular channels group sequencer.
 
+     
+     @note (*) and (**) are performing the same configuration
 
+     
+  2. Get the conversion data: This subsection provides an important function in 
+     the ADC peripheral since it returns the converted data of the current 
+     regular channel. When the Conversion value is read, the EOC Flag is 
+     automatically cleared.
 
+     
+     @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions 
+           results data (in the selected multi mode) can be returned in the same 
+           time using ADC_GetMultiModeConversionValue() function. 
+       
+  
+@endverbatim
 
+  * @{
 
+  */
 
+/**
 
+  * @brief  Configures for the selected ADC regular channel its corresponding
 
+  *         rank in the sequencer and its sample time.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_Channel_0: ADC Channel0 selected
 
+  *            @arg ADC_Channel_1: ADC Channel1 selected
 
+  *            @arg ADC_Channel_2: ADC Channel2 selected
 
+  *            @arg ADC_Channel_3: ADC Channel3 selected
 
+  *            @arg ADC_Channel_4: ADC Channel4 selected
 
+  *            @arg ADC_Channel_5: ADC Channel5 selected
 
+  *            @arg ADC_Channel_6: ADC Channel6 selected
 
+  *            @arg ADC_Channel_7: ADC Channel7 selected
 
+  *            @arg ADC_Channel_8: ADC Channel8 selected
 
+  *            @arg ADC_Channel_9: ADC Channel9 selected
 
+  *            @arg ADC_Channel_10: ADC Channel10 selected
 
+  *            @arg ADC_Channel_11: ADC Channel11 selected
 
+  *            @arg ADC_Channel_12: ADC Channel12 selected
 
+  *            @arg ADC_Channel_13: ADC Channel13 selected
 
+  *            @arg ADC_Channel_14: ADC Channel14 selected
 
+  *            @arg ADC_Channel_15: ADC Channel15 selected
 
+  *            @arg ADC_Channel_16: ADC Channel16 selected
 
+  *            @arg ADC_Channel_17: ADC Channel17 selected
 
+  *            @arg ADC_Channel_18: ADC Channel18 selected                       
+  * @param  Rank: The rank in the regular group sequencer.
 
+  *          This parameter must be between 1 to 16.
 
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
 
+  *            @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
 
+  *            @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
 
+  *            @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles	
+  *            @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles	
+  *            @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles	
+  *            @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles	
+  *            @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles	
+  * @retval None
 
+  */
 
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 
+{
 
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
 
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
 
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
 
+  
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
 
+  if (ADC_Channel > ADC_Channel_9)
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SMPR1;
 
+    
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
 
+    
+    /* Clear the old sample time */
 
+    tmpreg1 &= ~tmpreg2;
 
+    
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
 
+    
+    /* Set the new sample time */
 
+    tmpreg1 |= tmpreg2;
 
+    
+    /* Store the new register value */
 
+    ADCx->SMPR1 = tmpreg1;
 
+  }
 
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SMPR2;
 
+    
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
 
+    
+    /* Clear the old sample time */
 
+    tmpreg1 &= ~tmpreg2;
 
+    
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
 
+    
+    /* Set the new sample time */
 
+    tmpreg1 |= tmpreg2;
 
+    
+    /* Store the new register value */
 
+    ADCx->SMPR2 = tmpreg1;
 
+  }
 
+  /* For Rank 1 to 6 */
 
+  if (Rank < 7)
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SQR3;
 
+    
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
 
+    
+    /* Clear the old SQx bits for the selected rank */
 
+    tmpreg1 &= ~tmpreg2;
 
+    
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
 
+    
+    /* Set the SQx bits for the selected rank */
 
+    tmpreg1 |= tmpreg2;
 
+    
+    /* Store the new register value */
 
+    ADCx->SQR3 = tmpreg1;
 
+  }
 
+  /* For Rank 7 to 12 */
 
+  else if (Rank < 13)
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SQR2;
 
+    
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
 
+    
+    /* Clear the old SQx bits for the selected rank */
 
+    tmpreg1 &= ~tmpreg2;
 
+    
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
 
+    
+    /* Set the SQx bits for the selected rank */
 
+    tmpreg1 |= tmpreg2;
 
+    
+    /* Store the new register value */
 
+    ADCx->SQR2 = tmpreg1;
 
+  }
 
+  /* For Rank 13 to 16 */
 
+  else
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SQR1;
 
+    
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
 
+    
+    /* Clear the old SQx bits for the selected rank */
 
+    tmpreg1 &= ~tmpreg2;
 
+    
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
 
+    
+    /* Set the SQx bits for the selected rank */
 
+    tmpreg1 |= tmpreg2;
 
+    
+    /* Store the new register value */
 
+    ADCx->SQR1 = tmpreg1;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables the selected ADC software start conversion of the regular channels.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @retval None
 
+  */
 
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  
+  /* Enable the selected ADC conversion for regular group */
 
+  ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the selected ADC Software start regular conversion Status.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @retval The new state of ADC software start conversion (SET or RESET).
 
+  */
 
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  
+  /* Check the status of SWSTART bit */
 
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
 
+  {
 
+    /* SWSTART bit is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* SWSTART bit is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  
+  /* Return the SWSTART bit status */
 
+  return  bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the EOC on each regular channel conversion
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC EOC flag rising
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC EOC rising on each regular channel conversion */
 
+    ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC EOC rising on each regular channel conversion */
 
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the ADC continuous conversion mode 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC continuous conversion mode
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC continuous conversion mode */
 
+    ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC continuous conversion mode */
 
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the discontinuous mode for the selected ADC regular group 
+  *         channel.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  Number: specifies the discontinuous mode regular channel count value.
 
+  *          This number must be between 1 and 8.
 
+  * @retval None
 
+  */
 
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
 
+{
 
+  uint32_t tmpreg1 = 0;
 
+  uint32_t tmpreg2 = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
 
+  
+  /* Get the old register value */
 
+  tmpreg1 = ADCx->CR1;
 
+  
+  /* Clear the old discontinuous mode channel count */
 
+  tmpreg1 &= CR1_DISCNUM_RESET;
 
+  
+  /* Set the discontinuous mode channel count */
 
+  tmpreg2 = Number - 1;
 
+  tmpreg1 |= tmpreg2 << 13;
 
+  
+  /* Store the new register value */
 
+  ADCx->CR1 = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the discontinuous mode on regular group channel 
+  *         for the specified ADC
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC discontinuous mode on 
+  *         regular group channel.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC regular discontinuous mode */
 
+    ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC regular discontinuous mode */
 
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the last ADCx conversion result data for regular channel.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @retval The Data conversion value.
 
+  */
 
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  
+  /* Return the selected ADC conversion value */
 
+  return (uint16_t) ADCx->DR;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
+  *         data in the selected multi mode.
 
+  * @param  None  
+  * @retval The Data conversion value.
 
+  * @note   In dual mode, the value returned by this function is as following
 
+  *           Data[15:0] : these bits contain the regular data of ADC1.
 
+  *           Data[31:16]: these bits contain the regular data of ADC2.
 
+  * @note   In triple mode, the value returned by this function is as following
 
+  *           Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
 
+  *           Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.           
+  */
 
+uint32_t ADC_GetMultiModeConversionValue(void)
 
+{
 
+  /* Return the multi mode conversion value */
 
+  return (*(__IO uint32_t *) CDR_ADDRESS);
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
 
+ *  @brief   Regular Channels DMA Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Regular Channels DMA Configuration functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the DMA for ADC regular 
+  channels.
 
+  Since converted regular channel values are stored into a unique data register, 
+  it is useful to use DMA for conversion of more than one regular channel. This 
+  avoids the loss of the data already stored in the ADC Data register. 
+  
+  When the DMA mode is enabled (using the ADC_DMACmd() function), after each
 
+  conversion of a regular channel, a DMA request is generated.
 
+  
+  Depending on the "DMA disable selection for Independent ADC mode" 
+  configuration (using the ADC_DMARequestAfterLastTransferCmd() function), 
+  at the end of the last DMA transfer, two possibilities are allowed:
 
+  - No new DMA request is issued to the DMA controller (feature DISABLED) 
+  - Requests can continue to be generated (feature ENABLED).
 
+  
+  Depending on the "DMA disable selection for multi ADC mode" configuration 
+  (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), 
+  at the end of the last DMA transfer, two possibilities are allowed:
 
+  - No new DMA request is issued to the DMA controller (feature DISABLED) 
+  - Requests can continue to be generated (feature ENABLED).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+ /**
 
+  * @brief  Enables or disables the specified ADC DMA request.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC DMA transfer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC DMA request */
 
+    ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC DMA request */
 
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode)  
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC DMA request after last transfer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC DMA request after last transfer */
 
+    ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC DMA request after last transfer */
 
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the ADC DMA request after last transfer in multi ADC mode       
+  * @param  NewState: new state of the selected ADC DMA request after last transfer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @note   if Enabled, DMA requests are issued as long as data are converted and 
+  *         DMA mode for multi ADC mode (selected using ADC_CommonInit() function 
+  *         by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is 
+  *          ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.     
+  * @retval None
 
+  */
 
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC DMA request after last transfer */
 
+    ADC->CCR |= (uint32_t)ADC_CCR_DDS;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC DMA request after last transfer */
 
+    ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group6 Injected channels Configuration functions
 
+ *  @brief   Injected channels Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                     Injected channels Configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the ADC Injected channels,
 
+  it is composed of 2 sub sections : 
+    
+  1. Configuration functions for Injected channels: This subsection provides 
+     functions allowing to configure the ADC injected channels :    
+    - Configure the rank in the injected group sequencer for each channel
 
+    - Configure the sampling time for each channel    
+    - Activate the Auto injected Mode  
+    - Activate the Discontinuous Mode 
+    - scan mode activation  
+    - External/software trigger source   
+    - External trigger edge 
+    - injected channels sequencer.
 
+    
+   2. Get the Specified Injected channel conversion data: This subsection 
+      provides an important function in the ADC peripheral since it returns the 
+      converted data of the specific injected channel.
 
+
 
+@endverbatim
 
+  * @{
 
+  */ 
+/**
 
+  * @brief  Configures for the selected ADC injected channel its corresponding
 
+  *         rank in the sequencer and its sample time.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_Channel_0: ADC Channel0 selected
 
+  *            @arg ADC_Channel_1: ADC Channel1 selected
 
+  *            @arg ADC_Channel_2: ADC Channel2 selected
 
+  *            @arg ADC_Channel_3: ADC Channel3 selected
 
+  *            @arg ADC_Channel_4: ADC Channel4 selected
 
+  *            @arg ADC_Channel_5: ADC Channel5 selected
 
+  *            @arg ADC_Channel_6: ADC Channel6 selected
 
+  *            @arg ADC_Channel_7: ADC Channel7 selected
 
+  *            @arg ADC_Channel_8: ADC Channel8 selected
 
+  *            @arg ADC_Channel_9: ADC Channel9 selected
 
+  *            @arg ADC_Channel_10: ADC Channel10 selected
 
+  *            @arg ADC_Channel_11: ADC Channel11 selected
 
+  *            @arg ADC_Channel_12: ADC Channel12 selected
 
+  *            @arg ADC_Channel_13: ADC Channel13 selected
 
+  *            @arg ADC_Channel_14: ADC Channel14 selected
 
+  *            @arg ADC_Channel_15: ADC Channel15 selected
 
+  *            @arg ADC_Channel_16: ADC Channel16 selected
 
+  *            @arg ADC_Channel_17: ADC Channel17 selected
 
+  *            @arg ADC_Channel_18: ADC Channel18 selected                       
+  * @param  Rank: The rank in the injected group sequencer. 
+  *          This parameter must be between 1 to 4.
 
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
 
+  *            @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
 
+  *            @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
 
+  *            @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles	
+  *            @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles	
+  *            @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles	
+  *            @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles	
+  *            @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles	
+  * @retval None
 
+  */
 
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 
+{
 
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
 
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
 
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
 
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
 
+  if (ADC_Channel > ADC_Channel_9)
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SMPR1;
 
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
 
+    /* Clear the old sample time */
 
+    tmpreg1 &= ~tmpreg2;
 
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
 
+    /* Set the new sample time */
 
+    tmpreg1 |= tmpreg2;
 
+    /* Store the new register value */
 
+    ADCx->SMPR1 = tmpreg1;
 
+  }
 
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
 
+  {
 
+    /* Get the old register value */
 
+    tmpreg1 = ADCx->SMPR2;
 
+    /* Calculate the mask to clear */
 
+    tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
 
+    /* Clear the old sample time */
 
+    tmpreg1 &= ~tmpreg2;
 
+    /* Calculate the mask to set */
 
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
 
+    /* Set the new sample time */
 
+    tmpreg1 |= tmpreg2;
 
+    /* Store the new register value */
 
+    ADCx->SMPR2 = tmpreg1;
 
+  }
 
+  /* Rank configuration */
 
+  /* Get the old register value */
 
+  tmpreg1 = ADCx->JSQR;
 
+  /* Get JL value: Number = JL+1 */
 
+  tmpreg3 =  (tmpreg1 & JSQR_JL_SET)>> 20;
 
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
 
+  tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
 
+  /* Clear the old JSQx bits for the selected rank */
 
+  tmpreg1 &= ~tmpreg2;
 
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
 
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
 
+  /* Set the JSQx bits for the selected rank */
 
+  tmpreg1 |= tmpreg2;
 
+  /* Store the new register value */
 
+  ADCx->JSQR = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the sequencer length for injected channels
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  Length: The sequencer length. 
+  *          This parameter must be a number between 1 to 4.
 
+  * @retval None
 
+  */
 
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
 
+{
 
+  uint32_t tmpreg1 = 0;
 
+  uint32_t tmpreg2 = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
 
+  
+  /* Get the old register value */
 
+  tmpreg1 = ADCx->JSQR;
 
+  
+  /* Clear the old injected sequence length JL bits */
 
+  tmpreg1 &= JSQR_JL_RESET;
 
+  
+  /* Set the injected sequence length JL bits */
 
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
 
+  
+  /* Store the new register value */
 
+  ADCx->JSQR = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Set the injected channels conversion value offset
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
 
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
 
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
 
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
 
+  * @param  Offset: the offset value for the selected ADC injected channel
 
+  *          This parameter must be a 12bit value.
 
+  * @retval None
 
+  */
 
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
 
+{
 
+    __IO uint32_t tmp = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
 
+  assert_param(IS_ADC_OFFSET(Offset));
 
+  
+  tmp = (uint32_t)ADCx;
 
+  tmp += ADC_InjectedChannel;
 
+  
+  /* Set the selected injected channel data offset */
 
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
 
+}
 
+
 
+ /**
 
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
 
+  *          This parameter can be one of the following values:                    
+  *            @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected                       
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
 
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected                          
+  * @retval None
 
+  */
 
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
 
+  
+  /* Get the old register value */
 
+  tmpreg = ADCx->CR2;
 
+  
+  /* Clear the old external event selection for injected group */
 
+  tmpreg &= CR2_JEXTSEL_RESET;
 
+  
+  /* Set the external event selection for injected group */
 
+  tmpreg |= ADC_ExternalTrigInjecConv;
 
+  
+  /* Store the new register value */
 
+  ADCx->CR2 = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the ADCx external trigger edge for injected channels conversion.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
 
+  *         to start injected conversion. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for 
+  *                                                     injected conversion
 
+  *            @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
 
+  *            @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
 
+  *            @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising 
+  *                                                               and falling edge
 
+  * @retval None
 
+  */
 
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
 
+  /* Get the old register value */
 
+  tmpreg = ADCx->CR2;
 
+  /* Clear the old external trigger edge for injected group */
 
+  tmpreg &= CR2_JEXTEN_RESET;
 
+  /* Set the new external trigger edge for injected group */
 
+  tmpreg |= ADC_ExternalTrigInjecConvEdge;
 
+  /* Store the new register value */
 
+  ADCx->CR2 = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Enables the selected ADC software start conversion of the injected channels.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @retval None
 
+  */
 
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  /* Enable the selected ADC conversion for injected group */
 
+  ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the selected ADC Software start injected conversion Status.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
 
+  */
 
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  
+  /* Check the status of JSWSTART bit */
 
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
 
+  {
 
+    /* JSWSTART bit is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* JSWSTART bit is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the JSWSTART bit status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the selected ADC automatic injected group 
+  *         conversion after regular one.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC auto injected conversion
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC automatic injected group conversion */
 
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC automatic injected group conversion */
 
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the discontinuous mode for injected group 
+  *         channel for the specified ADC
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  NewState: new state of the selected ADC discontinuous mode on injected
 
+  *         group channel.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC injected discontinuous mode */
 
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC injected discontinuous mode */
 
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the ADC injected channel conversion result
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
 
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
 
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
 
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
 
+  * @retval The Data conversion value.
 
+  */
 
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
 
+
 
+  tmp = (uint32_t)ADCx;
 
+  tmp += ADC_InjectedChannel + JDR_OFFSET;
 
+  
+  /* Returns the selected injected channel conversion data value */
 
+  return (uint16_t) (*(__IO uint32_t*)  tmp); 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup ADC_Group7 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the ADC Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
 
+  
+  Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into 
+  3 groups:
 
+  
+  I. Flags and Interrupts for ADC regular channels
 
+  =================================================
 
+  Flags :
 
+  ---------- 
+     1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
 
+
 
+     2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending 
+              on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:
 
+               ==> a regular CHANNEL conversion 
+               ==> sequence of regular GROUP conversions .
 
+
 
+     3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL 
+              conversion starts.
 
+
 
+  Interrupts :
 
+  ------------
 
+     1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event.  
+     2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of 
+                     conversion event.
 
+  
+  
+  II. Flags and Interrupts for ADC Injected channels
 
+  =================================================
 
+  Flags :
 
+  ---------- 
+     1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at 
+               the end of injected GROUP conversion  
+              
+     2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when 
+               injected GROUP conversion starts.
 
+
 
+  Interrupts :
 
+  ------------
 
+     1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of 
+                      conversion event.     
+
 
+  III. General Flags and Interrupts for the ADC
 
+  ================================================= 
+  Flags :
 
+  ---------- 
+     1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage 
+              crosses the programmed thresholds values.
 
+              
+  Interrupts :
 
+  ------------
 
+     1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. 
+
 
+  
+  The user should identify which mode will be used in his application to manage 
+  the ADC controller events: Polling mode or Interrupt mode.
 
+  
+  In the Polling Mode it is advised to use the following functions:
 
+      - ADC_GetFlagStatus() : to check if flags events occur. 
+      - ADC_ClearFlag()     : to clear the flags events.
 
+      
+  In the Interrupt Mode it is advised to use the following functions:
 
+     - ADC_ITConfig()          : to enable or disable the interrupt source.
 
+     - ADC_GetITStatus()       : to check if Interrupt occurs.
 
+     - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                 (corresponding Flag). 
+@endverbatim
 
+  * @{
 
+  */ 
+/**
 
+  * @brief  Enables or disables the specified ADC interrupts.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
 
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
 
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
 
+  *            @arg ADC_IT_OVR: Overrun interrupt enable                       
+  * @param  NewState: new state of the specified ADC interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)  
+{
 
+  uint32_t itmask = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  assert_param(IS_ADC_IT(ADC_IT)); 
+
 
+  /* Get the ADC IT index */
 
+  itmask = (uint8_t)ADC_IT;
 
+  itmask = (uint32_t)0x01 << itmask;    
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected ADC interrupts */
 
+    ADCx->CR1 |= itmask;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected ADC interrupts */
 
+    ADCx->CR1 &= (~(uint32_t)itmask);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ADC flag is set or not.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
 
+  *            @arg ADC_FLAG_EOC: End of conversion flag
 
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
 
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
 
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
 
+  *            @arg ADC_FLAG_OVR: Overrun flag                                                 
+  * @retval The new state of ADC_FLAG (SET or RESET).
 
+  */
 
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
 
+
 
+  /* Check the status of the specified ADC flag */
 
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
 
+  {
 
+    /* ADC_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* ADC_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the ADC_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the ADCx's pending flags.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
 
+  *            @arg ADC_FLAG_EOC: End of conversion flag
 
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
 
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
 
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
 
+  *            @arg ADC_FLAG_OVR: Overrun flag                          
+  * @retval None
 
+  */
 
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
 
+
 
+  /* Clear the selected ADC flags */
 
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
 
+  * @param  ADCx:   where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
 
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
 
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
 
+  *            @arg ADC_IT_OVR: Overrun interrupt mask                        
+  * @retval The new state of ADC_IT (SET or RESET).
 
+  */
 
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t itmask = 0, enablestatus = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_IT(ADC_IT));
 
+
 
+  /* Get the ADC IT index */
 
+  itmask = ADC_IT >> 8;
 
+
 
+  /* Get the ADC_IT enable bit status */
 
+  enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
 
+
 
+  /* Check the status of the specified ADC interrupt */
 
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
 
+  {
 
+    /* ADC_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* ADC_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the ADC_IT status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the ADCx's interrupt pending bits.
 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
 
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
 
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
 
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
 
+  *            @arg ADC_IT_OVR: Overrun interrupt mask                         
+  * @retval None
 
+  */
 
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
 
+{
 
+  uint8_t itmask = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
 
+  assert_param(IS_ADC_IT(ADC_IT)); 
+  /* Get the ADC IT index */
 
+  itmask = (uint8_t)(ADC_IT >> 8);
 
+  /* Clear the selected ADC interrupt pending bits */
 
+  ADCx->SR = ~(uint32_t)itmask;
 
+}                    
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1704 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_can.c
Ver arquivo 

@@ -0,0 +1,1704 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_can.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Controller area network (CAN) peripheral:           
+  *           - Initialization and Configuration 
+  *           - CAN Frames Transmission 
+  *           - CAN Frames Reception    
+  *           - Operation modes switch  
+  *           - Error management          
+  *           - Interrupts and flags        
+  *         
+  *  @verbatim
 
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+                
+  *          1.  Enable the CAN controller interface clock using 
+  *                  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 
+  *              and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
 
+  *  @note   In case you are using CAN2 only, you have to enable the CAN1 clock.
 
+  *     
+  *          2. CAN pins configuration
 
+  *               - Enable the clock for the CAN GPIOs using the following function:
 
+  *                   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+  *               - Connect the involved CAN pins to AF9 using the following function 
+  *                   GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); 
+  *                - Configure these CAN pins in alternate function mode by calling
 
+  *                  the function  GPIO_Init();
 
+  *    
+  *          3.  Initialise and configure the CAN using CAN_Init() and 
+  *               CAN_FilterInit() functions.   
+  *               
+  *          4.  Transmit the desired CAN frame using CAN_Transmit() function.
 
+  *         
+  *          5.  Check the transmission of a CAN frame using CAN_TransmitStatus()
 
+  *              function.
 
+  *               
+  *          6.  Cancel the transmission of a CAN frame using CAN_CancelTransmit()
 
+  *              function.  
+  *            
+  *          7.  Receive a CAN frame using CAN_Recieve() function.
 
+  *         
+  *          8.  Release the receive FIFOs using CAN_FIFORelease() function.
 
+  *               
+  *          9. Return the number of pending received frames using 
+  *              CAN_MessagePending() function.            
+  *                   
+  *          10. To control CAN events you can use one of the following two methods:
 
+  *               - Check on CAN flags using the CAN_GetFlagStatus() function.  
+  *               - Use CAN interrupts through the function CAN_ITConfig() at 
+  *                 initialization phase and CAN_GetITStatus() function into 
+  *                 interrupt routines to check if the event has occurred or not.
 
+  *             After checking on a flag you should clear it using CAN_ClearFlag()
 
+  *             function. And after checking on an interrupt event you should 
+  *             clear it using CAN_ClearITPendingBit() function.            
+  *               
+  *              
+  *  @endverbatim
 
+  *         
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_can.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CAN 
+  * @brief CAN driver modules
 
+  * @{
 
+  */ 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* CAN Master Control Register bits */
 
+#define MCR_DBF           ((uint32_t)0x00010000) /* software master reset */
 
+
 
+/* CAN Mailbox Transmit Request */
 
+#define TMIDxR_TXRQ       ((uint32_t)0x00000001) /* Transmit mailbox request */
 
+
 
+/* CAN Filter Master Register bits */
 
+#define FMR_FINIT         ((uint32_t)0x00000001) /* Filter init mode */
 
+
 
+/* Time out for INAK bit */
 
+#define INAK_TIMEOUT      ((uint32_t)0x0000FFFF)
 
+/* Time out for SLAK bit */
 
+#define SLAK_TIMEOUT      ((uint32_t)0x0000FFFF)
 
+
 
+/* Flags in TSR register */
 
+#define CAN_FLAGS_TSR     ((uint32_t)0x08000000) 
+/* Flags in RF1R register */
 
+#define CAN_FLAGS_RF1R    ((uint32_t)0x04000000) 
+/* Flags in RF0R register */
 
+#define CAN_FLAGS_RF0R    ((uint32_t)0x02000000) 
+/* Flags in MSR register */
 
+#define CAN_FLAGS_MSR     ((uint32_t)0x01000000) 
+/* Flags in ESR register */
 
+#define CAN_FLAGS_ESR     ((uint32_t)0x00F00000) 
+
 
+/* Mailboxes definition */
 
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
 
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
 
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02) 
+
 
+#define CAN_MODE_MASK     ((uint32_t) 0x00000003)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
 
+
 
+/** @defgroup CAN_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CAN_Group1 Initialization and Configuration functions
 
+ *  @brief    Initialization and Configuration functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Initialization and Configuration functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number 
+     of time quanta to perform resynchronization, the number of time quanta in
 
+     Bit Segment 1 and 2 and many other modes. 
+     Refer to  @ref CAN_InitTypeDef  for more details.
 
+   - Configures the CAN reception filter.                                      
+   - Select the start bank filter for slave CAN.
 
+   - Enables or disables the Debug Freeze mode for CAN
 
+   - Enables or disables the CAN Time Trigger Operation communication mode
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @retval None.
 
+  */
 
+void CAN_DeInit(CAN_TypeDef* CANx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+ 
+  if (CANx == CAN1)
 
+  {
 
+    /* Enable CAN1 reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
 
+    /* Release CAN1 from reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
 
+  }
 
+  else
 
+  {  
+    /* Enable CAN2 reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
 
+    /* Release CAN2 from reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the CAN peripheral according to the specified
 
+  *         parameters in the CAN_InitStruct.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
 
+  *         the configuration information for the CAN peripheral.
 
+  * @retval Constant indicates initialization succeed which will be 
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
 
+  */
 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
 
+{
 
+  uint8_t InitStatus = CAN_InitStatus_Failed;
 
+  uint32_t wait_ack = 0x00000000;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
 
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
 
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
 
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
 
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
 
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
 
+
 
+  /* Exit from sleep mode */
 
+  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
 
+
 
+  /* Request initialisation */
 
+  CANx->MCR |= CAN_MCR_INRQ ;
 
+
 
+  /* Wait the acknowledge */
 
+  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
 
+  {
 
+    wait_ack++;
 
+  }
 
+
 
+  /* Check acknowledge */
 
+  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
 
+  {
 
+    InitStatus = CAN_InitStatus_Failed;
 
+  }
 
+  else 
+  {
 
+    /* Set the time triggered communication mode */
 
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_TTCM;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
 
+    }
 
+
 
+    /* Set the automatic bus-off management */
 
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_ABOM;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
 
+    }
 
+
 
+    /* Set the automatic wake-up mode */
 
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_AWUM;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
 
+    }
 
+
 
+    /* Set the no automatic retransmission */
 
+    if (CAN_InitStruct->CAN_NART == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_NART;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
 
+    }
 
+
 
+    /* Set the receive FIFO locked mode */
 
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_RFLM;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
 
+    }
 
+
 
+    /* Set the transmit FIFO priority */
 
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
 
+    {
 
+      CANx->MCR |= CAN_MCR_TXFP;
 
+    }
 
+    else
 
+    {
 
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
 
+    }
 
+
 
+    /* Set the bit timing register */
 
+    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
 
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
 
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
 
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
 
+               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
 
+
 
+    /* Request leave initialisation */
 
+    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
 
+
 
+   /* Wait the acknowledge */
 
+   wait_ack = 0;
 
+
 
+   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
 
+   {
 
+     wait_ack++;
 
+   }
 
+
 
+    /* ...and check acknowledged */
 
+    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
 
+    {
 
+      InitStatus = CAN_InitStatus_Failed;
 
+    }
 
+    else
 
+    {
 
+      InitStatus = CAN_InitStatus_Success ;
 
+    }
 
+  }
 
+
 
+  /* At this step, return the status of initialization */
 
+  return InitStatus;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the CAN reception filter according to the specified
 
+  *         parameters in the CAN_FilterInitStruct.
 
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
 
+  *         contains the configuration information.
 
+  * @retval None
 
+  */
 
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
 
+{
 
+  uint32_t filter_number_bit_pos = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
 
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
 
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
 
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
 
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
 
+
 
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
 
+
 
+  /* Initialisation mode for the filter */
 
+  CAN1->FMR |= FMR_FINIT;
 
+
 
+  /* Filter Deactivation */
 
+  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
 
+
 
+  /* Filter Scale */
 
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
 
+  {
 
+    /* 16-bit scale for the filter */
 
+    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
 
+
 
+    /* First 16-bit identifier and First 16-bit mask */
 
+    /* Or First 16-bit identifier and Second 16-bit identifier */
 
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
 
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
 
+
 
+    /* Second 16-bit identifier and Second 16-bit mask */
 
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
 
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
 
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
 
+  }
 
+
 
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
 
+  {
 
+    /* 32-bit scale for the filter */
 
+    CAN1->FS1R |= filter_number_bit_pos;
 
+    /* 32-bit identifier or First 32-bit identifier */
 
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
 
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
 
+    /* 32-bit mask or Second 32-bit identifier */
 
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
 
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
 
+  }
 
+
 
+  /* Filter Mode */
 
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
 
+  {
 
+    /*Id/Mask mode for the filter*/
 
+    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
 
+  }
 
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
 
+  {
 
+    /*Identifier list mode for the filter*/
 
+    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
 
+  }
 
+
 
+  /* Filter FIFO assignment */
 
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
 
+  {
 
+    /* FIFO 0 assignation for the filter */
 
+    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
 
+  }
 
+
 
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
 
+  {
 
+    /* FIFO 1 assignation for the filter */
 
+    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
 
+  }
 
+  
+  /* Filter activation */
 
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
 
+  {
 
+    CAN1->FA1R |= filter_number_bit_pos;
 
+  }
 
+
 
+  /* Leave the initialisation mode for the filter */
 
+  CAN1->FMR &= ~FMR_FINIT;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each CAN_InitStruct member with its default value.
 
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
 
+  * @retval None
 
+  */
 
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
 
+{
 
+  /* Reset CAN init structure parameters values */
 
+  
+  /* Initialize the time triggered communication mode */
 
+  CAN_InitStruct->CAN_TTCM = DISABLE;
 
+  
+  /* Initialize the automatic bus-off management */
 
+  CAN_InitStruct->CAN_ABOM = DISABLE;
 
+  
+  /* Initialize the automatic wake-up mode */
 
+  CAN_InitStruct->CAN_AWUM = DISABLE;
 
+  
+  /* Initialize the no automatic retransmission */
 
+  CAN_InitStruct->CAN_NART = DISABLE;
 
+  
+  /* Initialize the receive FIFO locked mode */
 
+  CAN_InitStruct->CAN_RFLM = DISABLE;
 
+  
+  /* Initialize the transmit FIFO priority */
 
+  CAN_InitStruct->CAN_TXFP = DISABLE;
 
+  
+  /* Initialize the CAN_Mode member */
 
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
 
+  
+  /* Initialize the CAN_SJW member */
 
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
 
+  
+  /* Initialize the CAN_BS1 member */
 
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
 
+  
+  /* Initialize the CAN_BS2 member */
 
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
 
+  
+  /* Initialize the CAN_Prescaler member */
 
+  CAN_InitStruct->CAN_Prescaler = 1;
 
+}
 
+
 
+/**
 
+  * @brief  Select the start bank filter for slave CAN.
 
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
 
+  * @retval None
 
+  */
 
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
 
+  
+  /* Enter Initialisation mode for the filter */
 
+  CAN1->FMR |= FMR_FINIT;
 
+  
+  /* Select the start slave bank */
 
+  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
 
+  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
 
+  
+  /* Leave Initialisation mode for the filter */
 
+  CAN1->FMR &= ~FMR_FINIT;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DBG Freeze for CAN.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  NewState: new state of the CAN peripheral. 
+  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
 
+  *          during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *          or DISABLE (CAN is working during debug).
 
+  * @retval None
 
+  */
 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable Debug Freeze  */
 
+    CANx->MCR |= MCR_DBF;
 
+  }
 
+  else
 
+  {
 
+    /* Disable Debug Freeze */
 
+    CANx->MCR &= ~MCR_DBF;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
 
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
+  *         sent over the CAN bus.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
 
+  *         When enabled, Time stamp (TIME[15:0]) value is  sent in the last two
 
+  *         data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] 
+  *         in data byte 7. 
+  * @retval None
 
+  */
 
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the TTCM mode */
 
+    CANx->MCR |= CAN_MCR_TTCM;
 
+
 
+    /* Set TGT bits */
 
+    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
 
+    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
 
+    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the TTCM mode */
 
+    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
 
+
 
+    /* Reset TGT bits */
 
+    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
 
+    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
 
+    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup CAN_Group2 CAN Frames Transmission functions
 
+ *  @brief    CAN Frames Transmission functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      CAN Frames Transmission functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initiate and transmit a CAN frame message (if there is an empty mailbox).
 
+   - Check the transmission status of a CAN Frame
 
+   - Cancel a transmit request
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Initiates and transmits a CAN frame message.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
 
+  * @retval The number of the mailbox that is used for transmission or
 
+  *         CAN_TxStatus_NoMailBox if there is no empty mailbox.
 
+  */
 
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
 
+{
 
+  uint8_t transmit_mailbox = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
 
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
 
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
 
+
 
+  /* Select one empty transmit mailbox */
 
+  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
 
+  {
 
+    transmit_mailbox = 0;
 
+  }
 
+  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
 
+  {
 
+    transmit_mailbox = 1;
 
+  }
 
+  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
 
+  {
 
+    transmit_mailbox = 2;
 
+  }
 
+  else
 
+  {
 
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
 
+  }
 
+
 
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
 
+  {
 
+    /* Set up the Id */
 
+    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
 
+    if (TxMessage->IDE == CAN_Id_Standard)
 
+    {
 
+      assert_param(IS_CAN_STDID(TxMessage->StdId));  
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
 
+                                                  TxMessage->RTR);
 
+    }
 
+    else
 
+    {
 
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
 
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
 
+                                                  TxMessage->IDE | \
 
+                                                  TxMessage->RTR);
 
+    }
 
+    
+    /* Set up the DLC */
 
+    TxMessage->DLC &= (uint8_t)0x0000000F;
 
+    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
 
+    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
 
+
 
+    /* Set up the data field */
 
+    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
 
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
 
+    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
 
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
 
+                                             ((uint32_t)TxMessage->Data[4]));
 
+    /* Request transmission */
 
+    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
 
+  }
 
+  return transmit_mailbox;
 
+}
 
+
 
+/**
 
+  * @brief  Checks the transmission status of a CAN Frame.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  TransmitMailbox: the number of the mailbox that is used for transmission.
 
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, 
+  *         CAN_TxStatus_Failed in an other case.
 
+  */
 
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
 
+{
 
+  uint32_t state = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
 
+ 
+  switch (TransmitMailbox)
 
+  {
 
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
 
+      break;
 
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
 
+      break;
 
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
 
+      break;
 
+    default:
 
+      state = CAN_TxStatus_Failed;
 
+      break;
 
+  }
 
+  switch (state)
 
+  {
 
+      /* transmit pending  */
 
+    case (0x0): state = CAN_TxStatus_Pending;
 
+      break;
 
+      /* transmit failed  */
 
+     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
 
+      break;
 
+     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
 
+      break;
 
+     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
 
+      break;
 
+      /* transmit succeeded  */
 
+    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
 
+      break;
 
+    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
 
+      break;
 
+    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
 
+      break;
 
+    default: state = CAN_TxStatus_Failed;
 
+      break;
 
+  }
 
+  return (uint8_t) state;
 
+}
 
+
 
+/**
 
+  * @brief  Cancels a transmit request.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  Mailbox: Mailbox number.
 
+  * @retval None
 
+  */
 
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
 
+  /* abort transmission */
 
+  switch (Mailbox)
 
+  {
 
+    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
 
+      break;
 
+    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
 
+      break;
 
+    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
 
+      break;
 
+    default:
 
+      break;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup CAN_Group3 CAN Frames Reception functions
 
+ *  @brief    CAN Frames Reception functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      CAN Frames Reception functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   -  Receive a correct CAN frame
 
+   -  Release a specified receive FIFO (2 FIFOs are available)
 
+   -  Return the number of the pending received CAN frames
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Receives a correct CAN frame.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
 
+  * @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
 
+  *         CAN DLC, CAN data and FMI number.
 
+  * @retval None
 
+  */
 
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_FIFO(FIFONumber));
 
+  /* Get the Id */
 
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
 
+  if (RxMessage->IDE == CAN_Id_Standard)
 
+  {
 
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
 
+  }
 
+  else
 
+  {
 
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
 
+  }
 
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
 
+  /* Get the DLC */
 
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
 
+  /* Get the FMI */
 
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
 
+  /* Get the data field */
 
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
 
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
 
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
 
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
 
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
 
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
 
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
 
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
 
+  /* Release the FIFO */
 
+  /* Release FIFO0 */
 
+  if (FIFONumber == CAN_FIFO0)
 
+  {
 
+    CANx->RF0R |= CAN_RF0R_RFOM0;
 
+  }
 
+  /* Release FIFO1 */
 
+  else /* FIFONumber == CAN_FIFO1 */
 
+  {
 
+    CANx->RF1R |= CAN_RF1R_RFOM1;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Releases the specified receive FIFO.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
 
+  * @retval None
 
+  */
 
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_FIFO(FIFONumber));
 
+  /* Release FIFO0 */
 
+  if (FIFONumber == CAN_FIFO0)
 
+  {
 
+    CANx->RF0R |= CAN_RF0R_RFOM0;
 
+  }
 
+  /* Release FIFO1 */
 
+  else /* FIFONumber == CAN_FIFO1 */
 
+  {
 
+    CANx->RF1R |= CAN_RF1R_RFOM1;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the number of pending received messages.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
 
+  * @retval NbMessage : which is the number of pending message.
 
+  */
 
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
 
+{
 
+  uint8_t message_pending=0;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_FIFO(FIFONumber));
 
+  if (FIFONumber == CAN_FIFO0)
 
+  {
 
+    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
 
+  }
 
+  else if (FIFONumber == CAN_FIFO1)
 
+  {
 
+    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
 
+  }
 
+  else
 
+  {
 
+    message_pending = 0;
 
+  }
 
+  return message_pending;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup CAN_Group4 CAN Operation modes functions
 
+ *  @brief    CAN Operation modes functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      CAN Operation modes functions
 
+ ===============================================================================  
+  This section provides functions allowing to select the CAN Operation modes
 
+  - sleep mode
 
+  - normal mode 
+  - initialization mode
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+  
+  
+/**
 
+  * @brief  Selects the CAN Operation mode.
 
+  * @param  CAN_OperatingMode: CAN Operating Mode.
 
+  *         This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
 
+  * @retval status of the requested mode which can be 
+  *         - CAN_ModeStatus_Failed:  CAN failed entering the specific mode 
+  *         - CAN_ModeStatus_Success: CAN Succeed entering the specific mode 
+  */
 
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
 
+{
 
+  uint8_t status = CAN_ModeStatus_Failed;
 
+  
+  /* Timeout for INAK or also for SLAK bits*/
 
+  uint32_t timeout = INAK_TIMEOUT; 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
 
+
 
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
 
+  {
 
+    /* Request initialisation */
 
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
 
+
 
+    /* Wait the acknowledge */
 
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
 
+    {
 
+      timeout--;
 
+    }
 
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
 
+    {
 
+      status = CAN_ModeStatus_Failed;
 
+    }
 
+    else
 
+    {
 
+      status = CAN_ModeStatus_Success;
 
+    }
 
+  }
 
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
 
+  {
 
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
 
+    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
 
+
 
+    /* Wait the acknowledge */
 
+    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
 
+    {
 
+      timeout--;
 
+    }
 
+    if ((CANx->MSR & CAN_MODE_MASK) != 0)
 
+    {
 
+      status = CAN_ModeStatus_Failed;
 
+    }
 
+    else
 
+    {
 
+      status = CAN_ModeStatus_Success;
 
+    }
 
+  }
 
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
 
+  {
 
+    /* Request Sleep mode */
 
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
 
+
 
+    /* Wait the acknowledge */
 
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
 
+    {
 
+      timeout--;
 
+    }
 
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
 
+    {
 
+      status = CAN_ModeStatus_Failed;
 
+    }
 
+    else
 
+    {
 
+      status = CAN_ModeStatus_Success;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    status = CAN_ModeStatus_Failed;
 
+  }
 
+
 
+  return  (uint8_t) status;
 
+}
 
+
 
+/**
 
+  * @brief  Enters the Sleep (low power) mode.
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
 
+  */
 
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
 
+{
 
+  uint8_t sleepstatus = CAN_Sleep_Failed;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+    
+  /* Request Sleep mode */
 
+   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
 
+   
+  /* Sleep mode status */
 
+  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
 
+  {
 
+    /* Sleep mode not entered */
 
+    sleepstatus =  CAN_Sleep_Ok;
 
+  }
 
+  /* return sleep mode status */
 
+   return (uint8_t)sleepstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Wakes up the CAN peripheral from sleep mode .
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
 
+  */
 
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
 
+{
 
+  uint32_t wait_slak = SLAK_TIMEOUT;
 
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+    
+  /* Wake up request */
 
+  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
 
+    
+  /* Sleep mode status */
 
+  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
 
+  {
 
+   wait_slak--;
 
+  }
 
+  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
 
+  {
 
+   /* wake up done : Sleep mode exited */
 
+    wakeupstatus = CAN_WakeUp_Ok;
 
+  }
 
+  /* return wakeup status */
 
+  return (uint8_t)wakeupstatus;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup CAN_Group5 CAN Bus Error management functions
 
+ *  @brief    CAN Bus Error management functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      CAN Bus Error management functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   -  Return the CANx's last error code (LEC)
 
+   -  Return the CANx Receive Error Counter (REC)
 
+   -  Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
 
+   
+   @note If TEC is greater than 255, The CAN is in bus-off state.
 
+   @note if REC or TEC are greater than 96, an Error warning flag occurs.
 
+   @note if REC or TEC are greater than 127, an Error Passive Flag occurs.
 
+                        
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Returns the CANx's last error code (LEC).
 
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
 
+  * @retval Error code: 
+  *          - CAN_ERRORCODE_NoErr: No Error  
+  *          - CAN_ERRORCODE_StuffErr: Stuff Error
 
+  *          - CAN_ERRORCODE_FormErr: Form Error
 
+  *          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
 
+  *          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
 
+  *          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
 
+  *          - CAN_ERRORCODE_CRCErr: CRC Error
 
+  *          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error  
+  */
 
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
 
+{
 
+  uint8_t errorcode=0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  
+  /* Get the error code*/
 
+  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
 
+  
+  /* Return the error code*/
 
+  return errorcode;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the CANx Receive Error Counter (REC).
 
+  * @note   In case of an error during reception, this counter is incremented 
+  *         by 1 or by 8 depending on the error condition as defined by the CAN 
+  *         standard. After every successful reception, the counter is 
+  *         decremented by 1 or reset to 120 if its value was higher than 128. 
+  *         When the counter value exceeds 127, the CAN controller enters the 
+  *         error passive state.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN Receive Error Counter. 
+  */
 
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
 
+{
 
+  uint8_t counter=0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  
+  /* Get the Receive Error Counter*/
 
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
 
+  
+  /* Return the Receive Error Counter*/
 
+  return counter;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
+  */
 
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
 
+{
 
+  uint8_t counter=0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
 
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
 
+  
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
 
+  return counter;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CAN_Group6 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the CAN Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
 
+  
+  The CAN provides 14 Interrupts sources and 15 Flags:
 
+
 
+  ===============  
+      Flags :
 
+  ===============
 
+  The 15 flags can be divided on 4 groups: 
+
 
+   A. Transmit Flags
 
+  -----------------------
 
+        CAN_FLAG_RQCP0, 
+        CAN_FLAG_RQCP1, 
+        CAN_FLAG_RQCP2  : Request completed MailBoxes 0, 1 and 2  Flags
 
+                          Set when when the last request (transmit or abort) has 
+                          been performed. 
+
 
+  B. Receive Flags
 
+  -----------------------
 
+
 
+        CAN_FLAG_FMP0,
 
+        CAN_FLAG_FMP1   : FIFO 0 and 1 Message Pending Flags 
+                          set to signal that messages are pending in the receive 
+                          FIFO.
 
+                          These Flags are cleared only by hardware. 
+
 
+        CAN_FLAG_FF0,
 
+        CAN_FLAG_FF1    : FIFO 0 and 1 Full Flags
 
+                          set when three messages are stored in the selected 
+                          FIFO.                        
+
 
+        CAN_FLAG_FOV0              
+        CAN_FLAG_FOV1   : FIFO 0 and 1 Overrun Flags
 
+                          set when a new message has been received and passed 
+                          the filter while the FIFO was full.         
+
 
+  C. Operating Mode Flags
 
+  ----------------------- 
+        CAN_FLAG_WKU    : Wake up Flag
 
+                          set to signal that a SOF bit has been detected while 
+                          the CAN hardware was in Sleep mode. 
+        
+        CAN_FLAG_SLAK   : Sleep acknowledge Flag
 
+                          Set to signal that the CAN has entered Sleep Mode. 
+    
+  D. Error Flags
 
+  ----------------------- 
+        CAN_FLAG_EWG    : Error Warning Flag
 
+                          Set when the warning limit has been reached (Receive 
+                          Error Counter or Transmit Error Counter greater than 96). 
+                          This Flag is cleared only by hardware.
 
+                            
+        CAN_FLAG_EPV    : Error Passive Flag
 
+                          Set when the Error Passive limit has been reached 
+                          (Receive Error Counter or Transmit Error Counter 
+                          greater than 127).
 
+                          This Flag is cleared only by hardware.
 
+                             
+        CAN_FLAG_BOF    : Bus-Off Flag
 
+                          set when CAN enters the bus-off state. The bus-off 
+                          state is entered on TEC overflow, greater than 255.
 
+                          This Flag is cleared only by hardware.
 
+                                   
+        CAN_FLAG_LEC    : Last error code Flag
 
+                          set If a message has been transferred (reception or
 
+                          transmission) with error, and the error code is hold.              
+                          
+  ===============  
+   Interrupts :
 
+  ===============
 
+  The 14 interrupts can be divided on 4 groups: 
+  
+   A. Transmit interrupt
 
+  -----------------------   
+          CAN_IT_TME   :  Transmit mailbox empty Interrupt
 
+                          if enabled, this interrupt source is pending when 
+                          no transmit request are pending for Tx mailboxes.      
+
 
+   B. Receive Interrupts
 
+  -----------------------          
+        CAN_IT_FMP0,
 
+        CAN_IT_FMP1    :  FIFO 0 and FIFO1 message pending Interrupts
 
+                          if enabled, these interrupt sources are pending when 
+                          messages are pending in the receive FIFO.
 
+                          The corresponding interrupt pending bits are cleared 
+                          only by hardware.
 
+                
+        CAN_IT_FF0,              
+        CAN_IT_FF1     :  FIFO 0 and FIFO1 full Interrupts
 
+                          if enabled, these interrupt sources are pending when
 
+                          three messages are stored in the selected FIFO.
 
+        
+        CAN_IT_FOV0,        
+        CAN_IT_FOV1    :  FIFO 0 and FIFO1 overrun Interrupts        
+                          if enabled, these interrupt sources are pending when
 
+                          a new message has been received and passed the filter
 
+                          while the FIFO was full.
 
+
 
+   C. Operating Mode Interrupts
 
+  -------------------------------          
+        CAN_IT_WKU     :  Wake-up Interrupt
 
+                          if enabled, this interrupt source is pending when 
+                          a SOF bit has been detected while the CAN hardware was 
+                          in Sleep mode.
 
+                                  
+        CAN_IT_SLK     :  Sleep acknowledge Interrupt
 
+                          if enabled, this interrupt source is pending when 
+                          the CAN has entered Sleep Mode.       
+
 
+   D. Error Interrupts 
+  -----------------------         
+        CAN_IT_EWG     :  Error warning Interrupt 
+                          if enabled, this interrupt source is pending when
 
+                          the warning limit has been reached (Receive Error 
+                          Counter or Transmit Error Counter=96). 
+                               
+        CAN_IT_EPV     :  Error passive Interrupt        
+                          if enabled, this interrupt source is pending when
 
+                          the Error Passive limit has been reached (Receive 
+                          Error Counter or Transmit Error Counter>127).
 
+                          
+        CAN_IT_BOF     :  Bus-off Interrupt
 
+                          if enabled, this interrupt source is pending when
 
+                          CAN enters the bus-off state. The bus-off state is 
+                          entered on TEC overflow, greater than 255.
 
+                          This Flag is cleared only by hardware.
 
+                                  
+        CAN_IT_LEC     :  Last error code Interrupt        
+                          if enabled, this interrupt source is pending  when
 
+                          a message has been transferred (reception or
 
+                          transmission) with error, and the error code is hold.
 
+                          
+        CAN_IT_ERR     :  Error Interrupt
 
+                          if enabled, this interrupt source is pending when 
+                          an error condition is pending.      
+                      
+
 
+  Managing the CAN controller events :
 
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the CAN controller events: Polling mode or Interrupt mode.
 
+  
+  1.  In the Polling Mode it is advised to use the following functions:
 
+      - CAN_GetFlagStatus() : to check if flags events occur. 
+      - CAN_ClearFlag()     : to clear the flags events.
 
+  
+
 
+  
+  2.  In the Interrupt Mode it is advised to use the following functions:
 
+      - CAN_ITConfig()       : to enable or disable the interrupt source.
 
+      - CAN_GetITStatus()    : to check if Interrupt occurs.
 
+      - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag).
 
+      @note  This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts 
+             pending bits since there are cleared only by hardware. 
+  
+@endverbatim
 
+  * @{
 
+  */ 
+/**
 
+  * @brief  Enables or disables the specified CANx interrupts.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
 
+  *          This parameter can be: 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
 
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
 
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
 
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
 
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
 
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
 
+  *            @arg CAN_IT_EPV: Error passive Interrupt
 
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
 
+  *            @arg CAN_IT_ERR: Error Interrupt
 
+  * @param  NewState: new state of the CAN interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_IT(CAN_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected CANx interrupt */
 
+    CANx->IER |= CAN_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected CANx interrupt */
 
+    CANx->IER &= ~CAN_IT;
 
+  }
 
+}
 
+/**
 
+  * @brief  Checks whether the specified CAN flag is set or not.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  CAN_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
 
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
 
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
 
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag   
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag   
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
 
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
 
+  *            @arg CAN_FLAG_EPV: Error Passive Flag  
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag      
+  * @retval The new state of CAN_FLAG (SET or RESET).
 
+  */
 
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
 
+  
+
 
+  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
 
+  { 
+    /* Check the status of the specified CAN flag */
 
+    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
 
+    { 
+      /* CAN_FLAG is set */
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    { 
+      /* CAN_FLAG is reset */
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
 
+  { 
+    /* Check the status of the specified CAN flag */
 
+    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
 
+    { 
+      /* CAN_FLAG is set */
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    { 
+      /* CAN_FLAG is reset */
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
 
+  { 
+    /* Check the status of the specified CAN flag */
 
+    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
 
+    { 
+      /* CAN_FLAG is set */
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    { 
+      /* CAN_FLAG is reset */
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
 
+  { 
+    /* Check the status of the specified CAN flag */
 
+    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
 
+    { 
+      /* CAN_FLAG is set */
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    { 
+      /* CAN_FLAG is reset */
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
 
+  { 
+    /* Check the status of the specified CAN flag */
 
+    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
 
+    { 
+      /* CAN_FLAG is set */
 
+      bitstatus = SET;
 
+    }
 
+    else
 
+    { 
+      /* CAN_FLAG is reset */
 
+      bitstatus = RESET;
 
+    }
 
+  }
 
+  /* Return the CAN_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the CAN's pending flags.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  CAN_FLAG: specifies the flag to clear.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
 
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
 
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag 
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag  
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
 
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag        
+  * @retval None
 
+  */
 
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
 
+{
 
+  uint32_t flagtmp=0;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
 
+  
+  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
 
+  {
 
+    /* Clear the selected CAN flags */
 
+    CANx->ESR = (uint32_t)RESET;
 
+  }
 
+  else /* MSR or TSR or RF0R or RF1R */
 
+  {
 
+    flagtmp = CAN_FLAG & 0x000FFFFF;
 
+
 
+    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
 
+    {
 
+      /* Receive Flags */
 
+      CANx->RF0R = (uint32_t)(flagtmp);
 
+    }
 
+    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
 
+    {
 
+      /* Receive Flags */
 
+      CANx->RF1R = (uint32_t)(flagtmp);
 
+    }
 
+    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
 
+    {
 
+      /* Transmit Flags */
 
+      CANx->TSR = (uint32_t)(flagtmp);
 
+    }
 
+    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
 
+    {
 
+      /* Operating mode Flags */
 
+      CANx->MSR = (uint32_t)(flagtmp);
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  CAN_IT: specifies the CAN interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
 
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
 
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
 
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
 
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
 
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
 
+  *            @arg CAN_IT_EPV: Error passive Interrupt
 
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
 
+  *            @arg CAN_IT_ERR: Error Interrupt
 
+  * @retval The current state of CAN_IT (SET or RESET).
 
+  */
 
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
 
+{
 
+  ITStatus itstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_IT(CAN_IT));
 
+  
+  /* check the interrupt enable bit */
 
+ if((CANx->IER & CAN_IT) != RESET)
 
+ {
 
+   /* in case the Interrupt is enabled, .... */
 
+    switch (CAN_IT)
 
+    {
 
+      case CAN_IT_TME:
 
+        /* Check CAN_TSR_RQCPx bits */
 
+        itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
+        break;
 
+      case CAN_IT_FMP0:
 
+        /* Check CAN_RF0R_FMP0 bit */
 
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
+        break;
 
+      case CAN_IT_FF0:
 
+        /* Check CAN_RF0R_FULL0 bit */
 
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
+        break;
 
+      case CAN_IT_FOV0:
 
+        /* Check CAN_RF0R_FOVR0 bit */
 
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
+        break;
 
+      case CAN_IT_FMP1:
 
+        /* Check CAN_RF1R_FMP1 bit */
 
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
+        break;
 
+      case CAN_IT_FF1:
 
+        /* Check CAN_RF1R_FULL1 bit */
 
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
+        break;
 
+      case CAN_IT_FOV1:
 
+        /* Check CAN_RF1R_FOVR1 bit */
 
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
+        break;
 
+      case CAN_IT_WKU:
 
+        /* Check CAN_MSR_WKUI bit */
 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
+        break;
 
+      case CAN_IT_SLK:
 
+        /* Check CAN_MSR_SLAKI bit */
 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
+        break;
 
+      case CAN_IT_EWG:
 
+        /* Check CAN_ESR_EWGF bit */
 
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
+        break;
 
+      case CAN_IT_EPV:
 
+        /* Check CAN_ESR_EPVF bit */
 
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
+        break;
 
+      case CAN_IT_BOF:
 
+        /* Check CAN_ESR_BOFF bit */
 
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
+        break;
 
+      case CAN_IT_LEC:
 
+        /* Check CAN_ESR_LEC bit */
 
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
+        break;
 
+      case CAN_IT_ERR:
 
+        /* Check CAN_MSR_ERRI bit */ 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
+        break;
 
+      default:
 
+        /* in case of error, return RESET */
 
+        itstatus = RESET;
 
+        break;
 
+    }
 
+  }
 
+  else
 
+  {
 
+   /* in case the Interrupt is not enabled, return RESET */
 
+    itstatus  = RESET;
 
+  }
 
+  
+  /* Return the CAN_IT status */
 
+  return  itstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the CANx's interrupt pending bits.
 
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
 
+  * @param  CAN_IT: specifies the interrupt pending bit to clear.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt
 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
 
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
 
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
 
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
 
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
 
+  *            @arg CAN_IT_EPV: Error passive Interrupt
 
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
 
+  *            @arg CAN_IT_ERR: Error Interrupt 
+  * @retval None
 
+  */
 
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
 
+  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
 
+
 
+  switch (CAN_IT)
 
+  {
 
+    case CAN_IT_TME:
 
+      /* Clear CAN_TSR_RQCPx (rc_w1)*/
 
+      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
+      break;
 
+    case CAN_IT_FF0:
 
+      /* Clear CAN_RF0R_FULL0 (rc_w1)*/
 
+      CANx->RF0R = CAN_RF0R_FULL0; 
+      break;
 
+    case CAN_IT_FOV0:
 
+      /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
 
+      CANx->RF0R = CAN_RF0R_FOVR0; 
+      break;
 
+    case CAN_IT_FF1:
 
+      /* Clear CAN_RF1R_FULL1 (rc_w1)*/
 
+      CANx->RF1R = CAN_RF1R_FULL1;  
+      break;
 
+    case CAN_IT_FOV1:
 
+      /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
 
+      CANx->RF1R = CAN_RF1R_FOVR1; 
+      break;
 
+    case CAN_IT_WKU:
 
+      /* Clear CAN_MSR_WKUI (rc_w1)*/
 
+      CANx->MSR = CAN_MSR_WKUI;  
+      break;
 
+    case CAN_IT_SLK:
 
+      /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
+      CANx->MSR = CAN_MSR_SLAKI;   
+      break;
 
+    case CAN_IT_EWG:
 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
 
+      CANx->MSR = CAN_MSR_ERRI;
 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ 
+      break;
 
+    case CAN_IT_EPV:
 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
 
+      break;
 
+    case CAN_IT_BOF:
 
+      /* Clear CAN_MSR_ERRI (rc_w1) */ 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
 
+       break;
 
+    case CAN_IT_LEC:
 
+      /*  Clear LEC bits */
 
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
 
+      CANx->MSR = CAN_MSR_ERRI; 
+      break;
 
+    case CAN_IT_ERR:
 
+      /*Clear LEC bits */
 
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
 
+       break;
 
+    default:
 
+       break;
 
+   }
 
+}
 
+ /**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @brief  Checks whether the CAN interrupt has occurred or not.
 
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
 
+  * @param  It_Bit: specifies the interrupt source bit to check.
 
+  * @retval The new state of the CAN Interrupt (SET or RESET).
 
+  */
 
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
 
+{
 
+  ITStatus pendingbitstatus = RESET;
 
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
 
+  {
 
+    /* CAN_IT is set */
 
+    pendingbitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* CAN_IT is reset */
 
+    pendingbitstatus = RESET;
 
+  }
 
+  return pendingbitstatus;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 133 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_crc.c
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@@ -0,0 +1,133 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_crc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides all the CRC firmware functions.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_crc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRC 
+  * @brief CRC driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup CRC_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Resets the CRC Data register (DR).
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void CRC_ResetDR(void)
 
+{
 
+  /* Reset CRC generator */
 
+  CRC->CR = CRC_CR_RESET;
 
+}
 
+
 
+/**
 
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
 
+  * @param  Data: data word(32-bit) to compute its CRC
 
+  * @retval 32-bit CRC
 
+  */
 
+uint32_t CRC_CalcCRC(uint32_t Data)
 
+{
 
+  CRC->DR = Data;
 
+  
+  return (CRC->DR);
 
+}
 
+
 
+/**
 
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
 
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
 
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
 
+  */
 
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
 
+{
 
+  uint32_t index = 0;
 
+  
+  for(index = 0; index < BufferLength; index++)
 
+  {
 
+    CRC->DR = pBuffer[index];
 
+  }
 
+  return (CRC->DR);
 
+}
 
+
 
+/**
 
+  * @brief  Returns the current CRC value.
 
+  * @param  None
 
+  * @retval 32-bit CRC
 
+  */
 
+uint32_t CRC_GetCRC(void)
 
+{
 
+  return (CRC->DR);
 
+}
 
+
 
+/**
 
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
 
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
 
+  */
 
+void CRC_SetIDRegister(uint8_t IDValue)
 
+{
 
+  CRC->IDR = IDValue;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
 
+  * @param  None
 
+  * @retval 8-bit value of the ID register 
+  */
 
+uint8_t CRC_GetIDRegister(void)
 
+{
 
+  return (CRC->IDR);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 856 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_cryp.c
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+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_cryp.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the  Cryptographic processor (CRYP) peripheral:           
+  *           - Initialization and Configuration functions
 
+  *           - Data treatment functions 
+  *           - Context swapping functions     
+  *           - DMA interface function       
+  *           - Interrupts and flags management       
+  *
 
+  *  @verbatim
 
+  *                               
+  *          ===================================================================      
+  *                                 How to use this driver
 
+  *          =================================================================== 
+  *          1. Enable the CRYP controller clock using 
+  *              RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
 
+  *
 
+  *          2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if 
+  *             needed CRYP_IVInit(). 
+  *
 
+  *          3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
 
+  *
 
+  *          4. Enable the CRYP controller using the CRYP_Cmd() function. 
+  *
 
+  *          5. If using DMA for Data input and output transfer, 
+  *             Activate the needed DMA Requests using CRYP_DMACmd() function 
+  
+  *          6. If DMA is not used for data transfer, use CRYP_DataIn() and 
+  *             CRYP_DataOut() functions to enter data to IN FIFO and get result
 
+  *             from OUT FIFO.
 
+  *
 
+  *          7. To control CRYP events you can use one of the following 
+  *              two methods:
 
+  *               - Check on CRYP flags using the CRYP_GetFlagStatus() function.  
+  *               - Use CRYP interrupts through the function CRYP_ITConfig() at 
+  *                 initialization phase and CRYP_GetITStatus() function into 
+  *                 interrupt routines in processing phase.
 
+  *       
+  *          8. Save and restore Cryptographic processor context using  
+  *             CRYP_SaveContext() and CRYP_RestoreContext() functions.     
+  *
 
+  *
 
+  *          ===================================================================  
+  *                Procedure to perform an encryption or a decryption
 
+  *          ===================================================================  
+  *
 
+  *      Initialization
 
+  *      ===============  
+  *     1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and 
+  *        CRYP_IVInit functions:
 
+  *        - Configure the key size (128-, 192- or 256-bit, in the AES only) 
+  *        - Enter the symmetric key 
+  *        - Configure the data type
 
+  *        - In case of decryption in AES-ECB or AES-CBC, you must prepare 
+  *          the key: configure the key preparation mode. Then Enable the CRYP 
+  *          peripheral using CRYP_Cmd() function: the BUSY flag is set. 
+  *          Wait until BUSY flag is reset : the key is prepared for decryption
 
+  *       - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the 
+  *          AES in ECB/CBC/CTR) 
+  *       - Configure the direction (encryption/decryption).
 
+  *       - Write the initialization vectors (in CBC or CTR modes only)
 
+  *
 
+  *    2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
 
+  *
 
+  *
 
+  *    Basic Processing mode (polling mode) 
+  *    ====================================  
+  *    1. Enable the cryptographic processor using CRYP_Cmd() function.
 
+  *
 
+  *    2. Write the first blocks in the input FIFO (2 to 8 words) using 
+  *       CRYP_DataIn() function.
 
+  *
 
+  *    3. Repeat the following sequence until the complete message has been 
+  *       processed:
 
+  *
 
+  *       a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() 
+  *          function), then read the OUT-FIFO using CRYP_DataOut() function
 
+  *          (1 block or until the FIFO is empty)
 
+  *
 
+  *       b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() 
+  *          function then write the IN FIFO using CRYP_DataIn() function 
+  *          (1 block or until the FIFO is full)
 
+  *
 
+  *    4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and 
+  *        both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is 
+  *        reset). You can disable the peripheral using CRYP_Cmd() function.
 
+  *
 
+  *    Interrupts Processing mode 
+  *    ===========================
 
+  *    In this mode, Processing is done when the data are transferred by the 
+  *    CPU during interrupts.
 
+  *
 
+  *    1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using 
+  *       CRYP_ITConfig() function.
 
+  *
 
+  *    2. Enable the cryptographic processor using CRYP_Cmd() function.
 
+  *
 
+  *    3. In the CRYP_IT_INI interrupt handler : load the input message into the 
+  *       IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a 
+  *       time, or load data until the IN FIFO is full. When the last word of
 
+  *       the message has been entered into the IN FIFO, disable the CRYP_IT_INI 
+  *       interrupt (using CRYP_ITConfig() function).
 
+  *
 
+  *    4. In the CRYP_IT_OUTI interrupt handler : read the output message from 
+  *       the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 
+  *       4 words) at a time or read data until the FIFO is empty.
 
+  *       When the last word has been read, INIM=0, BUSY=0 and both FIFOs are 
+  *       empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). 
+  *       You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() 
+  *       function) and you can disable the peripheral using CRYP_Cmd() function.
 
+  *
 
+  *    DMA Processing mode 
+  *    ====================
 
+  *    In this mode, Processing is done when the DMA is used to transfer the 
+  *    data from/to the memory.
 
+  *
 
+  *    1. Configure the DMA controller to transfer the input data from the 
+  *       memory using DMA_Init() function. 
+  *       The transfer length is the length of the message. 
+  *       As message padding is not managed by the peripheral, the message 
+  *       length must be an entire number of blocks. The data are transferred 
+  *       in burst mode. The burst length is 4 words in the AES and 2 or 4 
+  *       words in the DES/TDES. The DMA should be configured to set an 
+  *       interrupt on transfer completion of the output data to indicate that 
+  *       the processing is finished. 
+  *       Refer to DMA peripheral driver for more details.  
+  *
 
+  *    2. Enable the cryptographic processor using CRYP_Cmd() function. 
+  *       Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT 
+  *       using CRYP_DMACmd() function.
 
+  *
 
+  *    3. All the transfers and processing are managed by the DMA and the 
+  *       cryptographic processor. The DMA transfer complete interrupt indicates 
+  *       that the processing is complete. Both FIFOs are normally empty and 
+  *       CRYP_FLAG_BUSY flag is reset.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_cryp.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define FLAG_MASK     ((uint8_t)0x20)
 
+#define MAX_TIMEOUT   ((uint16_t)0xFFFF)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup CRYP_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup CRYP_Group1 Initialization and Configuration functions
 
+ *  @brief    Initialization and Configuration functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Initialization and Configuration functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the cryptographic Processor using CRYP_Init() function 
+      -  Encrypt or Decrypt 
+      -  mode : TDES-ECB, TDES-CBC, 
+                DES-ECB, DES-CBC, 
+                AES-ECB, AES-CBC, AES-CTR, AES-Key 
+      - DataType :  32-bit data, 16-bit data, bit data or bit-string
 
+      - Key Size (only in AES modes)
 
+   - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function 
+   - Configure the Initialization Vectors(IV) for CBC and CTR modes using 
+     CRYP_IVInit() function.  
+   - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.                         
+   - Enable or disable the CRYP Processor using CRYP_Cmd() function 
+    
+   
+@endverbatim
 
+  * @{
 
+  */
 
+/**
 
+  * @brief  Deinitializes the CRYP peripheral registers to their default reset values
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void CRYP_DeInit(void)
 
+{
 
+  /* Enable CRYP reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
 
+
 
+  /* Release CRYP from reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the CRYP peripheral according to the specified parameters
 
+  *         in the CRYP_InitStruct.
 
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
 
+  *         the configuration information for the CRYP peripheral.
 
+  * @retval None
 
+  */
 
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
 
+  assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
 
+  assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
 
+
 
+  /* Select Algorithm mode*/  
+  CRYP->CR &= ~CRYP_CR_ALGOMODE;
 
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
 
+
 
+  /* Select dataType */ 
+  CRYP->CR &= ~CRYP_CR_DATATYPE;
 
+  CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
 
+
 
+  /* select Key size (used only with AES algorithm) */
 
+  if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) ||
 
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) ||
 
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) ||
 
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key))
 
+  {
 
+    assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
 
+    CRYP->CR &= ~CRYP_CR_KEYSIZE;
 
+    CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be 
+                                                  configured once the key has 
+                                                  been prepared */
 
+  }
 
+
 
+  /* Select data Direction */ 
+  CRYP->CR &= ~CRYP_CR_ALGODIR;
 
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each CRYP_InitStruct member with its default value.
 
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
 
+{
 
+  /* Initialize the CRYP_AlgoDir member */
 
+  CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
 
+
 
+  /* initialize the CRYP_AlgoMode member */
 
+  CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
 
+
 
+  /* initialize the CRYP_DataType member */
 
+  CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
 
+  
+  /* Initialize the CRYP_KeySize member */
 
+  CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the CRYP Keys according to the specified parameters in
 
+  *         the CRYP_KeyInitStruct.
 
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
 
+  *         contains the configuration information for the CRYP Keys.
 
+  * @retval None
 
+  */
 
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
 
+{
 
+  /* Key Initialisation */
 
+  CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
 
+  CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
 
+  CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
 
+  CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
 
+  CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
 
+  CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
 
+  CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
 
+  CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each CRYP_KeyInitStruct member with its default value.
 
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
 
+{
 
+  CRYP_KeyInitStruct->CRYP_Key0Left  = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key0Right = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key1Left  = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key1Right = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key2Left  = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key2Right = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key3Left  = 0;
 
+  CRYP_KeyInitStruct->CRYP_Key3Right = 0;
 
+}
 
+/**
 
+  * @brief  Initializes the CRYP Initialization Vectors(IV) according to the
 
+  *         specified parameters in the CRYP_IVInitStruct.
 
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
 
+  *         the configuration information for the CRYP Initialization Vectors(IV).
 
+  * @retval None
 
+  */
 
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
 
+{
 
+  CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
 
+  CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
 
+  CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
 
+  CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each CRYP_IVInitStruct member with its default value.
 
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization 
+  *         Vectors(IV) structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
 
+{
 
+  CRYP_IVInitStruct->CRYP_IV0Left  = 0;
 
+  CRYP_IVInitStruct->CRYP_IV0Right = 0;
 
+  CRYP_IVInitStruct->CRYP_IV1Left  = 0;
 
+  CRYP_IVInitStruct->CRYP_IV1Right = 0;
 
+}
 
+
 
+/**
 
+  * @brief  Flushes the IN and OUT FIFOs (that is read and write pointers of the 
+  *         FIFOs are reset)
 
+  * @note   The FIFOs must be flushed only when BUSY flag is reset.  
+  * @param  None
 
+  * @retval None
 
+  */
 
+void CRYP_FIFOFlush(void)
 
+{
 
+  /* Reset the read and write pointers of the FIFOs */
 
+  CRYP->CR |= CRYP_CR_FFLUSH;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the CRYP peripheral.
 
+  * @param  NewState: new state of the CRYP peripheral.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void CRYP_Cmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Cryptographic processor */
 
+    CRYP->CR |= CRYP_CR_CRYPEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Cryptographic processor */
 
+    CRYP->CR &= ~CRYP_CR_CRYPEN;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup CRYP_Group2 CRYP Data processing functions
 
+ *  @brief    CRYP Data processing functions
 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      CRYP Data processing functions
 
+ ===============================================================================  
+  This section provides functions allowing the encryption and decryption 
+  operations: 
+  - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
 
+  - Get the data result from the OUT FIFO : using CRYP_DataOut() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Writes data in the Data Input register (DIN).
 
+  * @note   After the DIN register has been read once or several times, 
+  *         the FIFO must be flushed (using CRYP_FIFOFlush() function).  
+  * @param  Data: data to write in Data Input register
 
+  * @retval None
 
+  */
 
+void CRYP_DataIn(uint32_t Data)
 
+{
 
+  CRYP->DR = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the last data entered into the output FIFO.
 
+  * @param  None
 
+  * @retval Last data entered into the output FIFO.
 
+  */
 
+uint32_t CRYP_DataOut(void)
 
+{
 
+  return CRYP->DOUT;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup CRYP_Group3 Context swapping functions
 
+ *  @brief   Context swapping functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                             Context swapping functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to save and store CRYP Context
 
+
 
+  It is possible to interrupt an encryption/ decryption/ key generation process 
+  to perform another processing with a higher priority, and to complete the 
+  interrupted process later on, when the higher-priority task is complete. To do 
+  so, the context of the interrupted task must be saved from the CRYP registers 
+  to memory, and then be restored from memory to the CRYP registers.
 
+   
+  1. To save the current context, use CRYP_SaveContext() function
 
+  2. To restore the saved context, use CRYP_RestoreContext() function 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Saves the CRYP peripheral Context. 
+  * @note   This function stops DMA transfer before to save the context. After 
+  *         restoring the context, you have to enable the DMA again (if the DMA
 
+  *         was previously used).
 
+  * @param  CRYP_ContextSave: pointer to a CRYP_Context structure that contains
 
+  *         the repository for current context.
 
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that 
+  *         contains the configuration information for the CRYP Keys.  
+  * @retval None
 
+  */
 
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
 
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
 
+{
 
+  __IO uint32_t timeout = 0;
 
+  uint32_t ckeckmask = 0, bitstatus;    
+  ErrorStatus status = ERROR;
 
+
 
+  /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
 
+  CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
 
+    
+  /* Wait until both the IN and OUT FIFOs are empty  
+    (IFEM=1 and OFNE=0 in the CRYP_SR register) and the 
+     BUSY bit is cleared. */
 
+
 
+  if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
 
+  { 
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY ;
 
+  }
 
+  else /* AES or DES */
 
+  {
 
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
 
+  }           
+   
+  do 
+  {
 
+    bitstatus = CRYP->SR & ckeckmask;
 
+    timeout++;
 
+  }
 
+  while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
 
+     
+  if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
 
+  {
 
+    status = ERROR;
 
+  }
 
+  else
 
+  {      
+    /* Stop DMA transfers on the OUT FIFO by 
+       - writing the DOEN bit to 0 in the CRYP_DMACR register 
+       - and clear the CRYPEN bit. */
 
+
 
+    CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
 
+    CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
 
+
 
+    /* Save the current configuration (bits [9:2] in the CRYP_CR register) */
 
+    CRYP_ContextSave->CR_bits9to2  = CRYP->CR & (CRYP_CR_KEYSIZE  | 
+                                                 CRYP_CR_DATATYPE | 
+                                                 CRYP_CR_ALGOMODE |
 
+                                                 CRYP_CR_ALGODIR); 
+
 
+    /* and, if not in ECB mode, the initialization vectors. */
 
+    CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
 
+    CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
 
+    CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
 
+    CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
 
+
 
+    /* save The key value */
 
+    CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; 
+    CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; 
+    CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; 
+    CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; 
+    CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; 
+    CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; 
+    CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; 
+    CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; 
+
 
+   /* When needed, save the DMA status (pointers for IN and OUT messages, 
+      number of remaining bytes, etc.) */
 
+     
+    status = SUCCESS;
 
+  }
 
+
 
+   return status;
 
+}
 
+
 
+/**
 
+  * @brief  Restores the CRYP peripheral Context.
 
+  * @note   Since teh DMA transfer is stopped in CRYP_SaveContext() function,
 
+  *         after restoring the context, you have to enable the DMA again (if the
 
+  *         DMA was previously used).  
+  * @param  CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
 
+  *         the repository for saved context.
 
+  * @note   The data that were saved during context saving must be rewrited into
 
+  *         the IN FIFO.
 
+  * @retval None
 
+  */
 
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)  
+{
 
+
 
+  /* Configure the processor with the saved configuration */
 
+  CRYP->CR = CRYP_ContextRestore->CR_bits9to2;
 
+
 
+  /* restore The key value */
 
+  CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; 
+  CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
 
+  CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
 
+  CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
 
+  CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
 
+  CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
 
+  CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
 
+  CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
 
+
 
+  /* and the initialization vectors. */
 
+  CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
 
+  CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
 
+  CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
 
+  CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
 
+
 
+  /* Enable the cryptographic processor */
 
+  CRYP->CR |= CRYP_CR_CRYPEN;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
 
+ *  @brief   CRYP's DMA interface Configuration function 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   CRYP's DMA interface Configuration function
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the DMA interface for 
+  CRYP data input and output transfer.
 
+   
+  When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be 
+  transferred:
 
+  - From memory to the CRYP IN FIFO using the DMA peripheral by enabling 
+    the CRYP_DMAReq_DataIN request.
 
+  - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling 
+    the CRYP_DMAReq_DataOUT request.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the CRYP DMA interface.
 
+  * @param  CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
 
+  *           This parameter can be any combination of the following values:
 
+  *            @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
 
+  *            @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
 
+  * @param  NewState: new state of the selected CRYP DMA transfer request.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected CRYP DMA request */
 
+    CRYP->DMACR |= CRYP_DMAReq;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected CRYP DMA request */
 
+    CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup CRYP_Group5 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the CRYP Interrupts and 
+  to get the status and Interrupts pending bits.
 
+
 
+  The CRYP provides 2 Interrupts sources and 7 Flags:
 
+
 
+  Flags :
 
+  ------- 
+                          
+     1. CRYP_FLAG_IFEM :  Set when Input FIFO is empty.
 
+                          This Flag is cleared only by hardware.
 
+      
+     2. CRYP_FLAG_IFNF :  Set when Input FIFO is not full.
 
+                          This Flag is cleared only by hardware.
 
+
 
+
 
+     3. CRYP_FLAG_INRIS  : Set when Input FIFO Raw interrupt is pending 
+                           it gives the raw interrupt state prior to masking 
+                           of the input FIFO service interrupt.
 
+                           This Flag is cleared only by hardware.
 
+     
+     4. CRYP_FLAG_OFNE   : Set when Output FIFO not empty.
 
+                           This Flag is cleared only by hardware.
 
+        
+     5. CRYP_FLAG_OFFU   : Set when Output FIFO is full.
 
+                           This Flag is cleared only by hardware.
 
+                           
+     6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending 
+                           it gives the raw interrupt state prior to masking 
+                           of the output FIFO service interrupt.
 
+                           This Flag is cleared only by hardware.
 
+                               
+     7. CRYP_FLAG_BUSY   : Set when the CRYP core is currently processing a 
+                           block of data or a key preparation (for AES 
+                           decryption).
 
+                           This Flag is cleared only by hardware.
 
+                           To clear it, the CRYP core must be disabled and the 
+                           last processing has completed. 
+
 
+  Interrupts :
 
+  ------------
 
+
 
+   1. CRYP_IT_INI   : The input FIFO service interrupt is asserted when there 
+                      are less than 4 words in the input FIFO.
 
+                      This interrupt is associated to CRYP_FLAG_INRIS flag.
 
+
 
+                @note This interrupt is cleared by performing write operations 
+                      to the input FIFO until it holds 4 or more words. The 
+                      input FIFO service interrupt INMIS is enabled with the 
+                      CRYP enable bit. Consequently, when CRYP is disabled, the 
+                      INMIS signal is low even if the input FIFO is empty.
 
+
 
+
 
+
 
+   2. CRYP_IT_OUTI  : The output FIFO service interrupt is asserted when there 
+                      is one or more (32-bit word) data items in the output FIFO.
 
+                      This interrupt is associated to CRYP_FLAG_OUTRIS flag.
 
+
 
+                @note This interrupt is cleared by reading data from the output 
+                      FIFO until there is no valid (32-bit) word left (that is, 
+                      the interrupt follows the state of the OFNE (output FIFO 
+                      not empty) flag).
 
+
 
+
 
+  Managing the CRYP controller events :
 
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the CRYP controller events: Polling mode or Interrupt mode.
 
+
 
+  1.  In the Polling Mode it is advised to use the following functions:
 
+      - CRYP_GetFlagStatus() : to check if flags events occur. 
+
 
+  @note  The CRYPT flags do not need to be cleared since they are cleared as 
+         soon as the associated event are reset.   
+
 
+
 
+  2.  In the Interrupt Mode it is advised to use the following functions:
 
+      - CRYP_ITConfig()       : to enable or disable the interrupt source.
 
+      - CRYP_GetITStatus()    : to check if Interrupt occurs.
 
+
 
+  @note  The CRYPT interrupts have no pending bits, the interrupt is cleared as 
+         soon as the associated event is reset. 
+
 
+@endverbatim
 
+  * @{
 
+  */ 
+
 
+/**
 
+  * @brief  Enables or disables the specified CRYP interrupts.
 
+  * @param  CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
 
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
 
+  * @param  NewState: new state of the specified CRYP interrupt.
 
+  *           This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected CRYP interrupt */
 
+    CRYP->IMSCR |= CRYP_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected CRYP interrupt */
 
+    CRYP->IMSCR &= (uint8_t)~CRYP_IT;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified CRYP interrupt has occurred or not.
 
+  * @note   This function checks the status of the masked interrupt (i.e the 
+  *         interrupt should be previously enabled).     
+  * @param  CRYP_IT: specifies the CRYP (masked) interrupt source to check.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
 
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
 
+  * @retval The new state of CRYP_IT (SET or RESET).
 
+  */
 
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_CRYP_GET_IT(CRYP_IT));
 
+
 
+  /* Check the status of the specified CRYP interrupt */
 
+  if ((CRYP->MISR &  CRYP_IT) != (uint8_t)RESET)
 
+  {
 
+    /* CRYP_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* CRYP_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the CRYP_IT status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified CRYP flag is set or not.
 
+  * @param  CRYP_FLAG: specifies the CRYP flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
 
+  *            @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
 
+  *            @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
 
+  *            @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
 
+  *            @arg CRYP_FLAG_BUSY: Busy flag.
 
+  *            @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
 
+  *            @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
 
+  * @retval The new state of CRYP_FLAG (SET or RESET).
 
+  */
 
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  uint32_t tempreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
 
+
 
+  /* check if the FLAG is in RISR register */
 
+  if ((CRYP_FLAG & FLAG_MASK) != 0x00) 
+  {
 
+    tempreg = CRYP->RISR;
 
+  }
 
+  else  /* The FLAG is in SR register */
 
+  {
 
+    tempreg = CRYP->SR;
 
+  }
 
+
 
+
 
+  /* Check the status of the specified CRYP flag */
 
+  if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
 
+  {
 
+    /* CRYP_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* CRYP_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+
 
+  /* Return the CRYP_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 644 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_cryp_aes.c
Ver arquivo 

@@ -0,0 +1,644 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_cryp_aes.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using AES in ECB/CBC/CTR modes.
 
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
 
+  *          peripheral.
 
+  *
 
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable The CRYP controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
 
+  *
 
+  *          2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB()
 
+  *             function.
 
+  *
 
+  *          3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC()
 
+  *             function.
 
+  *
 
+  *          4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR()
 
+  *             function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_cryp.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define AESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup CRYP_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup CRYP_Group6 High Level AES functions
 
+ *  @brief   High Level AES functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          High Level AES functions
 
+ ===============================================================================
 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using AES in ECB Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  Key: Key used for AES algorithm.
 
+  * @param  Keysize: length of the Key, must be a 128, 192 or 256.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
 
+                         uint8_t* Input, uint32_t Ilength, uint8_t* Output)
 
+{
 
+  CRYP_InitTypeDef AES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
 
+
 
+  switch(Keysize)
 
+  {
 
+    case 128:
 
+    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 192:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_192b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 256:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_256b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    default:
 
+    break;
 
+  }
 
+
 
+  /*------------------ AES Decryption ------------------*/
 
+  if(Mode == MODE_DECRYPT) /* AES decryption */
 
+  {
 
+    /* Flush IN/OUT FIFOs */
 
+    CRYP_FIFOFlush();
 
+
 
+    /* Crypto Init for Key preparation for decryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+    AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
 
+    AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
 
+    CRYP_Init(&AES_CRYP_InitStructure);
 
+
 
+    /* Key Initialisation */
 
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
 
+
 
+    /* Enable Crypto processor */
 
+    CRYP_Cmd(ENABLE);
 
+
 
+    /* wait until the Busy flag is RESET */
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+      /* Crypto Init for decryption process */  
+      AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+    }
 
+  }
 
+  /*------------------ AES Encryption ------------------*/
 
+  else /* AES encryption */
 
+  {
 
+
 
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
 
+
 
+    /* Crypto Init for Encryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
 
+  }
 
+
 
+  AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
 
+  AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&AES_CRYP_InitStructure);
 
+
 
+  /* Flush IN/OUT FIFOs */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
 
+  {
 
+
 
+    /* Write the Input block in the IN FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut(); 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status; 
+}
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using AES in CBC Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
 
+  * @param  Key: Key used for AES algorithm.
 
+  * @param  Keysize: length of the Key, must be a 128, 192 or 256.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
 
+                         uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef AES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
 
+  CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t ivaddr     = (uint32_t)InitVectors;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
 
+
 
+  switch(Keysize)
 
+  {
 
+    case 128:
 
+    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 192:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_192b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 256:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_256b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    default:
 
+    break;
 
+  }
 
+
 
+  /* CRYP Initialization Vectors */
 
+  AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
 
+
 
+
 
+  /*------------------ AES Decryption ------------------*/
 
+  if(Mode == MODE_DECRYPT) /* AES decryption */
 
+  {
 
+    /* Flush IN/OUT FIFOs */
 
+    CRYP_FIFOFlush();
 
+
 
+    /* Crypto Init for Key preparation for decryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+    AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
 
+    AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
 
+
 
+    CRYP_Init(&AES_CRYP_InitStructure);
 
+
 
+    /* Key Initialisation */
 
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
 
+
 
+    /* Enable Crypto processor */
 
+    CRYP_Cmd(ENABLE);
 
+
 
+    /* wait until the Busy flag is RESET */
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+      /* Crypto Init for decryption process */  
+      AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+    }
 
+  }
 
+  /*------------------ AES Encryption ------------------*/
 
+  else /* AES encryption */
 
+  {
 
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
 
+
 
+    /* Crypto Init for Encryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
 
+  AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&AES_CRYP_InitStructure);
 
+
 
+  /* CRYP Initialization Vectors */
 
+  CRYP_IVInit(&AES_CRYP_IVInitStructure);
 
+
 
+  /* Flush IN/OUT FIFOs */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
 
+  {
 
+
 
+    /* Write the Input block in the IN FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using AES in CTR Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  InitVectors: Initialisation Vectors used for AES algorithm.
 
+  * @param  Key: Key used for AES algorithm.
 
+  * @param  Keysize: length of the Key, must be a 128, 192 or 256.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, 
+                         uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
 
+                         uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef AES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
 
+  CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t ivaddr     = (uint32_t)InitVectors;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
 
+
 
+  switch(Keysize)
 
+  {
 
+    case 128:
 
+    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 192:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_192b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    case 256:
 
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_256b;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+    keyaddr+=4;
 
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+    break;
 
+    default:
 
+    break;
 
+  }
 
+  /* CRYP Initialization Vectors */
 
+  AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
 
+
 
+  /* Key Initialisation */
 
+  CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
 
+
 
+  /*------------------ AES Decryption ------------------*/
 
+  if(Mode == MODE_DECRYPT) /* AES decryption */
 
+  {
 
+    /* Crypto Init for decryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+  }
 
+  /*------------------ AES Encryption ------------------*/
 
+  else /* AES encryption */
 
+  {
 
+    /* Crypto Init for Encryption process */
 
+    AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CTR;
 
+  AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&AES_CRYP_InitStructure);
 
+
 
+  /* CRYP Initialization Vectors */
 
+  CRYP_IVInit(&AES_CRYP_IVInitStructure);
 
+
 
+  /* Flush IN/OUT FIFOs */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
 
+  {
 
+
 
+    /* Write the Input block in the IN FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status;
 
+}
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
+

+ 297 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_cryp_des.c
Ver arquivo 

@@ -0,0 +1,297 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_cryp_des.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using DES in ECB/CBC modes.
 
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
 
+  *          peripheral.
 
+  *
 
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable The CRYP controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
 
+  *
 
+  *          2. Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB()
 
+  *             function.
 
+  *
 
+  *          3. Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC()
 
+  *             function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_cryp.h"
 
+
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define DESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+
 
+/** @defgroup CRYP_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup CRYP_Group8 High Level DES functions
 
+ *  @brief   High Level DES functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          High Level DES functions
 
+ ===============================================================================
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using DES in ECB Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  Key: Key used for DES algorithm.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, 
+                         uint32_t Ilength, uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef DES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
 
+
 
+  /* Crypto Init for Encryption process */
 
+  if( Mode == MODE_ENCRYPT ) /* DES encryption */
 
+  {
 
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
 
+  {      
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
 
+  }
 
+
 
+  DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
 
+  DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&DES_CRYP_InitStructure);
 
+
 
+  /* Key Initialisation */
 
+  DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+  CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
 
+
 
+  /* Flush IN/OUT FIFO */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
 
+  {
 
+
 
+    /* Write the Input block in the Input FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+
 
+/* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status; 
+}
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using DES in CBC Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  Key: Key used for DES algorithm.
 
+  * @param  InitVectors: Initialisation Vectors used for DES algorithm.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
 
+                         uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef DES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
 
+  CRYP_IVInitTypeDef DES_CRYP_IVInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t ivaddr     = (uint32_t)InitVectors;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
 
+
 
+  /* Crypto Init for Encryption process */
 
+  if(Mode == MODE_ENCRYPT) /* DES encryption */
 
+  {
 
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  else /*if(Mode == MODE_DECRYPT)*/ /* DES decryption */
 
+  {
 
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
 
+  }
 
+
 
+  DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_CBC;
 
+  DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&DES_CRYP_InitStructure);
 
+
 
+  /* Key Initialisation */
 
+  DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+  CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
 
+
 
+  /* Initialization Vectors */
 
+  DES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  DES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
 
+  CRYP_IVInit(&DES_CRYP_IVInitStructure);
 
+
 
+  /* Flush IN/OUT FIFO */
 
+  CRYP_FIFOFlush();
 
+  
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
 
+  {
 
+    /* Write the Input block in the Input FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status; 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 314 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_cryp_tdes.c
Ver arquivo 

@@ -0,0 +1,314 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_cryp_tdes.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using TDES in ECB/CBC modes .
 
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
 
+  *          peripheral.
 
+  *
 
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable The CRYP controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
 
+  *
 
+  *          2. Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB()
 
+  *             function.
 
+  *
 
+  *          3. Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC()
 
+  *             function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_cryp.h"
 
+
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define TDESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+
 
+/** @defgroup CRYP_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup CRYP_Group7 High Level TDES functions
 
+ *  @brief   High Level TDES functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          High Level TDES functions
 
+ ===============================================================================
 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using TDES in ECB Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  Key: Key used for TDES algorithm.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, 
+                          uint32_t Ilength, uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef TDES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
 
+
 
+  /* Crypto Init for Encryption process */
 
+  if(Mode == MODE_ENCRYPT) /* TDES encryption */
 
+  {
 
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
 
+  {
 
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+  }
 
+
 
+  TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
 
+  TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+  CRYP_Init(&TDES_CRYP_InitStructure);
 
+
 
+  /* Key Initialisation */
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+  CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
 
+
 
+  /* Flush IN/OUT FIFO */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
 
+  {
 
+    /* Write the Input block in the Input FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+    {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status; 
+}
 
+
 
+/**
 
+  * @brief  Encrypt and decrypt using TDES in CBC Mode
 
+  * @param  Mode: encryption or decryption Mode.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg MODE_ENCRYPT: Encryption
 
+  *            @arg MODE_DECRYPT: Decryption
 
+  * @param  Key: Key used for TDES algorithm.
 
+  * @param  InitVectors: Initialisation Vectors used for TDES algorithm.
 
+  * @param  Input: pointer to the Input buffer.
 
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
 
+  * @param  Output: pointer to the returned buffer.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: Operation done
 
+  *          - ERROR: Operation failed
 
+  */
 
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
 
+                          uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 
+{
 
+  CRYP_InitTypeDef TDES_CRYP_InitStructure;
 
+  CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
 
+  CRYP_IVInitTypeDef TDES_CRYP_IVInitStructure;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+  uint32_t ivaddr     = (uint32_t)InitVectors;
 
+  uint32_t i = 0;
 
+
 
+  /* Crypto structures initialisation*/
 
+  CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
 
+
 
+  /* Crypto Init for Encryption process */
 
+  if(Mode == MODE_ENCRYPT) /* TDES encryption */
 
+  {
 
+    TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
 
+  }
 
+  else
 
+  {
 
+    TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
 
+  }
 
+  TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_CBC;
 
+  TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
 
+
 
+  CRYP_Init(&TDES_CRYP_InitStructure);
 
+
 
+  /* Key Initialisation */
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
 
+  keyaddr+=4;
 
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
 
+  CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
 
+
 
+  /* Initialization Vectors */
 
+  TDES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
 
+  ivaddr+=4;
 
+  TDES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
 
+  CRYP_IVInit(&TDES_CRYP_IVInitStructure);
 
+
 
+  /* Flush IN/OUT FIFO */
 
+  CRYP_FIFOFlush();
 
+
 
+  /* Enable Crypto processor */
 
+  CRYP_Cmd(ENABLE);
 
+
 
+  for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
 
+  {
 
+    /* Write the Input block in the Input FIFO */
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+    CRYP_DataIn(*(uint32_t*)(inputaddr));
 
+    inputaddr+=4;
 
+
 
+    /* Wait until the complete message has been processed */
 
+    counter = 0;
 
+    do
 
+    {
 
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+   {
 
+       status = ERROR;
 
+    }
 
+    else
 
+    {
 
+
 
+      /* Read the Output block from the Output FIFO */
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+      *(uint32_t*)(outputaddr) = CRYP_DataOut();
 
+      outputaddr+=4;
 
+    }
 
+  }
 
+
 
+  /* Disable Crypto */
 
+  CRYP_Cmd(DISABLE);
 
+
 
+  return status; 
+}
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 707 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_dac.c
Ver arquivo 

@@ -0,0 +1,707 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dac.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+   * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
+  *           - DAC channels configuration: trigger, output buffer, data format
 
+  *           - DMA management      
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim
 
+  *    
+  *          ===================================================================
 
+  *                             DAC Peripheral features
 
+  *          ===================================================================
 
+  *          
+  *          DAC Channels
 
+  *          =============  
+  *          The device integrates two 12-bit Digital Analog Converters that can 
+  *          be used independently or simultaneously (dual mode):
 
+  *            1- DAC channel1 with DAC_OUT1 (PA4) as output
 
+  *            1- DAC channel2 with DAC_OUT2 (PA5) as output
 
+  *
 
+  *          DAC Triggers
 
+  *          =============
 
+  *          Digital to Analog conversion can be non-triggered using DAC_Trigger_None
 
+  *          and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
+  *          using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
 
+  *   
+  *         Digital to Analog conversion can be triggered by:
 
+  *             1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
 
+  *                The used pin (GPIOx_Pin9) must be configured in input mode.
 
+  *
 
+  *             2- Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+  *                (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
 
+  *                The timer TRGO event should be selected using TIM_SelectOutputTrigger()
 
+  *
 
+  *             3- Software using DAC_Trigger_Software
 
+  *
 
+  *          DAC Buffer mode feature
 
+  *          ========================  
+  *          Each DAC channel integrates an output buffer that can be used to 
+  *          reduce the output impedance, and to drive external loads directly
 
+  *          without having to add an external operational amplifier.
 
+  *          To enable, the output buffer use  
+  *              DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
 
+  *          
+  *          Refer to the device datasheet for more details about output 
+  *          impedance value with and without output buffer.
 
+  *          
+  *          DAC wave generation feature
 
+  *          =============================      
+  *          Both DAC channels can be used to generate
 
+  *             1- Noise wave using DAC_WaveGeneration_Noise
 
+  *             2- Triangle wave using DAC_WaveGeneration_Triangle
 
+  *        
+  *          Wave generation can be disabled using DAC_WaveGeneration_None
 
+  *
 
+  *          DAC data format
 
+  *          ================   
+  *          The DAC data format can be:
 
+  *             1- 8-bit right alignment using DAC_Align_8b_R
 
+  *             2- 12-bit left alignment using DAC_Align_12b_L
 
+  *             3- 12-bit right alignment using DAC_Align_12b_R
 
+  *
 
+  *          DAC data value to voltage correspondence  
+  *          ========================================  
+  *          The analog output voltage on each DAC channel pin is determined
 
+  *          by the following equation: 
+  *          DAC_OUTx = VREF+ * DOR / 4095
 
+  *          with  DOR is the Data Output Register
 
+  *                VEF+ is the input voltage reference (refer to the device datasheet)
 
+  *          e.g. To set DAC_OUT1 to 0.7V, use
 
+  *            DAC_SetChannel1Data(DAC_Align_12b_R, 868);
 
+  *          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
 
+  *
 
+  *          DMA requests 
+  *          =============    
+  *          A DMA1 request can be generated when an external trigger (but not
 
+  *          a software trigger) occurs if DMA1 requests are enabled using
 
+  *          DAC_DMACmd()
 
+  *          DMA1 requests are mapped as following:
 
+  *             1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
+  *                               already configured
 
+  *             2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
+  *                               already configured
 
+  *
 
+  *          ===================================================================      
+  *                              How to use this driver 
+  *          ===================================================================          
+  *            - DAC APB clock must be enabled to get write access to DAC
 
+  *              registers using
 
+  *              RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
 
+  *            - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
 
+  *            - Configure the DAC channel using DAC_Init() function
 
+  *            - Enable the DAC channel using DAC_Cmd() function
 
+  * 
+  *  @endverbatim
 
+  *    
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_dac.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DAC 
+  * @brief DAC driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* CR register Mask */
 
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
 
+
 
+/* DAC Dual Channels SWTRIG masks */
 
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
 
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
 
+
 
+/* DHR registers offsets */
 
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
 
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
 
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
 
+
 
+/* DOR register offset */
 
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup DAC_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DAC_Group1 DAC channels configuration
 
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
 
+@verbatim   
+ ===============================================================================
 
+          DAC channels configuration: trigger, output buffer, data format
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void DAC_DeInit(void)
 
+{
 
+  /* Enable DAC reset state */
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
 
+  /* Release DAC from reset state */
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the DAC peripheral according to the specified parameters
 
+  *         in the DAC_InitStruct.
 
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
 
+  *         the configuration information for the  specified DAC channel.
 
+  * @retval None
 
+  */
 
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
 
+{
 
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
 
+
 
+  /* Check the DAC parameters */
 
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
 
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
 
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
 
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
 
+
 
+/*---------------------------- DAC CR Configuration --------------------------*/
 
+  /* Get the DAC CR value */
 
+  tmpreg1 = DAC->CR;
 
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
 
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
 
+  /* Configure for the selected DAC channel: buffer output, trigger, 
+     wave generation, mask/amplitude for wave generation */
 
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
 
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
 
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
 
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
 
+             DAC_InitStruct->DAC_OutputBuffer);
 
+  /* Calculate CR register value depending on DAC_Channel */
 
+  tmpreg1 |= tmpreg2 << DAC_Channel;
 
+  /* Write to DAC CR */
 
+  DAC->CR = tmpreg1;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each DAC_InitStruct member with its default value.
 
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
 
+{
 
+/*--------------- Reset DAC init structure parameters values -----------------*/
 
+  /* Initialize the DAC_Trigger member */
 
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
 
+  /* Initialize the DAC_WaveGeneration member */
 
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
 
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
 
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
 
+  /* Initialize the DAC_OutputBuffer member */
 
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DAC channel.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @note   When the DAC channel is enabled the trigger source can no more be modified.
 
+  * @retval None
 
+  */
 
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DAC channel */
 
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DAC channel */
 
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the selected DAC channel software trigger.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  NewState: new state of the selected DAC channel software trigger.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable software trigger for the selected DAC channel */
 
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
 
+  }
 
+  else
 
+  {
 
+    /* Disable software trigger for the selected DAC channel */
 
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
 
+  * @param  NewState: new state of the DAC channels software triggers.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable software trigger for both DAC channels */
 
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
 
+  }
 
+  else
 
+  {
 
+    /* Disable software trigger for both DAC channels */
 
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the selected DAC channel wave generation.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_Wave: specifies the wave type to enable or disable.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Wave_Noise: noise wave generation
 
+  *            @arg DAC_Wave_Triangle: triangle wave generation
 
+  * @param  NewState: new state of the selected DAC channel wave generation.
 
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
 
+  */
 
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected wave generation for the selected DAC channel */
 
+    DAC->CR |= DAC_Wave << DAC_Channel;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected wave generation for the selected DAC channel */
 
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Set the specified data holding register value for DAC channel1.
 
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
 
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
 
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
 
+  * @param  Data: Data to be loaded in the selected data holding register.
 
+  * @retval None
 
+  */
 
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
 
+{  
+  __IO uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DAC_ALIGN(DAC_Align));
 
+  assert_param(IS_DAC_DATA(Data));
 
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
 
+
 
+  /* Set the DAC channel1 selected data holding register */
 
+  *(__IO uint32_t *) tmp = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Set the specified data holding register value for DAC channel2.
 
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
 
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
 
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
 
+  * @param  Data: Data to be loaded in the selected data holding register.
 
+  * @retval None
 
+  */
 
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_ALIGN(DAC_Align));
 
+  assert_param(IS_DAC_DATA(Data));
 
+  
+  tmp = (uint32_t)DAC_BASE;
 
+  tmp += DHR12R2_OFFSET + DAC_Align;
 
+
 
+  /* Set the DAC channel2 selected data holding register */
 
+  *(__IO uint32_t *)tmp = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Set the specified data holding register value for dual channel DAC.
 
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
 
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
 
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
 
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
 
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
 
+  * @note   In dual mode, a unique register access is required to write in both
 
+  *          DAC channels at the same time.
 
+  * @retval None
 
+  */
 
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
 
+{
 
+  uint32_t data = 0, tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DAC_ALIGN(DAC_Align));
 
+  assert_param(IS_DAC_DATA(Data1));
 
+  assert_param(IS_DAC_DATA(Data2));
 
+  
+  /* Calculate and set dual DAC data holding register value */
 
+  if (DAC_Align == DAC_Align_8b_R)
 
+  {
 
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
 
+  else
 
+  {
 
+    data = ((uint32_t)Data2 << 16) | Data1;
 
+  }
 
+  
+  tmp = (uint32_t)DAC_BASE;
 
+  tmp += DHR12RD_OFFSET + DAC_Align;
 
+
 
+  /* Set the dual DAC selected data holding register */
 
+  *(__IO uint32_t *)tmp = data;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the last data output value of the selected DAC channel.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @retval The selected DAC channel data output value.
 
+  */
 
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  
+  tmp = (uint32_t) DAC_BASE ;
 
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
 
+  
+  /* Returns the DAC channel data output register value */
 
+  return (uint16_t) (*(__IO uint32_t*) tmp);
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_Group2 DMA management functions
 
+ *  @brief   DMA management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          DMA management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DAC channel DMA request.
 
+  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
 
+  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  NewState: new state of the selected DAC channel DMA request.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
 
+  *          already configured.
 
+  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
 
+  *          already configured.    
+  * @retval None
 
+  */
 
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DAC channel DMA request */
 
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DAC channel DMA request */
 
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DAC_Group3 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DAC interrupts.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be the following values:
 
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
 
+  * @param  NewState: new state of the specified DAC interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DAC interrupts */
 
+    DAC->CR |=  (DAC_IT << DAC_Channel);
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DAC interrupts */
 
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified DAC flag is set or not.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be only of the following value:
 
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
 
+  * @retval The new state of DAC_FLAG (SET or RESET).
 
+  */
 
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
 
+
 
+  /* Check the status of the specified DAC flag */
 
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
 
+  {
 
+    /* DAC_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* DAC_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the DAC_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DAC channel's pending flags.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be of the following value:
 
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
 
+  */
 
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
 
+
 
+  /* Clear the selected DAC flags */
 
+  DAC->SR = (DAC_FLAG << DAC_Channel);
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be the following values:
 
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
 
+  * @retval The new state of DAC_IT (SET or RESET).
 
+  */
 
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t enablestatus = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_DAC_IT(DAC_IT));
 
+
 
+  /* Get the DAC_IT enable bit status */
 
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
 
+  
+  /* Check the status of the specified DAC interrupt */
 
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
 
+  {
 
+    /* DAC_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* DAC_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the DAC_IT status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DAC channel's interrupt pending bits.
 
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DAC_Channel_1: DAC Channel1 selected
 
+  *            @arg DAC_Channel_2: DAC Channel2 selected
 
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
 
+  *          This parameter can be the following values:
 
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
 
+  */
 
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
 
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
 
+  /* Clear the selected DAC interrupt pending bits */
 
+  DAC->SR = (DAC_IT << DAC_Channel);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 180 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_dbgmcu.c
Ver arquivo 

@@ -0,0 +1,180 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dbgmcu.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides all the DBGMCU firmware functions.
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_dbgmcu.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup DBGMCU_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/**
 
+  * @brief  Returns the device revision identifier.
 
+  * @param  None
 
+  * @retval Device revision identifier
 
+  */
 
+uint32_t DBGMCU_GetREVID(void)
 
+{
 
+   return(DBGMCU->IDCODE >> 16);
 
+}
 
+
 
+/**
 
+  * @brief  Returns the device identifier.
 
+  * @param  None
 
+  * @retval Device identifier
 
+  */
 
+uint32_t DBGMCU_GetDEVID(void)
 
+{
 
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
 
+}
 
+
 
+/**
 
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
 
+  * @param  DBGMCU_Periph: specifies the low power mode.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode        
+  * @param  NewState: new state of the specified low power mode in Debug mode.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    DBGMCU->CR |= DBGMCU_Periph;
 
+  }
 
+  else
 
+  {
 
+    DBGMCU->CR &= ~DBGMCU_Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
 
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
 
+  *   This parameter can be any combination of the following values:        
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
 
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
 
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 
+  *     @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.                                                                                
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
 
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted        
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
 
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
 
+  *     @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
 
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted           
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted        
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
 
+  }
 
+  else
 
+  {
 
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
 
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
 
+  *   This parameter can be any combination of the following values:       
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted                
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
 
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted                                                                                  
+  * @param  NewState: new state of the specified peripheral in Debug mode.
 
+  *   This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
 
+  }
 
+  else
 
+  {
 
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 540 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_dcmi.c
Ver arquivo 

@@ -0,0 +1,540 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dcmi.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the DCMI peripheral:           
+  *           - Initialization and Configuration
 
+  *           - Image capture functions  
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim  
+  *  
+  *        
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================  
+  *         
+  *         The sequence below describes how to use this driver to capture image
 
+  *         from a camera module connected to the DCMI Interface.
 
+  *         This sequence does not take into account the configuration of the  
+  *         camera module, which should be made before to configure and enable
 
+  *         the DCMI to capture images.
 
+  *           
+  *          1. Enable the clock for the DCMI and associated GPIOs using the following functions:
 
+  *                 RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
 
+  *                 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
 
+  *
 
+  *          2. DCMI pins configuration 
+  *             - Connect the involved DCMI pins to AF13 using the following function 
+  *                 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); 
+  *             - Configure these DCMI pins in alternate function mode by calling the function
 
+  *                 GPIO_Init();
 
+  *    
+  *          3. Declare a DCMI_InitTypeDef structure, for example:
 
+  *                 DCMI_InitTypeDef  DCMI_InitStructure;
 
+  *             and fill the DCMI_InitStructure variable with the allowed values
 
+  *             of the structure member.
 
+  *  
+  *          4. Initialize the DCMI interface by calling the function
 
+  *                 DCMI_Init(&DCMI_InitStructure); 
+  *  
+  *          5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
 
+  *             register to the destination memory buffer.
 
+  *  
+  *          6. Enable DCMI interface using the function
 
+  *                 DCMI_Cmd(ENABLE);
 
+  *                 
+  *         7. Start the image capture using the function
 
+  *                 DCMI_CaptureCmd(ENABLE);
 
+  *                 
+  *         8. At this stage the DCMI interface waits for the first start of frame,
 
+  *            then a DMA request is generated continuously/once (depending on the
 
+  *            mode used, Continuous/Snapshot) to transfer the received data into
 
+  *            the destination memory. 
+  *   
+  *  @note  If you need to capture only a rectangular window from the received
 
+  *         image, you have to use the DCMI_CROPConfig() function to configure 
+  *         the coordinates and size of the window to be captured, then enable 
+  *         the Crop feature using DCMI_CROPCmd(ENABLE);  
+  *         In this case, the Crop configuration should be made before to enable
 
+  *         and start the DCMI interface. 
+  *        
+  *  @endverbatim   
+  *  
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_dcmi.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DCMI 
+  * @brief DCMI driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup DCMI_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup DCMI_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the DCMI registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void DCMI_DeInit(void)
 
+{
 
+  DCMI->CR = 0x0;
 
+  DCMI->IER = 0x0;
 
+  DCMI->ICR = 0x1F;
 
+  DCMI->ESCR = 0x0;
 
+  DCMI->ESUR = 0x0;
 
+  DCMI->CWSTRTR = 0x0;
 
+  DCMI->CWSIZER = 0x0;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
 
+  * @param  DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains 
+  *         the configuration information for the DCMI.
 
+  * @retval None
 
+  */
 
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
 
+{
 
+  uint32_t temp = 0x0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
 
+  assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
 
+  assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
 
+  assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
 
+  assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
 
+  assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
 
+  assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
 
+
 
+  /* The DCMI configuration registers should be programmed correctly before 
+  enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
 
+  DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
 
+   
+  /* Reset the old DCMI configuration */
 
+  temp = DCMI->CR;
 
+  
+  temp &= ~((uint32_t)DCMI_CR_CM     | DCMI_CR_ESS   | DCMI_CR_PCKPOL |
 
+                      DCMI_CR_HSPOL  | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | 
+                      DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); 
+                  
+  /* Sets the new configuration of the DCMI peripheral */
 
+  temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
 
+                     DCMI_InitStruct->DCMI_SynchroMode |
 
+                     DCMI_InitStruct->DCMI_PCKPolarity |
 
+                     DCMI_InitStruct->DCMI_VSPolarity |
 
+                     DCMI_InitStruct->DCMI_HSPolarity |
 
+                     DCMI_InitStruct->DCMI_CaptureRate |
 
+                     DCMI_InitStruct->DCMI_ExtendedDataMode);
 
+
 
+  DCMI->CR = temp;                              
+}
 
+
 
+/**
 
+  * @brief  Fills each DCMI_InitStruct member with its default value.
 
+  * @param  DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
 
+{
 
+  /* Set the default configuration */
 
+  DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
 
+  DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
 
+  DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
 
+  DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
 
+  DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
 
+  DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
 
+  DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the DCMI peripheral CROP mode according to the specified
 
+  *         parameters in the DCMI_CROPInitStruct.
 
+  * @note   This function should be called before to enable and start the DCMI interface.   
+  * @param  DCMI_CROPInitStruct:  pointer to a DCMI_CROPInitTypeDef structure that 
+  *         contains the configuration information for the DCMI peripheral CROP mode.
 
+  * @retval None
 
+  */
 
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
 
+{  
+  /* Sets the CROP window coordinates */
 
+  DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
 
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
 
+
 
+  /* Sets the CROP window size */
 
+  DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
 
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DCMI Crop feature.
 
+  * @note   This function should be called before to enable and start the DCMI interface.
 
+  * @param  NewState: new state of the DCMI Crop feature. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DCMI_CROPCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DCMI Crop feature */
 
+    DCMI->CR |= (uint32_t)DCMI_CR_CROP;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DCMI Crop feature */
 
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets the embedded synchronization codes
 
+  * @param  DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
 
+  *         contains the embedded synchronization codes for the DCMI peripheral.
 
+  * @retval None
 
+  */
 
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
 
+{
 
+  DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
 
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
 
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
 
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DCMI JPEG format.
 
+  * @note   The Crop and Embedded Synchronization features cannot be used in this mode.  
+  * @param  NewState: new state of the DCMI JPEG format. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DCMI_JPEGCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+ 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DCMI JPEG format */
 
+    DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DCMI JPEG format */
 
+    DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DCMI_Group2 Image capture functions
 
+ *  @brief   Image capture functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                                 Image capture functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Enables or disables the DCMI interface.
 
+  * @param  NewState: new state of the DCMI interface. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DCMI_Cmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DCMI by setting ENABLE bit */
 
+    DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DCMI by clearing ENABLE bit */
 
+    DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the DCMI Capture.
 
+  * @param  NewState: new state of the DCMI capture. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DCMI_CaptureCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DCMI Capture */
 
+    DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DCMI Capture */
 
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Reads the data stored in the DR register.
 
+  * @param  None 
+  * @retval Data register value
 
+  */
 
+uint32_t DCMI_ReadData(void)
 
+{
 
+  return DCMI->DR;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DCMI_Group3 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the DCMI interface interrupts.
 
+  * @param  DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
 
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
 
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
 
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
 
+  *            @arg DCMI_IT_LINE: Line interrupt mask
 
+  * @param  NewState: new state of the specified DCMI interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Interrupt sources */
 
+    DCMI->IER |= DCMI_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Interrupt sources */
 
+    DCMI->IER &= (uint16_t)(~DCMI_IT);
 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Checks whether the  DCMI interface flag is set or not.
 
+  * @param  DCMI_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
 
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
 
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
 
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
 
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
 
+  *            @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
 
+  *            @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
 
+  *            @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
 
+  *            @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
 
+  *            @arg DCMI_FLAG_LINEMI: Line Masked flag mask
 
+  *            @arg DCMI_FLAG_HSYNC: HSYNC flag mask
 
+  *            @arg DCMI_FLAG_VSYNC: VSYNC flag mask
 
+  *            @arg DCMI_FLAG_FNE: Fifo not empty flag mask
 
+  * @retval The new state of DCMI_FLAG (SET or RESET).
 
+  */
 
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  uint32_t dcmireg, tempreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
 
+  
+  /* Get the DCMI register index */
 
+  dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
 
+  
+  if (dcmireg == 0x00) /* The FLAG is in RISR register */
 
+  {
 
+    tempreg= DCMI->RISR;
 
+  }
 
+  else if (dcmireg == 0x02) /* The FLAG is in SR register */
 
+  {
 
+    tempreg = DCMI->SR;
 
+  }
 
+  else /* The FLAG is in MISR register */
 
+  {
 
+    tempreg = DCMI->MISR;
 
+  }
 
+  
+  if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the DCMI_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DCMI's pending flags.
 
+  * @param  DCMI_FLAG: specifies the flag to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
 
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
 
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
 
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
 
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
 
+  * @retval None
 
+  */
 
+void DCMI_ClearFlag(uint16_t DCMI_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
 
+  
+  /* Clear the flag by writing in the ICR register 1 in the corresponding 
+  Flag position*/
 
+  
+  DCMI->ICR = DCMI_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the DCMI interrupt has occurred or not.
 
+  * @param  DCMI_IT: specifies the DCMI interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
 
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
 
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
 
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
 
+  *            @arg DCMI_IT_LINE: Line interrupt mask
 
+  * @retval The new state of DCMI_IT (SET or RESET).
 
+  */
 
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t itstatus = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DCMI_GET_IT(DCMI_IT));
 
+  
+  itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
 
+  
+  if ((itstatus != (uint16_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DCMI's interrupt pending bits.
 
+  * @param  DCMI_IT: specifies the DCMI interrupt pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
 
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
 
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
 
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
 
+  *            @arg DCMI_IT_LINE: Line interrupt mask
 
+  * @retval None
 
+  */
 
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
 
+{
 
+  /* Clear the interrupt pending Bit by writing in the ICR register 1 in the 
+  corresponding pending Bit position*/
 
+  
+  DCMI->ICR = DCMI_IT;
 
+}
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1289 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_dma.c
Ver arquivo 

@@ -0,0 +1,1289 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_dma.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):           
+  *           - Initialization and Configuration
 
+  *           - Data Counter
 
+  *           - Double Buffer mode configuration and command  
+  *           - Interrupts and flags management
 
+  *           
+  *  @verbatim
 
+  *      
+  *          ===================================================================      
+  *                                 How to use this driver
 
+  *          =================================================================== 
+  *          1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
 
+  *             function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
 
+  *             function for DMA2.
 
+  *
 
+  *          2. Enable and configure the peripheral to be connected to the DMA Stream
 
+  *             (except for internal SRAM / FLASH memories: no initialization is 
+  *             necessary). 
+  *        
+  *          3. For a given Stream, program the required configuration through following parameters:   
+  *             Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination 
+  *             data formats, Circular or Normal mode, Stream Priority level, Source and Destination 
+  *             Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or 
+  *             Destination (if needed) using the DMA_Init() function.
 
+  *             To avoid filling un-nesecessary fields, you can call DMA_StructInit() function
 
+  *             to initialize a given structure with default values (reset values), the modify
 
+  *             only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats).
 
+  *
 
+  *          4. Enable the NVIC and the corresponding interrupt(s) using the function 
+  *             DMA_ITConfig() if you need to use DMA interrupts. 
+  *
 
+  *          5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring 
+  *             the second Memory address and the first Memory to be used through the function 
+  *             DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
 
+  *             DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
 
+  *    
+  *          6. Enable the DMA stream using the DMA_Cmd() function. 
+  *                
+  *          7. Activate the needed Stream Request using PPP_DMACmd() function for
 
+  *             any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
 
+  *             The function allowing this operation is provided in each PPP peripheral
 
+  *             driver (ie. SPI_DMACmd for SPI peripheral).
 
+  *             Once the Stream is enabled, it is not possible to modify its configuration
 
+  *             unless the stream is stopped and disabled.
 
+  *             After enabling the Stream, it is advised to monitor the EN bit status using
 
+  *             the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
 
+  *             this bit will remain reset and all transfers on this Stream will remain on hold.      
+  *
 
+  *          8. Optionally, you can configure the number of data to be transferred
 
+  *             when the Stream is disabled (ie. after each Transfer Complete event
 
+  *             or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
 
+  *             And you can get the number of remaining data to be transferred using 
+  *             the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
 
+  *             enabled and running).  
+  *                   
+  *          9. To control DMA events you can use one of the following 
+  *              two methods:
 
+  *               a- Check on DMA Stream flags using the function DMA_GetFlagStatus().  
+  *               b- Use DMA interrupts through the function DMA_ITConfig() at initialization
 
+  *                  phase and DMA_GetITStatus() function into interrupt routines in
 
+  *                  communication phase.  
+  *              After checking on a flag you should clear it using DMA_ClearFlag()
 
+  *              function. And after checking on an interrupt event you should 
+  *              clear it using DMA_ClearITPendingBit() function.    
+  *              
+  *          10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
 
+  *              the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
 
+  *              the Memory Address to be modified is not the one currently in use by DMA Stream.
 
+  *              This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
 
+  *              
+  *          11. Optionally, Pause-Resume operations may be performed:
 
+  *              The DMA_Cmd() function may be used to perform Pause-Resume operation. When a 
+  *              transfer is ongoing, calling this function to disable the Stream will cause the 
+  *              transfer to be paused. All configuration registers and the number of remaining 
+  *              data will be preserved. When calling again this function to re-enable the Stream, 
+  *              the transfer will be resumed from the point where it was paused.          
+  *                 
+  * @note   Memory-to-Memory transfer is possible by setting the address of the memory into
 
+  *         the Peripheral registers. In this mode, Circular mode and Double Buffer mode
 
+  *         are not allowed.
 
+  *  
+  * @note   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
 
+  *         possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
 
+  *         Half-Word data size for the peripheral to access its data register and set Word data size
 
+  *         for the Memory to gain in access time. Each two Half-words will be packed and written in
 
+  *         a single access to a Word in the Memory).
 
+  *    
+  * @note  When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
 
+  *        and Destination. In this case the Peripheral Data Size will be applied to both Source
 
+  *        and Destination.               
+  *
 
+  *  @endverbatim
 
+  *                                  
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_dma.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DMA 
+  * @brief DMA driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* Masks Definition */
 
+#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
 
+                                           DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
 
+
 
+#define DMA_Stream0_IT_MASK     (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
 
+                                           DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
 
+                                           DMA_LISR_TCIF0)
 
+
 
+#define DMA_Stream1_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 6)
 
+#define DMA_Stream2_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 16)
 
+#define DMA_Stream3_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 22)
 
+#define DMA_Stream4_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream5_IT_MASK     (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream6_IT_MASK     (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream7_IT_MASK     (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
 
+#define TRANSFER_IT_MASK        (uint32_t)0x0F3C0F3C
 
+#define HIGH_ISR_MASK           (uint32_t)0x20000000
 
+#define RESERVED_MASK           (uint32_t)0x0F7D0F7D  
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+
 
+/** @defgroup DMA_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup DMA_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                 Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+  This subsection provides functions allowing to initialize the DMA Stream source
 
+  and destination addresses, incrementation and data sizes, transfer direction, 
+  buffer size, circular/normal mode selection, memory-to-memory mode selection 
+  and Stream priority value.
 
+  
+  The DMA_Init() function follows the DMA configuration procedures as described in
 
+  reference manual (RM0090) except the first point: waiting on EN bit to be reset.
 
+  This condition should be checked by user application using the function DMA_GetCmdStatus()
 
+  before calling the DMA_Init() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitialize the DMAy Streamx registers to their default reset values.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *         to 7 to select the DMA Stream.
 
+  * @retval None
 
+  */
 
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+
 
+  /* Disable the selected DMAy Streamx */
 
+  DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
 
+
 
+  /* Reset DMAy Streamx control register */
 
+  DMAy_Streamx->CR  = 0;
 
+  
+  /* Reset DMAy Streamx Number of Data to Transfer register */
 
+  DMAy_Streamx->NDTR = 0;
 
+  
+  /* Reset DMAy Streamx peripheral address register */
 
+  DMAy_Streamx->PAR  = 0;
 
+  
+  /* Reset DMAy Streamx memory 0 address register */
 
+  DMAy_Streamx->M0AR = 0;
 
+
 
+  /* Reset DMAy Streamx memory 1 address register */
 
+  DMAy_Streamx->M1AR = 0;
 
+
 
+  /* Reset DMAy Streamx FIFO control register */
 
+  DMAy_Streamx->FCR = (uint32_t)0x00000021; 
+
 
+  /* Reset interrupt pending bits for the selected stream */
 
+  if (DMAy_Streamx == DMA1_Stream0)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream0 */
 
+    DMA1->LIFCR = DMA_Stream0_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream1)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream1 */
 
+    DMA1->LIFCR = DMA_Stream1_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream2)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream2 */
 
+    DMA1->LIFCR = DMA_Stream2_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream3)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream3 */
 
+    DMA1->LIFCR = DMA_Stream3_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream4)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream4 */
 
+    DMA1->HIFCR = DMA_Stream4_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream5)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream5 */
 
+    DMA1->HIFCR = DMA_Stream5_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream6)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream6 */
 
+    DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA1_Stream7)
 
+  {
 
+    /* Reset interrupt pending bits for DMA1 Stream7 */
 
+    DMA1->HIFCR = DMA_Stream7_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream0)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream0 */
 
+    DMA2->LIFCR = DMA_Stream0_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream1)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream1 */
 
+    DMA2->LIFCR = DMA_Stream1_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream2)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream2 */
 
+    DMA2->LIFCR = DMA_Stream2_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream3)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream3 */
 
+    DMA2->LIFCR = DMA_Stream3_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream4)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream4 */
 
+    DMA2->HIFCR = DMA_Stream4_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream5)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream5 */
 
+    DMA2->HIFCR = DMA_Stream5_IT_MASK;
 
+  }
 
+  else if (DMAy_Streamx == DMA2_Stream6)
 
+  {
 
+    /* Reset interrupt pending bits for DMA2 Stream6 */
 
+    DMA2->HIFCR = DMA_Stream6_IT_MASK;
 
+  }
 
+  else 
+  {
 
+    if (DMAy_Streamx == DMA2_Stream7)
 
+    {
 
+      /* Reset interrupt pending bits for DMA2 Stream7 */
 
+      DMA2->HIFCR = DMA_Stream7_IT_MASK;
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the DMAy Streamx according to the specified parameters in 
+  *         the DMA_InitStruct structure.
 
+  * @note   Before calling this function, it is recommended to check that the Stream 
+  *         is actually disabled using the function DMA_GetCmdStatus().  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *         to 7 to select the DMA Stream.
 
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
 
+  *         the configuration information for the specified DMA Stream.  
+  * @retval None
 
+  */
 
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
 
+  assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
 
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
 
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
 
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
 
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
 
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
 
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
 
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
 
+  assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
 
+  assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
 
+  assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
 
+  assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
 
+
 
+  /*------------------------- DMAy Streamx CR Configuration ------------------*/
 
+  /* Get the DMAy_Streamx CR value */
 
+  tmpreg = DMAy_Streamx->CR;
 
+
 
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
 
+  tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
 
+                         DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
 
+                         DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
 
+                         DMA_SxCR_DIR));
 
+
 
+  /* Configure DMAy Streamx: */
 
+  /* Set CHSEL bits according to DMA_CHSEL value */
 
+  /* Set DIR bits according to DMA_DIR value */
 
+  /* Set PINC bit according to DMA_PeripheralInc value */
 
+  /* Set MINC bit according to DMA_MemoryInc value */
 
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
 
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
 
+  /* Set CIRC bit according to DMA_Mode value */
 
+  /* Set PL bits according to DMA_Priority value */
 
+  /* Set MBURST bits according to DMA_MemoryBurst value */
 
+  /* Set PBURST bits according to DMA_PeripheralBurst value */
 
+  tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
 
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
 
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
 
+            DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
 
+            DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
 
+
 
+  /* Write to DMAy Streamx CR register */
 
+  DMAy_Streamx->CR = tmpreg;
 
+
 
+  /*------------------------- DMAy Streamx FCR Configuration -----------------*/
 
+  /* Get the DMAy_Streamx FCR value */
 
+  tmpreg = DMAy_Streamx->FCR;
 
+
 
+  /* Clear DMDIS and FTH bits */
 
+  tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
 
+
 
+  /* Configure DMAy Streamx FIFO: 
+    Set DMDIS bits according to DMA_FIFOMode value 
+    Set FTH bits according to DMA_FIFOThreshold value */
 
+  tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
 
+
 
+  /* Write to DMAy Streamx CR */
 
+  DMAy_Streamx->FCR = tmpreg;
 
+
 
+  /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
 
+  /* Write to DMAy Streamx NDTR register */
 
+  DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
 
+
 
+  /*------------------------- DMAy Streamx PAR Configuration -----------------*/
 
+  /* Write to DMAy Streamx PAR */
 
+  DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
 
+
 
+  /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
 
+  /* Write to DMAy Streamx M0AR */
 
+  DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each DMA_InitStruct member with its default value.
 
+  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
 
+{
 
+  /*-------------- Reset DMA init structure parameters values ----------------*/
 
+  /* Initialize the DMA_Channel member */
 
+  DMA_InitStruct->DMA_Channel = 0;
 
+
 
+  /* Initialize the DMA_PeripheralBaseAddr member */
 
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
 
+
 
+  /* Initialize the DMA_Memory0BaseAddr member */
 
+  DMA_InitStruct->DMA_Memory0BaseAddr = 0;
 
+
 
+  /* Initialize the DMA_DIR member */
 
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
 
+
 
+  /* Initialize the DMA_BufferSize member */
 
+  DMA_InitStruct->DMA_BufferSize = 0;
 
+
 
+  /* Initialize the DMA_PeripheralInc member */
 
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
 
+
 
+  /* Initialize the DMA_MemoryInc member */
 
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
 
+
 
+  /* Initialize the DMA_PeripheralDataSize member */
 
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
 
+
 
+  /* Initialize the DMA_MemoryDataSize member */
 
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
 
+
 
+  /* Initialize the DMA_Mode member */
 
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
 
+
 
+  /* Initialize the DMA_Priority member */
 
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
 
+
 
+  /* Initialize the DMA_FIFOMode member */
 
+  DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
 
+
 
+  /* Initialize the DMA_FIFOThreshold member */
 
+  DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
 
+
 
+  /* Initialize the DMA_MemoryBurst member */
 
+  DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
 
+
 
+  /* Initialize the DMA_PeripheralBurst member */
 
+  DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DMAy Streamx.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *         to 7 to select the DMA Stream.
 
+  * @param  NewState: new state of the DMAy Streamx. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  *
 
+  * @note  This function may be used to perform Pause-Resume operation. When a
 
+  *        transfer is ongoing, calling this function to disable the Stream will
 
+  *        cause the transfer to be paused. All configuration registers and the
 
+  *        number of remaining data will be preserved. When calling again this
 
+  *        function to re-enable the Stream, the transfer will be resumed from
 
+  *        the point where it was paused.          
+  *    
+  * @note  After configuring the DMA Stream (DMA_Init() function) and enabling the
 
+  *        stream, it is recommended to check (or wait until) the DMA Stream is
 
+  *        effectively enabled. A Stream may remain disabled if a configuration 
+  *        parameter is wrong.
 
+  *        After disabling a DMA Stream, it is also recommended to check (or wait
 
+  *        until) the DMA Stream is effectively disabled. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
 
+  *        and the Stream will be effectively disabled only after the transfer of
 
+  *        this single data is finished.            
+  *    
+  * @retval None
 
+  */
 
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected DMAy Streamx by setting EN bit */
 
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected DMAy Streamx by clearing EN bit */
 
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures, when the PINC (Peripheral Increment address mode) bit is
 
+  *         set, if the peripheral address should be incremented with the data 
+  *         size (configured with PSIZE bits) or by a fixed offset equal to 4
 
+  *         (32-bit aligned addresses).
 
+  *   
+  * @note   This function has no effect if the Peripheral Increment mode is disabled.
 
+  *     
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_Pincos: specifies the Peripheral increment offset size.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DMA_PINCOS_Psize: Peripheral address increment is done  
+  *                                   accordingly to PSIZE parameter.
 
+  *            @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is 
+  *                                         fixed to 4 (32-bit aligned addresses). 
+  * @retval None
 
+  */
 
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
 
+
 
+  /* Check the needed Peripheral increment offset */
 
+  if(DMA_Pincos != DMA_PINCOS_Psize)
 
+  {
 
+    /* Configure DMA_SxCR_PINCOS bit with the input parameter */
 
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;     
+  }
 
+  else
 
+  {
 
+    /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
 
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;    
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures, when the DMAy Streamx is disabled, the flow controller for
 
+  *         the next transactions (Peripheral or Memory).
 
+  *       
+  * @note   Before enabling this feature, check if the used peripheral supports 
+  *         the Flow Controller mode or not.    
+  *  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_FlowCtrl: specifies the DMA flow controller.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is 
+  *                                      the DMA controller.
 
+  *            @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller 
+  *                                          is the peripheral.    
+  * @retval None
 
+  */
 
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
 
+
 
+  /* Check the needed flow controller  */
 
+  if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
 
+  {
 
+    /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
 
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;   
+  }
 
+  else
 
+  {
 
+    /* Clear the PFCTRL bit: Memory is the flow controller */
 
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;    
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DMA_Group2 Data Counter functions
 
+ *  @brief   Data Counter functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                           Data Counter functions
 
+ ===============================================================================  
+
 
+  This subsection provides function allowing to configure and read the buffer size
 
+  (number of data to be transferred). 
+
 
+  The DMA data counter can be written only when the DMA Stream is disabled 
+  (ie. after transfer complete event).
 
+
 
+  The following function can be used to write the Stream data counter value:
 
+    - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
 
+
 
+@note It is advised to use this function rather than DMA_Init() in situations where
 
+      only the Data buffer needs to be reloaded.
 
+
 
+@note If the Source and Destination Data Sizes are different, then the value written in
 
+      data counter, expressing the number of transfers, is relative to the number of 
+      transfers from the Peripheral point of view.
 
+      ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value
 
+      to be configured in the data counter is the number of Half-Words to be transferred
 
+      from/to the peripheral.
 
+
 
+  The DMA data counter can be read to indicate the number of remaining transfers for
 
+  the relative DMA Stream. This counter is decremented at the end of each data 
+  transfer and when the transfer is complete: 
+   - If Normal mode is selected: the counter is set to 0.
 
+   - If Circular mode is selected: the counter is reloaded with the initial value
 
+     (configured before enabling the DMA Stream)
 
+   
+  The following function can be used to read the Stream data counter value:
 
+     - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Writes the number of data units to be transferred on the DMAy Streamx.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  Counter: Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
 
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
 
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
 
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
 
+  *      
+  * @note   In Memory-to-Memory transfer mode, the memory buffer pointed by 
+  *         DMAy_SxPAR register is considered as Peripheral.
 
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
 
+  */
 
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+
 
+  /* Write the number of data units to be transferred */
 
+  DMAy_Streamx->NDTR = (uint16_t)Counter;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
 
+  */
 
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+
 
+  /* Return the number of remaining data units for DMAy Streamx */
 
+  return ((uint16_t)(DMAy_Streamx->NDTR));
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DMA_Group3 Double Buffer mode functions
 
+ *  @brief   Double Buffer mode functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Double Buffer mode functions
 
+ ===============================================================================  
+
 
+  This subsection provides function allowing to configure and control the double 
+  buffer mode parameters.
 
+  
+  The Double Buffer mode can be used only when Circular mode is enabled.
 
+  The Double Buffer mode cannot be used when transferring data from Memory to Memory.
 
+  
+  The Double Buffer mode allows to set two different Memory addresses from/to which
 
+  the DMA controller will access alternatively (after completing transfer to/from target
 
+  memory 0, it will start transfer to/from target memory 1).
 
+  This allows to reduce software overhead for double buffering and reduce the CPU
 
+  access time.
 
+
 
+  Two functions must be called before calling the DMA_Init() function:
 
+   - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
 
+                                uint32_t DMA_CurrentMemory);
 
+   - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
 
+   
+  DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first
 
+  Memory target from/to which the transfer will start after enabling the DMA Stream.
 
+  Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable 
+  it when it should not be used).
 
+  
+   
+  Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is 
+  stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
 
+   used:
 
+    - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
 
+                            uint32_t DMA_MemoryTarget);
 
+    - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
 
+
 
+  DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories.
 
+  The Memory of which the base address will be modified must not be currently be used by the DMA Stream
 
+  (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address
 
+  of target Memory 0 and vice versa).
 
+  To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
 
+  returns the index of the Memory target currently in use by the DMA Stream.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Configures, when the DMAy Streamx is disabled, the double buffer mode 
+  *         and the current memory target.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  Memory1BaseAddr: the base address of the second buffer (Memory 1)  
+  * @param  DMA_CurrentMemory: specifies which memory will be first buffer for
 
+  *         the transactions when the Stream will be enabled. 
+  *          This parameter can be one of the following values:
 
+  *            @arg DMA_Memory_0: Memory 0 is the current buffer.
 
+  *            @arg DMA_Memory_1: Memory 1 is the current buffer.  
+  *       
+  * @note   Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
 
+  *   
+  * @retval None
 
+  */
 
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
 
+                                uint32_t DMA_CurrentMemory)
 
+{  
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
 
+
 
+  if (DMA_CurrentMemory != DMA_Memory_0)
 
+  {
 
+    /* Set Memory 1 as current memory address */
 
+    DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);    
+  }
 
+  else
 
+  {
 
+    /* Set Memory 0 as current memory address */
 
+    DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);    
+  }
 
+
 
+  /* Write to DMAy Streamx M1AR */
 
+  DMAy_Streamx->M1AR = Memory1BaseAddr;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the double buffer mode for the selected DMA stream.
 
+  * @note   This function can be called only when the DMA Stream is disabled.  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  NewState: new state of the DMAy Streamx double buffer mode. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
 
+{  
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Configure the Double Buffer mode */
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Double buffer mode */
 
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Double buffer mode */
 
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the Memory address for the next buffer transfer in double
 
+  *         buffer mode (for dynamic use). This function can be called when the
 
+  *         DMA Stream is enabled and when the transfer is ongoing.  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  MemoryBaseAddr: The base address of the target memory buffer
 
+  * @param  DMA_MemoryTarget: Next memory target to be used. 
+  *         This parameter can be one of the following values:
 
+  *            @arg DMA_Memory_0: To use the memory address 0
 
+  *            @arg DMA_Memory_1: To use the memory address 1
 
+  * 
+  * @note    It is not allowed to modify the Base Address of a target Memory when
 
+  *          this target is involved in the current transfer. ie. If the DMA Stream
 
+  *          is currently transferring to/from Memory 1, then it not possible to
 
+  *          modify Base address of Memory 1, but it is possible to modify Base
 
+  *          address of Memory 0.
 
+  *          To know which Memory is currently used, you can use the function
 
+  *          DMA_GetCurrentMemoryTarget().             
+  *  
+  * @retval None
 
+  */
 
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
 
+                           uint32_t DMA_MemoryTarget)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
 
+    
+  /* Check the Memory target to be configured */
 
+  if (DMA_MemoryTarget != DMA_Memory_0)
 
+  {
 
+    /* Write to DMAy Streamx M1AR */
 
+    DMAy_Streamx->M1AR = MemoryBaseAddr;    
+  }  
+  else
 
+  {
 
+    /* Write to DMAy Streamx M0AR */
 
+    DMAy_Streamx->M0AR = MemoryBaseAddr;  
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the current memory target used by double buffer transfer.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @retval The memory target number: 0 for Memory0 or 1 for Memory1. 
+  */
 
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
 
+{
 
+  uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+
 
+  /* Get the current memory target */
 
+  if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
 
+  {
 
+    /* Current memory buffer used is Memory 1 */
 
+    tmp = 1;
 
+  }  
+  else
 
+  {
 
+    /* Current memory buffer used is Memory 0 */
 
+    tmp = 0;    
+  }
 
+  return tmp;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup DMA_Group4 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This subsection provides functions allowing to
 
+   - Check the DMA enable status
 
+   - Check the FIFO status 
+   - Configure the DMA Interrupts sources and check or clear the flags or pending bits status.   
+   
+ 1. DMA Enable status:
 
+   After configuring the DMA Stream (DMA_Init() function) and enabling the stream,
 
+   it is recommended to check (or wait until) the DMA Stream is effectively enabled.
 
+   A Stream may remain disabled if a configuration parameter is wrong.
 
+   After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA
 
+   Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, 
+   the current data will be transferred and the Stream will be effectively disabled only after
 
+   this data transfer completion.
 
+   To monitor this state it is possible to use the following function:
 
+     - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+ 2. FIFO Status:
 
+   It is possible to monitor the FIFO status when a transfer is ongoing using the following 
+   function:
 
+     - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+ 3. DMA Interrupts and Flags:
 
+  The user should identify which mode will be used in his application to manage the
 
+  DMA controller events: Polling mode or Interrupt mode. 
+    
+  Polling Mode
 
+  =============
 
+    Each DMA stream can be managed through 4 event Flags:
 
+    (x : DMA Stream number )
 
+       1. DMA_FLAG_FEIFx  : to indicate that a FIFO Mode Transfer Error event occurred.
 
+       2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
 
+       3. DMA_FLAG_TEIFx  : to indicate that a Transfer Error event occurred.
 
+       4. DMA_FLAG_HTIFx  : to indicate that a Half-Transfer Complete event occurred.
 
+       5. DMA_FLAG_TCIFx  : to indicate that a Transfer Complete event occurred .       
+
 
+   In this Mode it is advised to use the following functions:
 
+      - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
 
+      - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
 
+
 
+  Interrupt Mode
 
+  ===============
 
+    Each DMA Stream can be managed through 4 Interrupts:
 
+
 
+    Interrupt Source
 
+    ----------------
 
+       1. DMA_IT_FEIFx  : specifies the interrupt source for the  FIFO Mode Transfer Error event.
 
+       2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
 
+       3. DMA_IT_TEIFx  : specifies the interrupt source for the Transfer Error event.
 
+       4. DMA_IT_HTIFx  : specifies the interrupt source for the Half-Transfer Complete event.
 
+       5. DMA_IT_TCIFx  : specifies the interrupt source for the a Transfer Complete event. 
+     
+  In this Mode it is advised to use the following functions:
 
+     - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
 
+     - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
 
+     - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Returns the status of EN bit for the specified DMAy Streamx.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  *   
+  * @note    After configuring the DMA Stream (DMA_Init() function) and enabling
 
+  *          the stream, it is recommended to check (or wait until) the DMA Stream
 
+  *          is effectively enabled. A Stream may remain disabled if a configuration
 
+  *          parameter is wrong.
 
+  *          After disabling a DMA Stream, it is also recommended to check (or wait 
+  *          until) the DMA Stream is effectively disabled. If a Stream is disabled
 
+  *          while a data transfer is ongoing, the current data will be transferred
 
+  *          and the Stream will be effectively disabled only after the transfer
 
+  *          of this single data is finished.  
+  *      
+  * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
 
+  */
 
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
 
+{
 
+  FunctionalState state = DISABLE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+
 
+  if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
 
+  {
 
+    /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
 
+    state = ENABLE;
 
+  }
 
+  else
 
+  {
 
+    /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and 
+        all transfers are complete) */
 
+    state = DISABLE;
 
+  }
 
+  return state;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the current DMAy Streamx FIFO filled level.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 
+  *         to 7 to select the DMA Stream.
 
+  * @retval The FIFO filling state.
 
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                               and not empty.
 
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
 
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
 
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
 
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
 
+  *           - DMA_FIFOStatus_Full: when FIFO is full
 
+  */
 
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
 
+{
 
+  uint32_t tmpreg = 0;
 
+ 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  
+  /* Get the FIFO level bits */
 
+  tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
 
+  
+  return tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified DMAy Streamx flag is set or not.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
 
+  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
 
+  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
 
+  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
 
+  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
 
+  *         Where x can be 0 to 7 to select the DMA Stream.
 
+  * @retval The new state of DMA_FLAG (SET or RESET).
 
+  */
 
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  DMA_TypeDef* DMAy;
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
 
+
 
+  /* Determine the DMA to which belongs the stream */
 
+  if (DMAy_Streamx < DMA2_Stream0)
 
+  {
 
+    /* DMAy_Streamx belongs to DMA1 */
 
+    DMAy = DMA1; 
+  } 
+  else 
+  {
 
+    /* DMAy_Streamx belongs to DMA2 */
 
+    DMAy = DMA2; 
+  }
 
+
 
+  /* Check if the flag is in HISR or LISR */
 
+  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
 
+  {
 
+    /* Get DMAy HISR register value */
 
+    tmpreg = DMAy->HISR;
 
+  }
 
+  else
 
+  {
 
+    /* Get DMAy LISR register value */
 
+    tmpreg = DMAy->LISR;
 
+  }   
+ 
+  /* Mask the reserved bits */
 
+  tmpreg &= (uint32_t)RESERVED_MASK;
 
+
 
+  /* Check the status of the specified DMA flag */
 
+  if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
 
+  {
 
+    /* DMA_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* DMA_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+
 
+  /* Return the DMA_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DMAy Streamx's pending flags.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_FLAG: specifies the flag to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
 
+  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
 
+  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
 
+  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
 
+  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
 
+  *         Where x can be 0 to 7 to select the DMA Stream.   
+  * @retval None
 
+  */
 
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
 
+{
 
+  DMA_TypeDef* DMAy;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
 
+
 
+  /* Determine the DMA to which belongs the stream */
 
+  if (DMAy_Streamx < DMA2_Stream0)
 
+  {
 
+    /* DMAy_Streamx belongs to DMA1 */
 
+    DMAy = DMA1; 
+  } 
+  else 
+  {
 
+    /* DMAy_Streamx belongs to DMA2 */
 
+    DMAy = DMA2; 
+  }
 
+
 
+  /* Check if LIFCR or HIFCR register is targeted */
 
+  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
 
+  {
 
+    /* Set DMAy HIFCR register clear flag bits */
 
+    DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
 
+  }
 
+  else 
+  {
 
+    /* Set DMAy LIFCR register clear flag bits */
 
+    DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
 
+  }    
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified DMAy Streamx interrupts.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
 
+  *            @arg DMA_IT_FE:  FIFO error interrupt mask
 
+  * @param  NewState: new state of the specified DMA interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Check if the DMA_IT parameter contains a FIFO interrupt */
 
+  if ((DMA_IT & DMA_IT_FE) != 0)
 
+  {
 
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the selected DMA FIFO interrupts */
 
+      DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
 
+    }    
+    else 
+    {
 
+      /* Disable the selected DMA FIFO interrupts */
 
+      DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;  
+    }
 
+  }
 
+
 
+  /* Check if the DMA_IT parameter contains a Transfer interrupt */
 
+  if (DMA_IT != DMA_IT_FE)
 
+  {
 
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the selected DMA transfer interrupts */
 
+      DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
 
+    }
 
+    else
 
+    {
 
+      /* Disable the selected DMA transfer interrupts */
 
+      DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
 
+    }    
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified DMAy Streamx interrupt has occurred or not.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_IT: specifies the DMA interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg DMA_IT_TCIFx:  Streamx transfer complete interrupt
 
+  *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
 
+  *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
 
+  *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
 
+  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
 
+  *         Where x can be 0 to 7 to select the DMA Stream.
 
+  * @retval The new state of DMA_IT (SET or RESET).
 
+  */
 
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  DMA_TypeDef* DMAy;
 
+  uint32_t tmpreg = 0, enablestatus = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_GET_IT(DMA_IT));
 
+ 
+  /* Determine the DMA to which belongs the stream */
 
+  if (DMAy_Streamx < DMA2_Stream0)
 
+  {
 
+    /* DMAy_Streamx belongs to DMA1 */
 
+    DMAy = DMA1; 
+  } 
+  else 
+  {
 
+    /* DMAy_Streamx belongs to DMA2 */
 
+    DMAy = DMA2; 
+  }
 
+
 
+  /* Check if the interrupt enable bit is in the CR or FCR register */
 
+  if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
 
+  {
 
+    /* Get the interrupt enable position mask in CR register */
 
+    tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
+    
+    /* Check the enable bit in CR register */
 
+    enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
 
+  }
 
+  else 
+  {
 
+    /* Check the enable bit in FCR register */
 
+    enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); 
+  }
 
+ 
+  /* Check if the interrupt pending flag is in LISR or HISR */
 
+  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
 
+  {
 
+    /* Get DMAy HISR register value */
 
+    tmpreg = DMAy->HISR ;
 
+  }
 
+  else
 
+  {
 
+    /* Get DMAy LISR register value */
 
+    tmpreg = DMAy->LISR ;
 
+  } 
+
 
+  /* mask all reserved bits */
 
+  tmpreg &= (uint32_t)RESERVED_MASK;
 
+
 
+  /* Check the status of the specified DMA interrupt */
 
+  if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 
+  {
 
+    /* DMA_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* DMA_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+
 
+  /* Return the DMA_IT status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the DMAy Streamx's interrupt pending bits.
 
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
 
+  *          to 7 to select the DMA Stream.
 
+  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg DMA_IT_TCIFx:  Streamx transfer complete interrupt
 
+  *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
 
+  *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
 
+  *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
 
+  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
 
+  *         Where x can be 0 to 7 to select the DMA Stream.
 
+  * @retval None
 
+  */
 
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
 
+{
 
+  DMA_TypeDef* DMAy;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
 
+  assert_param(IS_DMA_CLEAR_IT(DMA_IT));
 
+
 
+  /* Determine the DMA to which belongs the stream */
 
+  if (DMAy_Streamx < DMA2_Stream0)
 
+  {
 
+    /* DMAy_Streamx belongs to DMA1 */
 
+    DMAy = DMA1; 
+  } 
+  else 
+  {
 
+    /* DMAy_Streamx belongs to DMA2 */
 
+    DMAy = DMA2; 
+  }
 
+
 
+  /* Check if LIFCR or HIFCR register is targeted */
 
+  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
 
+  {
 
+    /* Set DMAy HIFCR register clear interrupt bits */
 
+    DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
 
+  }
 
+  else 
+  {
 
+    /* Set DMAy LIFCR register clear interrupt bits */
 
+    DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
 
+  }   
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 312 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_exti.c
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@@ -0,0 +1,312 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_exti.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:           
+  *           - Initialization and Configuration
 
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim  
+  *  
+  *          ===================================================================
 
+  *                                     EXTI features
 
+  *          ===================================================================
 
+  *    
+  *          External interrupt/event lines are mapped as following:
 
+  *            1- All available GPIO pins are connected to the 16 external 
+  *               interrupt/event lines from EXTI0 to EXTI15.
 
+  *            2- EXTI line 16 is connected to the PVD Output
 
+  *            3- EXTI line 17 is connected to the RTC Alarm event
 
+  *            4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event                                    
+  *            5- EXTI line 19 is connected to the Ethernet Wakeup event
 
+  *            6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+  *            7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events                                               
+  *            8- EXTI line 22 is connected to the RTC Wakeup event
 
+  *        
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================  
+  *              
+  *          In order to use an I/O pin as an external interrupt source, follow
 
+  *          steps below:
 
+  *            1- Configure the I/O in input mode using GPIO_Init()
 
+  *            2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
 
+  *            3- Select the mode(interrupt, event) and configure the trigger 
+  *               selection (Rising, falling or both) using EXTI_Init()
 
+  *            4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
 
+  *   
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
 
+  *         registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
 
+  *          
+  *  @endverbatim                  
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_exti.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup EXTI_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void EXTI_DeInit(void)
 
+{
 
+  EXTI->IMR = 0x00000000;
 
+  EXTI->EMR = 0x00000000;
 
+  EXTI->RTSR = 0x00000000;
 
+  EXTI->FTSR = 0x00000000;
 
+  EXTI->PR = 0x007FFFFF;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the EXTI peripheral according to the specified
 
+  *         parameters in the EXTI_InitStruct.
 
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
 
+  *         that contains the configuration information for the EXTI peripheral.
 
+  * @retval None
 
+  */
 
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
 
+{
 
+  uint32_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
 
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
 
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
 
+
 
+  tmp = (uint32_t)EXTI_BASE;
 
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
 
+  {
 
+    /* Clear EXTI line configuration */
 
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
 
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
 
+
 
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
 
+
 
+    /* Clear Rising Falling edge configuration */
 
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
 
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
 
+    
+    /* Select the trigger for the selected external interrupts */
 
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
 
+    {
 
+      /* Rising Falling edge */
 
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
 
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
 
+    }
 
+    else
 
+    {
 
+      tmp = (uint32_t)EXTI_BASE;
 
+      tmp += EXTI_InitStruct->EXTI_Trigger;
 
+
 
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    tmp += EXTI_InitStruct->EXTI_Mode;
 
+
 
+    /* Disable the selected external lines */
 
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
 
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
 
+{
 
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
 
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
 
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
 
+}
 
+
 
+/**
 
+  * @brief  Generates a Software interrupt on selected EXTI line.
 
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
 
+  *         will be generated.
 
+  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
 
+  * @retval None
 
+  */
 
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_EXTI_LINE(EXTI_Line));
 
+  
+  EXTI->SWIER |= EXTI_Line;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Checks whether the specified EXTI line flag is set or not.
 
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
 
+  *          This parameter can be EXTI_Linex where x can be(0..22)
 
+  * @retval The new state of EXTI_Line (SET or RESET).
 
+  */
 
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
 
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the EXTI's line pending flags.
 
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
 
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
 
+  * @retval None
 
+  */
 
+void EXTI_ClearFlag(uint32_t EXTI_Line)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_EXTI_LINE(EXTI_Line));
 
+  
+  EXTI->PR = EXTI_Line;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified EXTI line is asserted or not.
 
+  * @param  EXTI_Line: specifies the EXTI line to check.
 
+  *          This parameter can be EXTI_Linex where x can be(0..22)
 
+  * @retval The new state of EXTI_Line (SET or RESET).
 
+  */
 
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t enablestatus = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
 
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
 
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the EXTI's line pending bits.
 
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
 
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
 
+  * @retval None
 
+  */
 
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_EXTI_LINE(EXTI_Line));
 
+  
+  EXTI->PR = EXTI_Line;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1062 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_flash.c
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@@ -0,0 +1,1062 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_flash.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH peripheral:
 
+  *            - FLASH Interface configuration
 
+  *            - FLASH Memory Programming
 
+  *            - Option Bytes Programming
 
+  *            - Interrupts and flags management
 
+  *  
+  *  @verbatim
 
+  *  
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *                           
+  *          This driver provides functions to configure and program the FLASH 
+  *          memory of all STM32F4xx devices.
 
+  *          These functions are split in 4 groups:
 
+  * 
+  *           1. FLASH Interface configuration functions: this group includes the
 
+  *              management of the following features:
 
+  *                    - Set the latency
 
+  *                    - Enable/Disable the prefetch buffer
 
+  *                    - Enable/Disable the Instruction cache and the Data cache
 
+  *                    - Reset the Instruction cache and the Data cache
 
+  *  
+  *           2. FLASH Memory Programming functions: this group includes all needed
 
+  *              functions to erase and program the main memory:
 
+  *                    - Lock and Unlock the FLASH interface
 
+  *                    - Erase function: Erase sector, erase all sectors
 
+  *                    - Program functions: byte, half word, word and double word
 
+  *  
+  *           3. Option Bytes Programming functions: this group includes all needed
 
+  *              functions to manage the Option Bytes:
 
+  *                    - Set/Reset the write protection
 
+  *                    - Set the Read protection Level
 
+  *                    - Set the BOR level
 
+  *                    - Program the user Option Bytes
 
+  *                    - Launch the Option Bytes loader
 
+  *  
+  *           4. Interrupts and flags management functions: this group 
+  *              includes all needed functions to:
 
+  *                    - Enable/Disable the FLASH interrupt sources
 
+  *                    - Get flags status
 
+  *                    - Clear flags
 
+  *                    - Get FLASH operation status
 
+  *                    - Wait for last FLASH operation
 
+  * 
+  *  @endverbatim
 
+  *                      
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_flash.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/ 
+#define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup FLASH_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
 
+  *  @brief   FLASH Interface configuration functions 
+ *
 
+
 
+@verbatim   
+ ===============================================================================
 
+                       FLASH Interface configuration functions
 
+ ===============================================================================
 
+
 
+   This group includes the following functions:
 
+    - void FLASH_SetLatency(uint32_t FLASH_Latency)
 
+       To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+       must be correctly programmed according to the frequency of the CPU clock 
+      (HCLK) and the supply voltage of the device.
 
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
 
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
 
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
 
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96  | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |      NA        |120 < HCLK <= 138|112 < HCLK <= 120| 
+ |***************|****************|****************|*****************|*****************|*****************************+
 
+ |               | voltage range  | voltage range  | voltage range   | voltage range   | voltage range 2.7 V - 3.6 V |
 
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   | with External Vpp = 9V      |
 
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| 
+ |Max Parallelism|      x32       |               x16                |       x8        |          x64                |              
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|   
+ |PSIZE[1:0]     |      10        |               01                 |       00        |           11                |
 
+ +-------------------------------------------------------------------------------------------------------------------+  
+   @note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
 
+         You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
 
+             
+    - void FLASH_PrefetchBufferCmd(FunctionalState NewState)
 
+    - void FLASH_InstructionCacheCmd(FunctionalState NewState)
 
+    - void FLASH_DataCacheCmd(FunctionalState NewState)
 
+    - void FLASH_InstructionCacheReset(void)
 
+    - void FLASH_DataCacheReset(void)
 
+   
+   The unlock sequence is not needed for these functions.
 
+ 
+@endverbatim
 
+  * @{
 
+  */
 
+ 
+/**
 
+  * @brief  Sets the code latency value.
 
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FLASH_Latency_0: FLASH Zero Latency cycle
 
+  *            @arg FLASH_Latency_1: FLASH One Latency cycle
 
+  *            @arg FLASH_Latency_2: FLASH Two Latency cycles
 
+  *            @arg FLASH_Latency_3: FLASH Three Latency cycles
 
+  *            @arg FLASH_Latency_4: FLASH Four Latency cycles 
+  *            @arg FLASH_Latency_5: FLASH Five Latency cycles 
+  *            @arg FLASH_Latency_6: FLASH Six Latency cycles
 
+  *            @arg FLASH_Latency_7: FLASH Seven Latency cycles      
+  * @retval None
 
+  */
 
+void FLASH_SetLatency(uint32_t FLASH_Latency)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
 
+  
+  /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
 
+  *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Prefetch Buffer.
 
+  * @param  NewState: new state of the Prefetch Buffer.
 
+  *          This parameter  can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  /* Enable or disable the Prefetch Buffer */
 
+  if(NewState != DISABLE)
 
+  {
 
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
 
+  }
 
+  else
 
+  {
 
+    FLASH->ACR &= (~FLASH_ACR_PRFTEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Instruction Cache feature.
 
+  * @param  NewState: new state of the Instruction Cache.
 
+  *          This parameter  can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FLASH_InstructionCacheCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if(NewState != DISABLE)
 
+  {
 
+    FLASH->ACR |= FLASH_ACR_ICEN;
 
+  }
 
+  else
 
+  {
 
+    FLASH->ACR &= (~FLASH_ACR_ICEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Data Cache feature.
 
+  * @param  NewState: new state of the Data Cache.
 
+  *          This parameter  can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FLASH_DataCacheCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if(NewState != DISABLE)
 
+  {
 
+    FLASH->ACR |= FLASH_ACR_DCEN;
 
+  }
 
+  else
 
+  {
 
+    FLASH->ACR &= (~FLASH_ACR_DCEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Resets the Instruction Cache.
 
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_InstructionCacheReset(void)
 
+{
 
+  FLASH->ACR |= FLASH_ACR_ICRST;
 
+}
 
+
 
+/**
 
+  * @brief  Resets the Data Cache.
 
+  * @note   This function must be used only when the Data Cache is disabled.  
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_DataCacheReset(void)
 
+{
 
+  FLASH->ACR |= FLASH_ACR_DCRST;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
 
+ *  @brief   FLASH Memory Programming functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                      FLASH Memory Programming functions
 
+ ===============================================================================   
+
 
+   This group includes the following functions:
 
+    - void FLASH_Unlock(void)
 
+    - void FLASH_Lock(void)
 
+    - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
 
+    - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
 
+    - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
 
+    - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
 
+    - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
 
+    - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
 
+   
+   Any operation of erase or program should follow these steps:
 
+   1. Call the FLASH_Unlock() function to enable the FLASH control register access
 
+
 
+   2. Call the desired function to erase sector(s) or program data
 
+
 
+   3. Call the FLASH_Lock() function to disable the FLASH control register access
 
+      (recommended to protect the FLASH memory against possible unwanted operation)
 
+    
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Unlocks the FLASH control register access
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_Unlock(void)
 
+{
 
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
 
+  {
 
+    /* Authorize the FLASH Registers access */
 
+    FLASH->KEYR = FLASH_KEY1;
 
+    FLASH->KEYR = FLASH_KEY2;
 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Locks the FLASH control register access
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_Lock(void)
 
+{
 
+  /* Set the LOCK Bit to lock the FLASH Registers access */
 
+  FLASH->CR |= FLASH_CR_LOCK;
 
+}
 
+
 
+/**
 
+  * @brief  Erases a specified FLASH Sector.
 
+  *   
+  * @param  FLASH_Sector: The Sector number to be erased.
 
+  *          This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11
 
+  *    
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
 
+  *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
 
+  *                                  the operation will be done by half word (16-bit)
 
+  *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
 
+  *                                  the operation will be done by word (32-bit)
 
+  *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
 
+  *       
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
 
+{
 
+  uint32_t tmp_psize = 0x0;
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_SECTOR(FLASH_Sector));
 
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
 
+  
+  if(VoltageRange == VoltageRange_1)
 
+  {
 
+     tmp_psize = FLASH_PSIZE_BYTE;
 
+  }
 
+  else if(VoltageRange == VoltageRange_2)
 
+  {
 
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
 
+  }
 
+  else if(VoltageRange == VoltageRange_3)
 
+  {
 
+    tmp_psize = FLASH_PSIZE_WORD;
 
+  }
 
+  else
 
+  {
 
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
 
+  }
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  { 
+    /* if the previous operation is completed, proceed to erase the sector */
 
+    FLASH->CR &= CR_PSIZE_MASK;
 
+    FLASH->CR |= tmp_psize;
 
+    FLASH->CR &= SECTOR_MASK;
 
+    FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
 
+    FLASH->CR |= FLASH_CR_STRT;
 
+    
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+    
+    /* if the erase operation is completed, disable the SER Bit */
 
+    FLASH->CR &= (~FLASH_CR_SER);
 
+    FLASH->CR &= SECTOR_MASK; 
+  }
 
+  /* Return the Erase Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Erases all FLASH Sectors.
 
+  *    
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
 
+  *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
 
+  *                                  the operation will be done by half word (16-bit)
 
+  *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
 
+  *                                  the operation will be done by word (32-bit)
 
+  *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
 
+  *       
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
 
+{
 
+  uint32_t tmp_psize = 0x0;
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+  
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
 
+  
+  if(VoltageRange == VoltageRange_1)
 
+  {
 
+     tmp_psize = FLASH_PSIZE_BYTE;
 
+  }
 
+  else if(VoltageRange == VoltageRange_2)
 
+  {
 
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
 
+  }
 
+  else if(VoltageRange == VoltageRange_3)
 
+  {
 
+    tmp_psize = FLASH_PSIZE_WORD;
 
+  }
 
+  else
 
+  {
 
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
 
+  }  
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    /* if the previous operation is completed, proceed to erase all sectors */
 
+     FLASH->CR &= CR_PSIZE_MASK;
 
+     FLASH->CR |= tmp_psize;
 
+     FLASH->CR |= FLASH_CR_MER;
 
+     FLASH->CR |= FLASH_CR_STRT;
 
+    
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+
 
+    /* if the erase operation is completed, disable the MER Bit */
 
+    FLASH->CR &= (~FLASH_CR_MER);
 
+
 
+  }   
+  /* Return the Erase Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Programs a double word (64-bit) at a specified address.
 
+  * @note   This function must be used when the device voltage range is from
 
+  *         2.7V to 3.6V and an External Vpp is present.           
+  * @param  Address: specifies the address to be programmed.
 
+  * @param  Data: specifies the data to be programmed.
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_ADDRESS(Address));
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    /* if the previous operation is completed, proceed to program the new data */
 
+    FLASH->CR &= CR_PSIZE_MASK;
 
+    FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
 
+    FLASH->CR |= FLASH_CR_PG;
 
+  
+    *(__IO uint64_t*)Address = Data;
 
+        
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+
 
+    /* if the program operation is completed, disable the PG Bit */
 
+    FLASH->CR &= (~FLASH_CR_PG);
 
+  } 
+  /* Return the Program Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Programs a word (32-bit) at a specified address.
 
+  * @param  Address: specifies the address to be programmed.
 
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @note   This function must be used when the device voltage range is from 2.7V to 3.6V. 
+  * @param  Data: specifies the data to be programmed.
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_ADDRESS(Address));
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    /* if the previous operation is completed, proceed to program the new data */
 
+    FLASH->CR &= CR_PSIZE_MASK;
 
+    FLASH->CR |= FLASH_PSIZE_WORD;
 
+    FLASH->CR |= FLASH_CR_PG;
 
+  
+    *(__IO uint32_t*)Address = Data;
 
+        
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+
 
+    /* if the program operation is completed, disable the PG Bit */
 
+    FLASH->CR &= (~FLASH_CR_PG);
 
+  } 
+  /* Return the Program Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Programs a half word (16-bit) at a specified address. 
+  * @note   This function must be used when the device voltage range is from 2.1V to 3.6V.               
+  * @param  Address: specifies the address to be programmed.
 
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @param  Data: specifies the data to be programmed.
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_ADDRESS(Address));
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    /* if the previous operation is completed, proceed to program the new data */
 
+    FLASH->CR &= CR_PSIZE_MASK;
 
+    FLASH->CR |= FLASH_PSIZE_HALF_WORD;
 
+    FLASH->CR |= FLASH_CR_PG;
 
+  
+    *(__IO uint16_t*)Address = Data;
 
+        
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+
 
+    /* if the program operation is completed, disable the PG Bit */
 
+    FLASH->CR &= (~FLASH_CR_PG);
 
+  } 
+  /* Return the Program Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Programs a byte (8-bit) at a specified address.
 
+  * @note   This function can be used within all the device supply voltage ranges.               
+  * @param  Address: specifies the address to be programmed.
 
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @param  Data: specifies the data to be programmed.
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_ADDRESS(Address));
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    /* if the previous operation is completed, proceed to program the new data */
 
+    FLASH->CR &= CR_PSIZE_MASK;
 
+    FLASH->CR |= FLASH_PSIZE_BYTE;
 
+    FLASH->CR |= FLASH_CR_PG;
 
+  
+    *(__IO uint8_t*)Address = Data;
 
+        
+    /* Wait for last operation to be completed */
 
+    status = FLASH_WaitForLastOperation();
 
+
 
+    /* if the program operation is completed, disable the PG Bit */
 
+    FLASH->CR &= (~FLASH_CR_PG);
 
+  } 
+
 
+  /* Return the Program Status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
 
+ *  @brief   Option Bytes Programming functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                        Option Bytes Programming functions
 
+ ===============================================================================  
+ 
+   This group includes the following functions:
 
+   - void FLASH_OB_Unlock(void)
 
+   - void FLASH_OB_Lock(void)
 
+   - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
 
+   - void FLASH_OB_RDPConfig(uint8_t OB_RDP)
 
+   - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 
+   - void FLASH_OB_BORConfig(uint8_t OB_BOR)
 
+   - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)							
+   - FLASH_Status FLASH_OB_Launch(void)
 
+   - uint32_t FLASH_OB_GetUser(void)						
+   - uint8_t FLASH_OB_GetWRP(void)						
+   - uint8_t FLASH_OB_GetRDP(void)							
+   - uint8_t FLASH_OB_GetBOR(void)
 
+   
+   Any operation of erase or program should follow these steps:
 
+   1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access
 
+
 
+   2. Call one or several functions to program the desired Option Bytes:
 
+      - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable 
+        the desired sector write protection
 
+      - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
 
+      - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure 
+        the user Option Bytes.
 
+      - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level 			 
+
 
+   3. Once all needed Option Bytes to be programmed are correctly written, call the
 
+      FLASH_OB_Launch() function to launch the Option Bytes programming process.
 
+     
+     @note When changing the IWDG mode from HW to SW or from SW to HW, a system 
+           reset is needed to make the change effective.  
+
 
+   4. Call the FLASH_OB_Lock() function to disable the FLASH option control register
 
+      access (recommended to protect the Option Bytes against possible unwanted operations)
 
+    
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Unlocks the FLASH Option Control Registers access.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_OB_Unlock(void)
 
+{
 
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
 
+  {
 
+    /* Authorizes the Option Byte register programming */
 
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
 
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Locks the FLASH Option Control Registers access.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void FLASH_OB_Lock(void)
 
+{
 
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
 
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the write protection of the desired sectors
 
+  * @param  OB_WRP: specifies the sector(s) to be write protected or unprotected.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11                      
+  *            @arg OB_WRP_Sector_All
 
+  * @param  Newstate: new state of the Write Protection.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None  
+  */
 
+void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
 
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_OB_WRP(OB_WRP));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  status = FLASH_WaitForLastOperation();
 
+
 
+  if(status == FLASH_COMPLETE)
 
+  { 
+    if(NewState != DISABLE)
 
+    {
 
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
 
+    }
 
+    else
 
+    {
 
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets the read protection level.
 
+  * @param  OB_RDP: specifies the read protection level.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg OB_RDP_Level_0: No protection
 
+  *            @arg OB_RDP_Level_1: Read protection of the memory
 
+  *            @arg OB_RDP_Level_2: Full chip protection
 
+  *   
+  * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
 
+  *    
+  * @retval None
 
+  */
 
+void FLASH_OB_RDPConfig(uint8_t OB_RDP)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_OB_RDP(OB_RDP));
 
+
 
+  status = FLASH_WaitForLastOperation();
 
+
 
+  if(status == FLASH_COMPLETE)
 
+  {
 
+    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
 
+
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+  * @param  OB_IWDG: Selects the IWDG mode
 
+  *          This parameter can be one of the following values:
 
+  *            @arg OB_IWDG_SW: Software IWDG selected
 
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
 
+  * @param  OB_STOP: Reset event when entering STOP mode.
 
+  *          This parameter  can be one of the following values:
 
+  *            @arg OB_STOP_NoRST: No reset generated when entering in STOP
 
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
 
+  * @param  OB_STDBY: Reset event when entering Standby mode.
 
+  *          This parameter  can be one of the following values:
 
+  *            @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
 
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
 
+  * @retval None
 
+  */
 
+void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 
+{
 
+  uint8_t optiontmp = 0xFF;
 
+  FLASH_Status status = FLASH_COMPLETE; 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
 
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
 
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+  
+  if(status == FLASH_COMPLETE)
 
+  { 
+    /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
 
+    optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); 
+
 
+    /* Update User Option Byte */
 
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Sets the BOR Level. 
+  * @param  OB_BOR: specifies the Option Bytes BOR Reset Level.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
 
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
 
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
 
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
 
+  * @retval None
 
+  */
 
+void FLASH_OB_BORConfig(uint8_t OB_BOR)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_OB_BOR(OB_BOR));
 
+
 
+  /* Set the BOR Level */
 
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
 
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
 
+
 
+}
 
+
 
+/**
 
+  * @brief  Launch the option byte loading.
 
+  * @param  None
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_OB_Launch(void)
 
+{
 
+  FLASH_Status status = FLASH_COMPLETE;
 
+
 
+  /* Set the OPTSTRT bit in OPTCR register */
 
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
 
+
 
+  /* Wait for last operation to be completed */
 
+  status = FLASH_WaitForLastOperation();
 
+
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the FLASH User Option Bytes values.
 
+  * @param  None
 
+  * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
 
+  *         and RST_STDBY(Bit2).
 
+  */
 
+uint8_t FLASH_OB_GetUser(void)
 
+{
 
+  /* Return the User Option Byte */
 
+  return (uint8_t)(FLASH->OPTCR >> 5);
 
+}
 
+
 
+/**
 
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
 
+  * @param  None
 
+  * @retval The FLASH Write Protection  Option Bytes value
 
+  */
 
+uint16_t FLASH_OB_GetWRP(void)
 
+{
 
+  /* Return the FLASH write protection Register value */
 
+  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
 
+}
 
+
 
+/**
 
+  * @brief  Returns the FLASH Read Protection level.
 
+  * @param  None
 
+  * @retval FLASH ReadOut Protection Status:
 
+  *           - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
 
+  *           - RESET, when OB_RDP_Level_0 is set
 
+  */
 
+FlagStatus FLASH_OB_GetRDP(void)
 
+{
 
+  FlagStatus readstatus = RESET;
 
+
 
+  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
 
+  {
 
+    readstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    readstatus = RESET;
 
+  }
 
+  return readstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the FLASH BOR level.
 
+  * @param  None
 
+  * @retval The FLASH BOR level:
 
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
 
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
 
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
 
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
+  */
 
+uint8_t FLASH_OB_GetBOR(void)
 
+{
 
+  /* Return the FLASH BOR level */
 
+  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified FLASH interrupts.
 
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg FLASH_IT_ERR: FLASH Error Interrupt
 
+  *            @arg FLASH_IT_EOP: FLASH end of operation Interrupt
 
+  * @retval None 
+  */
 
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if(NewState != DISABLE)
 
+  {
 
+    /* Enable the interrupt sources */
 
+    FLASH->CR |= FLASH_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the interrupt sources */
 
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified FLASH flag is set or not.
 
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
 
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
 
+  *            @arg FLASH_FLAG_BSY: FLASH Busy flag
 
+  * @retval The new state of FLASH_FLAG (SET or RESET).
 
+  */
 
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
 
+
 
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
 
+  return bitstatus; 
+}
 
+
 
+/**
 
+  * @brief  Clears the FLASH's pending flags.
 
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
 
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
 
+  * @retval None
 
+  */
 
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
 
+  
+  /* Clear the flags */
 
+  FLASH->SR = FLASH_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the FLASH Status.
 
+  * @param  None
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_GetStatus(void)
 
+{
 
+  FLASH_Status flashstatus = FLASH_COMPLETE;
 
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
 
+    flashstatus = FLASH_BUSY;
 
+  }
 
+  else 
+  {  
+    if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
 
+    { 
+      flashstatus = FLASH_ERROR_WRP;
 
+    }
 
+    else 
+    {
 
+      if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
 
+      {
 
+        flashstatus = FLASH_ERROR_PROGRAM; 
+      }
 
+      else
 
+      {
 
+        if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
 
+        {
 
+          flashstatus = FLASH_ERROR_OPERATION;
 
+        }
 
+        else
 
+        {
 
+          flashstatus = FLASH_COMPLETE;
 
+        }
 
+      }
 
+    }
 
+  }
 
+  /* Return the FLASH Status */
 
+  return flashstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Waits for a FLASH operation to complete.
 
+  * @param  None
 
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
 
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
 
+  */
 
+FLASH_Status FLASH_WaitForLastOperation(void)
 
+{ 
+  __IO FLASH_Status status = FLASH_COMPLETE;
 
+   
+  /* Check for the FLASH Status */
 
+  status = FLASH_GetStatus();
 
+
 
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
 
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
 
+     flag will be set */
 
+  while(status == FLASH_BUSY)
 
+  {
 
+    status = FLASH_GetStatus();
 
+  }
 
+  /* Return the operation status */
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 987 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_fsmc.c
Ver arquivo 

@@ -0,0 +1,987 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_fsmc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+ * @brief    This file provides firmware functions to manage the following 
+  *          functionalities of the FSMC peripheral:           
+  *           - Interface with SRAM, PSRAM, NOR and OneNAND memories
 
+  *           - Interface with NAND memories
 
+  *           - Interface with 16-bit PC Card compatible memories  
+  *           - Interrupts and flags management   
+  *           
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_fsmc.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* --------------------- FSMC registers bit mask ---------------------------- */
 
+/* FSMC BCRx Mask */
 
+#define BCR_MBKEN_SET          ((uint32_t)0x00000001)
 
+#define BCR_MBKEN_RESET        ((uint32_t)0x000FFFFE)
 
+#define BCR_FACCEN_SET         ((uint32_t)0x00000040)
 
+
 
+/* FSMC PCRx Mask */
 
+#define PCR_PBKEN_SET          ((uint32_t)0x00000004)
 
+#define PCR_PBKEN_RESET        ((uint32_t)0x000FFFFB)
 
+#define PCR_ECCEN_SET          ((uint32_t)0x00000040)
 
+#define PCR_ECCEN_RESET        ((uint32_t)0x000FFFBF)
 
+#define PCR_MEMORYTYPE_NAND    ((uint32_t)0x00000008)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup FSMC_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
 
+ *  @brief   NOR/SRAM Controller functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    NOR/SRAM Controller functions
 
+ ===============================================================================  
+
 
+ The following sequence should be followed to configure the FSMC to interface with
 
+ SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
 
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
 
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
 
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
 
+
 
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
 
+          GPIO_Init();    
+       
+   3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:
 
+          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
 
+      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
 
+      the structure member.
 
+      
+   4. Initialize the NOR/SRAM Controller by calling the function
 
+          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
 
+   5. Then enable the NOR/SRAM Bank, for example:
 
+          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);  
+
 
+   6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *   reset values.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval None
 
+  */
 
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
 
+{
 
+  /* Check the parameter */
 
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
 
+  
+  /* FSMC_Bank1_NORSRAM1 */
 
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
 
+  {
 
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
 
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
 
+  else
 
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
 
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
 
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
 
+
 
+/**
 
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
 
+  *         parameters in the FSMC_NORSRAMInitStruct.
 
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
 
+  *         that contains the configuration information for the FSMC NOR/SRAM 
+  *         specified Banks.                       
+  * @retval None
 
+  */
 
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
 
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
 
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
 
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
 
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
 
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
 
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
 
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
 
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
 
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
 
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
 
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
 
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
 
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
 
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
 
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
 
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
 
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
 
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
 
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
 
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
 
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
 
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
 
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
 
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
 
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
 
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
 
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
 
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
 
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
 
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
 
+  {
 
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
 
+  }
 
+  /* Bank1 NOR/SRAM timing register configuration */
 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
 
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
 
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
 
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
 
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
 
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
 
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
 
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
 
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
 
+  {
 
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
 
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
 
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
 
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
 
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
 
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
 
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
 
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
 
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
 
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
 
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
 
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
 
+  }
 
+  else
 
+  {
 
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
 
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
 
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
 
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
 
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
 
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
 
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
 
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
 
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
 
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
 
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
 
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
 
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
 
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
 
+{
 
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
 
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
 
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Group2 NAND Controller functions
 
+ *  @brief   NAND Controller functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    NAND Controller functions
 
+ ===============================================================================  
+
 
+ The following sequence should be followed to configure the FSMC to interface with
 
+ 8-bit or 16-bit NAND memory connected to the NAND Bank:
 
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
 
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
 
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
 
+
 
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
 
+          GPIO_Init();    
+       
+   3. Declare a FSMC_NANDInitTypeDef structure, for example:
 
+          FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;
 
+      and fill the FSMC_NANDInitStructure variable with the allowed values of
 
+      the structure member.
 
+      
+   4. Initialize the NAND Controller by calling the function
 
+          FSMC_NANDInit(&FSMC_NANDInitStructure); 
+
 
+   5. Then enable the NAND Bank, for example:
 
+          FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);  
+
 
+   6. At this stage you can read/write from/to the memory connected to the NAND Bank. 
+   
+@note To enable the Error Correction Code (ECC), you have to use the function
 
+          FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);  
+      and to get the current ECC value you have to use the function
 
+          ECCval = FSMC_GetECC(FSMC_Bank3_NAND); 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
+  * @retval None
 
+  */
 
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
 
+{
 
+  /* Check the parameter */
 
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
 
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    /* Set the FSMC_Bank2 registers to their reset values */
 
+    FSMC_Bank2->PCR2 = 0x00000018;
 
+    FSMC_Bank2->SR2 = 0x00000040;
 
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
 
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
+  }
 
+  /* FSMC_Bank3_NAND */  
+  else
 
+  {
 
+    /* Set the FSMC_Bank3 registers to their reset values */
 
+    FSMC_Bank3->PCR3 = 0x00000018;
 
+    FSMC_Bank3->SR3 = 0x00000040;
 
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
 
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Initializes the FSMC NAND Banks according to the specified parameters
 
+  *         in the FSMC_NANDInitStruct.
 
+  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
 
+  *         contains the configuration information for the FSMC NAND specified Banks.                       
+  * @retval None
 
+  */
 
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
 
+{
 
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
+    
+  /* Check the parameters */
 
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
 
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
 
+  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
 
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
 
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
 
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
 
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
 
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
 
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
 
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
 
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
 
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
 
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
 
+  
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
 
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
 
+            PCR_MEMORYTYPE_NAND |
 
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
 
+            FSMC_NANDInitStruct->FSMC_ECC |
 
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
 
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
 
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
 
+            
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
 
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
 
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
 
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
 
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
 
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
 
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
 
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
 
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
 
+  
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    /* FSMC_Bank2_NAND registers configuration */
 
+    FSMC_Bank2->PCR2 = tmppcr;
 
+    FSMC_Bank2->PMEM2 = tmppmem;
 
+    FSMC_Bank2->PATT2 = tmppatt;
 
+  }
 
+  else
 
+  {
 
+    /* FSMC_Bank3_NAND registers configuration */
 
+    FSMC_Bank3->PCR3 = tmppcr;
 
+    FSMC_Bank3->PMEM3 = tmppmem;
 
+    FSMC_Bank3->PATT3 = tmppatt;
 
+  }
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
 
+  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
 
+  *         will be initialized.
 
+  * @retval None
 
+  */
 
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
 
+{ 
+  /* Reset NAND Init structure parameters values */
 
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
 
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
 
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
 
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
 
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
 
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
 
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
 
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
 
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified NAND Memory Bank.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
 
+{
 
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
 
+    }
 
+    else
 
+    {
 
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
 
+    }
 
+    else
 
+    {
 
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
 
+    }
 
+  }
 
+}
 
+/**
 
+  * @brief  Enables or disables the FSMC NAND ECC feature.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  * @param  NewState: new state of the FSMC NAND ECC feature.  
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
 
+{
 
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
 
+    }
 
+    else
 
+    {
 
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
 
+    }
 
+    else
 
+    {
 
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the error correction code register value.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  * @retval The Error Correction Code (ECC) value.
 
+  */
 
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
 
+{
 
+  uint32_t eccval = 0x00000000;
 
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    /* Get the ECCR2 register value */
 
+    eccval = FSMC_Bank2->ECCR2;
 
+  }
 
+  else
 
+  {
 
+    /* Get the ECCR3 register value */
 
+    eccval = FSMC_Bank3->ECCR3;
 
+  }
 
+  /* Return the error correction code value */
 
+  return(eccval);
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Group3 PCCARD Controller functions
 
+ *  @brief   PCCARD Controller functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    PCCARD Controller functions
 
+ ===============================================================================  
+
 
+ The following sequence should be followed to configure the FSMC to interface with
 
+ 16-bit PC Card compatible memory connected to the PCCARD Bank:
 
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
 
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
 
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
 
+
 
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
 
+          GPIO_Init();    
+       
+   3. Declare a FSMC_PCCARDInitTypeDef structure, for example:
 
+          FSMC_PCCARDInitTypeDef  FSMC_PCCARDInitStructure;
 
+      and fill the FSMC_PCCARDInitStructure variable with the allowed values of
 
+      the structure member.
 
+      
+   4. Initialize the PCCARD Controller by calling the function
 
+          FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); 
+
 
+   5. Then enable the PCCARD Bank:
 
+          FSMC_PCCARDCmd(ENABLE);  
+
 
+   6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. 
+ 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
 
+  * @param  None                       
+  * @retval None
 
+  */
 
+void FSMC_PCCARDDeInit(void)
 
+{
 
+  /* Set the FSMC_Bank4 registers to their reset values */
 
+  FSMC_Bank4->PCR4 = 0x00000018; 
+  FSMC_Bank4->SR4 = 0x00000000;	
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
 
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
 
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified parameters
 
+  *         in the FSMC_PCCARDInitStruct.
 
+  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
 
+  *         that contains the configuration information for the FSMC PCCARD Bank.                       
+  * @retval None
 
+  */
 
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
 
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
 
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
 
+ 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
 
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
 
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
 
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
 
+  
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
 
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
 
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
 
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
 
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
 
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
 
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
 
+  
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
 
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
 
+                     FSMC_MemoryDataWidth_16b |  
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
 
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
 
+            
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
 
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
 
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
 
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
 
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
 
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
 
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
 
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
 
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
+            
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
 
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
 
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
 
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
 
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
+}
 
+
 
+/**
 
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
 
+  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
 
+{
 
+  /* Reset PCCARD Init structure parameters values */
 
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
 
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
 
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
 
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
 
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the PCCARD Memory Bank.
 
+  * @param  NewState: new state of the PCCARD Memory Bank.  
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FSMC_PCCARDCmd(FunctionalState NewState)
 
+{
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
 
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
 
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup FSMC_Group4  Interrupts and flags management functions
 
+ *  @brief    Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                     Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified FSMC interrupts.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
 
+  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
 
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
 
+  * @param  NewState: new state of the specified FSMC interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
 
+{
 
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
 
+  assert_param(IS_FSMC_IT(FSMC_IT));	
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected FSMC_Bank2 interrupts */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      FSMC_Bank2->SR2 |= FSMC_IT;
 
+    }
 
+    /* Enable the selected FSMC_Bank3 interrupts */
 
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
 
+    {
 
+      FSMC_Bank3->SR3 |= FSMC_IT;
 
+    }
 
+    /* Enable the selected FSMC_Bank4 interrupts */
 
+    else
 
+    {
 
+      FSMC_Bank4->SR4 |= FSMC_IT;    
+    }
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected FSMC_Bank2 interrupts */
 
+    if(FSMC_Bank == FSMC_Bank2_NAND)
 
+    {
 
+      
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
 
+    }
 
+    /* Disable the selected FSMC_Bank3 interrupts */
 
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
 
+    {
 
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
 
+    }
 
+    /* Disable the selected FSMC_Bank4 interrupts */
 
+    else
 
+    {
 
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified FSMC flag is set or not.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
 
+  * @param  FSMC_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
 
+  *            @arg FSMC_FLAG_Level: Level detection Flag.
 
+  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
 
+  *            @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
+  * @retval The new state of FSMC_FLAG (SET or RESET).
 
+  */
 
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  uint32_t tmpsr = 0x00000000;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
 
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
 
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    tmpsr = FSMC_Bank2->SR2;
 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
 
+  {
 
+    tmpsr = FSMC_Bank3->SR3;
 
+  }
 
+  /* FSMC_Bank4_PCCARD*/
 
+  else
 
+  {
 
+    tmpsr = FSMC_Bank4->SR4;
 
+  } 
+  
+  /* Get the flag status */
 
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the flag status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the FSMC's pending flags.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
 
+  * @param  FSMC_FLAG: specifies the flag to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
 
+  *            @arg FSMC_FLAG_Level: Level detection Flag.
 
+  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
 
+  * @retval None
 
+  */
 
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 
+{
 
+ /* Check the parameters */
 
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
 
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
 
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
 
+  {
 
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
 
+  }
 
+  /* FSMC_Bank4_PCCARD*/
 
+  else
 
+  {
 
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
 
+  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
 
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
+  * @retval The new state of FSMC_IT (SET or RESET).
 
+  */
 
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
 
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
 
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    tmpsr = FSMC_Bank2->SR2;
 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
 
+  {
 
+    tmpsr = FSMC_Bank3->SR3;
 
+  }
 
+  /* FSMC_Bank4_PCCARD*/
 
+  else
 
+  {
 
+    tmpsr = FSMC_Bank4->SR4;
 
+  } 
+  
+  itstatus = tmpsr & FSMC_IT;
 
+  
+  itenable = tmpsr & (FSMC_IT >> 3);
 
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus; 
+}
 
+
 
+/**
 
+  * @brief  Clears the FSMC's interrupt pending bits.
 
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
 
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
 
+  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
 
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
 
+  * @retval None
 
+  */
 
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
 
+  assert_param(IS_FSMC_IT(FSMC_IT));
 
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
 
+  {
 
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
 
+  {
 
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
 
+  }
 
+  /* FSMC_Bank4_PCCARD*/
 
+  else
 
+  {
 
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 567 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_gpio.c
Ver arquivo 

@@ -0,0 +1,567 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_gpio.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:           
+  *           - Initialization and Configuration
 
+  *           - GPIO Read and Write
 
+  *           - GPIO Alternate functions configuration
 
+  * 
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================       
+  *           1. Enable the GPIO AHB clock using the following function
 
+  *                RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
 
+  *             
+  *           2. Configure the GPIO pin(s) using GPIO_Init()
 
+  *              Four possible configuration are available for each pin:
 
+  *                - Input: Floating, Pull-up, Pull-down.
 
+  *                - Output: Push-Pull (Pull-up, Pull-down or no Pull)
 
+  *                          Open Drain (Pull-up, Pull-down or no Pull).
 
+  *                  In output mode, the speed is configurable: 2 MHz, 25 MHz,
 
+  *                  50 MHz or 100 MHz.
 
+  *                - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
 
+  *                                      Open Drain (Pull-up, Pull-down or no Pull).
 
+  *                - Analog: required mode when a pin is to be used as ADC channel
 
+  *                          or DAC output.
 
+  * 
+  *          3- Peripherals alternate function:
 
+  *              - For ADC and DAC, configure the desired pin in analog mode using 
+  *                  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
 
+  *              - For other peripherals (TIM, USART...):
 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
 
+  *                 - Configure the desired pin in alternate function mode using
 
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
 
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
 
+  *                 - Call GPIO_Init() function
 
+  *        
+  *          4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
 
+  *          
+  *          5. To set/reset the level of a pin configured in output mode use
 
+  *             GPIO_SetBits()/GPIO_ResetBits()
 
+  *               
+  *          6. During and just after reset, the alternate functions are not 
+  *             active and the GPIO pins are configured in input floating mode
 
+  *             (except JTAG pins).
 
+  *
 
+  *          7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
+  *             general-purpose (PC14 and PC15, respectively) when the LSE
 
+  *             oscillator is off. The LSE has priority over the GPIO function.
 
+  *
 
+  *          8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+  *             general-purpose PH0 and PH1, respectively, when the HSE 
+  *             oscillator is off. The HSE has priority over the GPIO function.
 
+  *             
+  *  @endverbatim        
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_gpio.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup GPIO_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup GPIO_Group1 Initialization and Configuration
 
+ *  @brief   Initialization and Configuration
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                        Initialization and Configuration
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
 
+  * @note   By default, The GPIO pins are configured in input floating mode (except JTAG pins).
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @retval None
 
+  */
 
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+
 
+  if (GPIOx == GPIOA)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOB)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOC)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOD)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOE)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOF)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOG)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
 
+  }
 
+  else if (GPIOx == GPIOH)
 
+  {
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
 
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
 
+  }
 
+  else
 
+  {
 
+    if (GPIOx == GPIOI)
 
+    {
 
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
 
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
 
+  *         the configuration information for the specified GPIO peripheral.
 
+  * @retval None
 
+  */
 
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
 
+{
 
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
 
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
 
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
 
+
 
+  /* -------------------------Configure the port pins---------------- */
 
+  /*-- GPIO Mode Configuration --*/
 
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
 
+  {
 
+    pos = ((uint32_t)0x01) << pinpos;
 
+    /* Get the port pins position */
 
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
 
+
 
+    if (currentpin == pos)
 
+    {
 
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
 
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
 
+
 
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
 
+      {
 
+        /* Check Speed mode parameters */
 
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
 
+
 
+        /* Speed mode configuration */
 
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
 
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
 
+
 
+        /* Check Output mode parameters */
 
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
 
+
 
+        /* Output mode configuration*/
 
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
 
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
 
+      }
 
+
 
+      /* Pull-up Pull down resistor configuration*/
 
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
 
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Fills each GPIO_InitStruct member with its default value.
 
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
 
+{
 
+  /* Reset GPIO init structure parameters values */
 
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
 
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
 
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
 
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
 
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
 
+}
 
+
 
+/**
 
+  * @brief  Locks GPIO Pins configuration registers.
 
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
 
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
 
+  * @note   The configuration of the locked GPIO pins can no longer be modified
 
+  *         until the next reset.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bit to be locked.
 
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 
+  * @retval None
 
+  */
 
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  __IO uint32_t tmp = 0x00010000;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
 
+
 
+  tmp |= GPIO_Pin;
 
+  /* Set LCKK bit */
 
+  GPIOx->LCKR = tmp;
 
+  /* Reset LCKK bit */
 
+  GPIOx->LCKR =  GPIO_Pin;
 
+  /* Set LCKK bit */
 
+  GPIOx->LCKR = tmp;
 
+  /* Read LCKK bit*/
 
+  tmp = GPIOx->LCKR;
 
+  /* Read LCKK bit*/
 
+  tmp = GPIOx->LCKR;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup GPIO_Group2 GPIO Read and Write
 
+ *  @brief   GPIO Read and Write
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                              GPIO Read and Write
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Reads the specified input port pin.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bit to read.
 
+  *         This parameter can be GPIO_Pin_x where x can be (0..15).
 
+  * @retval The input port pin value.
 
+  */
 
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  uint8_t bitstatus = 0x00;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 
+
 
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
 
+  {
 
+    bitstatus = (uint8_t)Bit_SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = (uint8_t)Bit_RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Reads the specified GPIO input data port.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @retval GPIO input data port value.
 
+  */
 
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+
 
+  return ((uint16_t)GPIOx->IDR);
 
+}
 
+
 
+/**
 
+  * @brief  Reads the specified output data port bit.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bit to read.
 
+  *          This parameter can be GPIO_Pin_x where x can be (0..15).
 
+  * @retval The output port pin value.
 
+  */
 
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  uint8_t bitstatus = 0x00;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 
+
 
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
 
+  {
 
+    bitstatus = (uint8_t)Bit_SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = (uint8_t)Bit_RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Reads the specified GPIO output data port.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @retval GPIO output data port value.
 
+  */
 
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+
 
+  return ((uint16_t)GPIOx->ODR);
 
+}
 
+
 
+/**
 
+  * @brief  Sets the selected data port bits.
 
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
 
+  *         the read and the modify access.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bits to be written.
 
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 
+  * @retval None
 
+  */
 
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
 
+
 
+  GPIOx->BSRRL = GPIO_Pin;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the selected data port bits.
 
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
 
+  *         the read and the modify access.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bits to be written.
 
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 
+  * @retval None
 
+  */
 
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
 
+
 
+  GPIOx->BSRRH = GPIO_Pin;
 
+}
 
+
 
+/**
 
+  * @brief  Sets or clears the selected data port bit.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: specifies the port bit to be written.
 
+  *          This parameter can be one of GPIO_Pin_x where x can be (0..15).
 
+  * @param  BitVal: specifies the value to be written to the selected bit.
 
+  *          This parameter can be one of the BitAction enum values:
 
+  *            @arg Bit_RESET: to clear the port pin
 
+  *            @arg Bit_SET: to set the port pin
 
+  * @retval None
 
+  */
 
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
 
+
 
+  if (BitVal != Bit_RESET)
 
+  {
 
+    GPIOx->BSRRL = GPIO_Pin;
 
+  }
 
+  else
 
+  {
 
+    GPIOx->BSRRH = GPIO_Pin ;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Writes data to the specified GPIO data port.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  PortVal: specifies the value to be written to the port output data register.
 
+  * @retval None
 
+  */
 
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+
 
+  GPIOx->ODR = PortVal;
 
+}
 
+
 
+/**
 
+  * @brief  Toggles the specified GPIO pins..
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
 
+  * @retval None
 
+  */
 
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+
 
+  GPIOx->ODR ^= GPIO_Pin;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
 
+ *  @brief   GPIO Alternate functions configuration function
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+               GPIO Alternate functions configuration function
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Changes the mapping of the specified pin.
 
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
 
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
 
+  *         This parameter can be GPIO_PinSourcex where x can be (0..15).
 
+  * @param  GPIO_AFSelection: selects the pin to used as Alternate function.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) 
+  *            @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) 
+  *            @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
 
+  *            @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
 
+  *            @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
 
+  *            @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
 
+  *            @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
 
+  *            @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
 
+  *            @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
 
+  *            @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
 
+  *            @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
 
+  *            @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
 
+  *            @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
 
+  *            @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
 
+  *            @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
 
+  *            @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
 
+  *            @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
 
+  *            @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
 
+  *            @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
 
+  *            @arg GPIO_AF_USART1: Connect USART1 pins to AF7
 
+  *            @arg GPIO_AF_USART2: Connect USART2 pins to AF7
 
+  *            @arg GPIO_AF_USART3: Connect USART3 pins to AF7
 
+  *            @arg GPIO_AF_UART4: Connect UART4 pins to AF8
 
+  *            @arg GPIO_AF_UART5: Connect UART5 pins to AF8
 
+  *            @arg GPIO_AF_USART6: Connect USART6 pins to AF8
 
+  *            @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
 
+  *            @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
 
+  *            @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
 
+  *            @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
 
+  *            @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
 
+  *            @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
 
+  *            @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
 
+  *            @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
 
+  *            @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
 
+  *            @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
 
+  *            @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
 
+  *            @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
 
+  *            @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
 
+  * @retval None
 
+  */
 
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 
+{
 
+  uint32_t temp = 0x00;
 
+  uint32_t temp_2 = 0x00;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
 
+  assert_param(IS_GPIO_AF(GPIO_AF));
 
+  
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
 
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
 
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
 
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 706 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_hash.c
Ver arquivo 

@@ -0,0 +1,706 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_hash.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the HASH / HMAC Processor (HASH) peripheral:           
+  *           - Initialization and Configuration functions
 
+  *           - Message Digest generation functions
 
+  *           - context swapping functions   
+  *           - DMA interface function       
+  *           - Interrupts and flags management       
+  *         
+  *  @verbatim
 
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          HASH operation : 
+  *          ----------------                   
+  *         1. Enable the HASH controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
 
+  *           
+  *         2. Initialise the HASH using HASH_Init() function. 
+  *               
+  *         3 . Reset the HASH processor core, so that the HASH will be ready 
+  *             to compute he message digest of a new message by using 
+  *             HASH_Reset() function.
 
+  *
 
+  *         4. Enable the HASH controller using the HASH_Cmd() function. 
+  *                
+  *         5. if using DMA for Data input transfer, Activate the DMA Request 
+  *            using HASH_DMACmd() function 
+  *                    
+  *         6. if DMA is not used for data transfer, use HASH_DataIn() function 
+  *            to enter data to IN FIFO.
 
+  *             
+  *          
+  *         7. Configure the Number of valid bits in last word of the message 
+  *            using HASH_SetLastWordValidBitsNbr() function.
 
+  *             
+  *         8. if the message length is not an exact multiple of 512 bits, 
+  *            then the function HASH_StartDigest() must be called to 
+  *            launch the computation of the final digest.     
+  *             
+  *         9. Once computed, the digest can be read using HASH_GetDigest() 
+  *            function.         
+  *                   
+  *        10. To control HASH events you can use one of the following 
+  *              two methods:
 
+  *               a- Check on HASH flags using the HASH_GetFlagStatus() function.  
+  *               b- Use HASH interrupts through the function HASH_ITConfig() at 
+  *                  initialization phase and HASH_GetITStatus() function into 
+  *                  interrupt routines in hashing phase.
 
+  *          After checking on a flag you should clear it using HASH_ClearFlag()
 
+  *          function. And after checking on an interrupt event you should 
+  *          clear it using HASH_ClearITPendingBit() function.     
+  *                     
+  *        11. Save and restore hash processor context using 
+  *            HASH_SaveContext() and HASH_RestoreContext() functions.     
+  *              
+  *
 
+  *            
+  *          HMAC operation : 
+  *          ----------------  
+  *          The HMAC algorithm is used for message authentication, by 
+  *          irreversibly binding the message being processed to a key chosen 
+  *          by the user. 
+  *          For HMAC specifications, refer to "HMAC: keyed-hashing for message 
+  *          authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
 
+  *          
+  *          Basically, the HMAC algorithm consists of two nested hash operations:
 
+  *          HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
 
+  *          where:
 
+  *          - "pad" is a sequence of zeroes needed to extend the key to the 
+  *                  length of the underlying hash function data block (that is 
+  *                  512 bits for both the SHA-1 and MD5 hash algorithms)
 
+  *          - "|"   represents the concatenation operator 
+  *          
+  *         
+  *         To compute the HMAC, four different phases are required:
 
+  *                    
+  *         1.  Initialise the HASH using HASH_Init() function to do HMAC 
+  *             operation. 
+  *                
+  *         2.  The key (to be used for the inner hash function) is then given 
+  *             to the core. This operation follows the same mechanism as the 
+  *             one used to send the message in the hash operation (that is, 
+  *             by HASH_DataIn() function and, finally, 
+  *             HASH_StartDigest() function.
 
+  *          
+  *         3.  Once the last word has been entered and computation has started, 
+  *             the hash processor elaborates the key. It is then ready to 
+  *             accept the message text using the same mechanism as the one 
+  *             used to send the message in the hash operation.
 
+  *       
+  *         4.  After the first hash round, the hash processor returns "ready" 
+  *             to indicate that it is ready to receive the key to be used for 
+  *             the outer hash function (normally, this key is the same as the 
+  *             one used for the inner hash function). When the last word of 
+  *             the key is entered and computation starts, the HMAC result is 
+  *             made available using HASH_GetDigest() function.
 
+  *               
+  *              
+  *  @endverbatim
 
+  *         
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_hash.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup HASH 
+  * @brief HASH driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/ 
+
 
+/** @defgroup HASH_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup HASH_Group1 Initialization and Configuration functions
 
+ *  @brief    Initialization and Configuration functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Initialization and Configuration functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the HASH peripheral
 
+   - Configure the HASH Processor 
+      - MD5/SHA1, 
+      - HASH/HMAC, 
+      - datatype 
+      - HMAC Key (if mode = HMAC)
 
+   - Reset the HASH Processor 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Deinitializes the HASH peripheral registers to their default reset values
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void HASH_DeInit(void)
 
+{
 
+  /* Enable HASH reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
 
+  /* Release HASH from reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the HASH peripheral according to the specified parameters
 
+  *         in the HASH_InitStruct structure.
 
+  * @note   the hash processor is reset when calling this function so that the
 
+  *         HASH will be ready to compute the message digest of a new message.
 
+  *         There is no need to call HASH_Reset() function.           
+  * @param  HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
 
+  *         the configuration information for the HASH peripheral.
 
+  * @note   The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only 
+  *          if the algorithm mode is HMAC.       
+  * @retval None
 
+  */
 
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
 
+  assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
 
+  assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
 
+  
+  /* Configure the Algorithm used, algorithm mode and the datatype */
 
+  HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
 
+  HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
 
+               HASH_InitStruct->HASH_DataType | \
 
+               HASH_InitStruct->HASH_AlgoMode);
 
+  
+  /* if algorithm mode is HMAC, set the Key */  
+  if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) 
+  {
 
+    assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
 
+    HASH->CR &= ~HASH_CR_LKEY;
 
+    HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
 
+  }
 
+
 
+  /* Reset the HASH processor core, so that the HASH will be ready to compute 
+     the message digest of a new message */
 
+  HASH->CR |= HASH_CR_INIT;  
+}
 
+
 
+/**
 
+  * @brief  Fills each HASH_InitStruct member with its default value.
 
+  * @param  HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
 
+  *          be initialized.  
+  *  @note  The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
 
+  *          Data type selected is 32b and HMAC Key Type is short key.  
+  * @retval None
 
+  */
 
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
 
+{
 
+  /* Initialize the HASH_AlgoSelection member */
 
+  HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
 
+
 
+  /* Initialize the HASH_AlgoMode member */
 
+  HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
 
+
 
+  /* Initialize the HASH_DataType member */
 
+  HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
 
+
 
+  /* Initialize the HASH_HMACKeyType member */
 
+  HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
 
+}
 
+
 
+/**
 
+  * @brief  Resets the HASH processor core, so that the HASH will be ready
 
+  *         to compute the message digest of a new message.
 
+  * @note   Calling this function will clear the HASH_SR_DCIS (Digest calculation 
+  *         completion interrupt status) bit corresponding to HASH_IT_DCI 
+  *         interrupt and HASH_FLAG_DCIS flag. 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void HASH_Reset(void)
 
+{
 
+  /* Reset the HASH processor core */
 
+  HASH->CR |= HASH_CR_INIT;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+ 
+/** @defgroup HASH_Group2 Message Digest generation functions
 
+ *  @brief    Message Digest generation functions
 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Message Digest generation functions
 
+ ===============================================================================  
+  This section provides functions allowing the generation of message digest: 
+  - Push data in the IN FIFO : using HASH_DataIn()
 
+  - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()  
+  - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() 
+  - start digest calculation : using HASH_StartDigest()
 
+  - Get the Digest message : using HASH_GetDigest()
 
+ 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+
 
+/**
 
+  * @brief  Configure the Number of valid bits in last word of the message
 
+  * @param  ValidNumber: Number of valid bits in last word of the message.
 
+  *           This parameter must be a number between 0 and 0x1F.
 
+  *             - 0x00: All 32 bits of the last data written are valid
 
+  *             - 0x01: Only bit [0] of the last data written is valid
 
+  *             - 0x02: Only bits[1:0] of the last data written are valid
 
+  *             - 0x03: Only bits[2:0] of the last data written are valid
 
+  *             - ...
 
+  *             - 0x1F: Only bits[30:0] of the last data written are valid    
+  * @note   The Number of valid bits must be set before to start the message 
+  *         digest competition (in Hash and HMAC) and key treatment(in HMAC).    
+  * @retval None
 
+  */
 
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
 
+  
+  /* Configure the Number of valid bits in last word of the message */
 
+  HASH->STR &= ~(HASH_STR_NBW);
 
+  HASH->STR |= ValidNumber;
 
+}
 
+
 
+/**
 
+  * @brief  Writes data in the Data Input FIFO
 
+  * @param  Data: new data of the message to be processed.
 
+  * @retval None
 
+  */
 
+void HASH_DataIn(uint32_t Data)
 
+{
 
+  /* Write in the DIN register a new data */
 
+  HASH->DIN = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the number of words already pushed into the IN FIFO.
 
+  * @param  None
 
+  * @retval The value of words already pushed into the IN FIFO.
 
+  */
 
+uint8_t HASH_GetInFIFOWordsNbr(void)
 
+{
 
+  /* Return the value of NBW bits */
 
+  return ((HASH->CR & HASH_CR_NBW) >> 8);
 
+}
 
+
 
+/**
 
+  * @brief  Provides the message digest result.
 
+  * @note   In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used
 
+  *         and is read as zero.  
+  * @param  HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will 
+  *         hold the message digest result 
+  * @retval None
 
+  */
 
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
 
+{
 
+  /* Get the data field */
 
+  HASH_MessageDigest->Data[0] = HASH->HR[0];
 
+  HASH_MessageDigest->Data[1] = HASH->HR[1];
 
+  HASH_MessageDigest->Data[2] = HASH->HR[2];
 
+  HASH_MessageDigest->Data[3] = HASH->HR[3];
 
+  HASH_MessageDigest->Data[4] = HASH->HR[4];
 
+}
 
+
 
+/**
 
+  * @brief  Starts the message padding and calculation of the final message     
+  * @param  None
 
+  * @retval None
 
+  */
 
+void HASH_StartDigest(void)
 
+{
 
+  /* Start the Digest calculation */
 
+  HASH->STR |= HASH_STR_DCAL;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_Group3 Context swapping functions
 
+ *  @brief   Context swapping functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                             Context swapping functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to save and store HASH Context
 
+  
+  It is possible to interrupt a HASH/HMAC process to perform another processing 
+  with a higher priority, and to complete the interrupted process later on, when 
+  the higher priority task is complete. To do so, the context of the interrupted 
+  task must be saved from the HASH registers to memory, and then be restored 
+  from memory to the HASH registers.
 
+  
+  1. To save the current context, use HASH_SaveContext() function
 
+  2. To restore the saved context, use HASH_RestoreContext() function 
+  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Save the Hash peripheral Context. 
+  * @note   The context can be saved only when no block is currently being 
+  *         processed. So user must wait for DINIS = 1 (the last block has been 
+  *         processed and the input FIFO is empty) or NBW != 0 (the FIFO is not 
+  *         full and no processing is ongoing).   
+  * @param  HASH_ContextSave: pointer to a HASH_Context structure that contains
 
+  *         the repository for current context.
 
+  * @retval None
 
+  */
 
+void HASH_SaveContext(HASH_Context* HASH_ContextSave)
 
+{
 
+  uint8_t i = 0;
 
+  
+  /* save context registers */
 
+  HASH_ContextSave->HASH_IMR = HASH->IMR;  
+  HASH_ContextSave->HASH_STR = HASH->STR;      
+  HASH_ContextSave->HASH_CR  = HASH->CR;     
+  for(i=0; i<=50;i++)
 
+  {
 
+     HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
 
+  }   
+}
 
+
 
+/**
 
+  * @brief  Restore the Hash peripheral Context.  
+  * @note   After calling this function, user can restart the processing from the
 
+  *         point where it has been interrupted.  
+  * @param  HASH_ContextRestore: pointer to a HASH_Context structure that contains
 
+  *         the repository for saved context.
 
+  * @retval None
 
+  */
 
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)  
+{
 
+  uint8_t i = 0;
 
+  
+  /* restore context registers */
 
+  HASH->IMR = HASH_ContextRestore->HASH_IMR;   
+  HASH->STR = HASH_ContextRestore->HASH_STR;     
+  HASH->CR = HASH_ContextRestore->HASH_CR;
 
+  
+  /* Initialize the hash processor */
 
+  HASH->CR |= HASH_CR_INIT; 
+  
+   /* continue restoring context registers */     
+  for(i=0; i<=50;i++)
 
+  {
 
+     HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
 
+  }   
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
 
+ *  @brief   HASH's DMA interface Configuration function 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   HASH's DMA interface Configuration function
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the DMA interface for 
+  HASH/ HMAC data input transfer.
 
+   
+  When the DMA mode is enabled (using the HASH_DMACmd() function), data can be 
+  sent to the IN FIFO using the DMA peripheral.
 
+
 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Enables or disables the HASH DMA interface.
 
+  * @note   The DMA is disabled by hardware after the end of transfer.
 
+  * @param  NewState: new state of the selected HASH DMA transfer request.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void HASH_DMACmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the HASH DMA request */
 
+    HASH->CR |= HASH_CR_DMAE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the HASH DMA request */
 
+    HASH->CR &= ~HASH_CR_DMAE;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup HASH_Group5 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the HASH Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
 
+  
+  The HASH provides 2 Interrupts sources and 5 Flags:
 
+  
+  Flags :
 
+  ---------- 
+     1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO 
+                          which means that a  new block (512 bit) can be entered 
+                          into the input buffer.
 
+                          
+     2. HASH_FLAG_DCIS :  set when Digest calculation is complete
 
+      
+     3. HASH_FLAG_DMAS :  set when HASH's DMA interface is enabled (DMAE=1) or 
+                          a transfer is ongoing.
 
+                          This Flag is cleared only by hardware.
 
+                           
+     4. HASH_FLAG_BUSY :  set when The hash core is processing a block of data
 
+                          This Flag is cleared only by hardware. 
+                           
+     5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that 
+                          the Data IN FIFO contains at least one word of data.
 
+                          This Flag is cleared only by hardware.
 
+     
+  Interrupts :
 
+  ------------
 
+    
+   1. HASH_IT_DINI  : if enabled, this interrupt source is pending when 16 
+                      locations are free in the Data IN FIFO  which means that 
+                      a new block (512 bit) can be entered into the input buffer.
 
+                      This interrupt source is cleared using 
+                      HASH_ClearITPendingBit(HASH_IT_DINI) function.
 
+   
+   2. HASH_IT_DCI   : if enabled, this interrupt source is pending when Digest 
+                      calculation is complete.
 
+                      This interrupt source is cleared using 
+                      HASH_ClearITPendingBit(HASH_IT_DCI) function.
 
+
 
+  Managing the HASH controller events :
 
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the HASH controller events: Polling mode or Interrupt mode.
 
+  
+  1.  In the Polling Mode it is advised to use the following functions:
 
+      - HASH_GetFlagStatus() : to check if flags events occur. 
+      - HASH_ClearFlag()     : to clear the flags events.
 
+    
+  2.  In the Interrupt Mode it is advised to use the following functions:
 
+      - HASH_ITConfig()       : to enable or disable the interrupt source.
 
+      - HASH_GetITStatus()    : to check if Interrupt occurs.
 
+      - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                (corresponding Flag). 
+
 
+@endverbatim
 
+  * @{
 
+  */ 
+  
+/**
 
+  * @brief  Enables or disables the specified HASH interrupts.
 
+  * @param  HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg HASH_IT_DINI: Data Input interrupt
 
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
 
+  * @param  NewState: new state of the specified HASH interrupt.
 
+  *           This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_IT(HASH_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected HASH interrupt */
 
+    HASH->IMR |= HASH_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected HASH interrupt */
 
+    HASH->IMR &= (uint8_t) ~HASH_IT;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified HASH flag is set or not.
 
+  * @param  HASH_FLAG: specifies the HASH flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg HASH_FLAG_DINIS: Data input interrupt status flag
 
+  *            @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
 
+  *            @arg HASH_FLAG_BUSY: Busy flag
 
+  *            @arg HASH_FLAG_DMAS: DMAS Status flag
 
+  *            @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
 
+  * @retval The new state of HASH_FLAG (SET or RESET)
 
+  */
 
+FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  uint32_t tempreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
 
+
 
+  /* check if the FLAG is in CR register */
 
+  if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) 
+  {
 
+    tempreg = HASH->CR;
 
+  }
 
+  else /* The FLAG is in SR register */
 
+  {
 
+    tempreg = HASH->SR;
 
+  }
 
+
 
+  /* Check the status of the specified HASH flag */
 
+  if ((tempreg & HASH_FLAG) != (uint16_t)RESET)
 
+  {
 
+    /* HASH is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* HASH_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+
 
+  /* Return the HASH_FLAG status */
 
+  return  bitstatus;
 
+}
 
+/**
 
+  * @brief  Clears the HASH flags.
 
+  * @param  HASH_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg HASH_FLAG_DINIS: Data Input Flag
 
+  *            @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag                       
+  * @retval None
 
+  */
 
+void HASH_ClearFlag(uint16_t HASH_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
 
+  
+  /* Clear the selected HASH flags */
 
+  HASH->SR = ~(uint32_t)HASH_FLAG;
 
+}
 
+/**
 
+  * @brief  Checks whether the specified HASH interrupt has occurred or not.
 
+  * @param  HASH_IT: specifies the HASH interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg HASH_IT_DINI: Data Input interrupt
 
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
 
+  * @retval The new state of HASH_IT (SET or RESET).
 
+  */
 
+ITStatus HASH_GetITStatus(uint8_t HASH_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_GET_IT(HASH_IT));  
+
 
+
 
+  /* Check the status of the specified HASH interrupt */
 
+  tmpreg =  HASH->SR;
 
+
 
+  if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
 
+  {
 
+    /* HASH_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* HASH_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the HASH_IT status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the HASH interrupt pending bit(s).
 
+  * @param  HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg HASH_IT_DINI: Data Input interrupt
 
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
 
+  * @retval None
 
+  */
 
+void HASH_ClearITPendingBit(uint8_t HASH_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_HASH_IT(HASH_IT));
 
+
 
+  /* Clear the selected HASH interrupt pending bit */
 
+  HASH->SR = (uint8_t)~HASH_IT;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 320 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_hash_md5.c
Ver arquivo 

@@ -0,0 +1,320 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_hash_md5.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides high level functions to compute the HASH MD5 and
 
+  *          HMAC MD5 Digest of an input message.
 
+  *          It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
 
+  *          peripheral.
 
+  *
 
+  *  @verbatim
 
+  *    
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable The HASH controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
 
+  *
 
+  *          2. Calculate the HASH MD5 Digest using HASH_MD5() function.
 
+  *
 
+  *          3. Calculate the HMAC MD5 Digest using HMAC_MD5() function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_hash.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup HASH 
+  * @brief HASH driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define MD5BUSY_TIMEOUT    ((uint32_t) 0x00010000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup HASH_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup HASH_Group7 High Level MD5 functions
 
+ *  @brief   High Level MD5 Hash and HMAC functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          High Level MD5 Hash and HMAC functions
 
+ ===============================================================================
 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Compute the HASH MD5 digest.
 
+  * @param  Input: pointer to the Input buffer to be treated.
 
+  * @param  Ilen: length of the Input buffer.
 
+  * @param  Output: the returned digest
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: digest computation done
 
+  *          - ERROR: digest computation failed
 
+  */
 
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 
+{
 
+  HASH_InitTypeDef MD5_HASH_InitStructure;
 
+  HASH_MsgDigest MD5_MessageDigest;
 
+  __IO uint16_t nbvalidbitsdata = 0;
 
+  uint32_t i = 0;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+
 
+
 
+  /* Number of valid bits in last word of the Input data */
 
+  nbvalidbitsdata = 8 * (Ilen % 4);
 
+
 
+  /* HASH peripheral initialization */
 
+  HASH_DeInit();
 
+
 
+  /* HASH Configuration */
 
+  MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
 
+  MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
 
+  MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
 
+  HASH_Init(&MD5_HASH_InitStructure);
 
+
 
+  /* Configure the number of valid bits in last word of the data */
 
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
 
+
 
+  /* Write the Input block in the IN FIFO */
 
+  for(i=0; i<Ilen; i+=4)
 
+  {
 
+    HASH_DataIn(*(uint32_t*)inputaddr);
 
+    inputaddr+=4;
 
+  }
 
+
 
+  /* Start the HASH processor */
 
+  HASH_StartDigest();
 
+
 
+  /* wait until the Busy flag is RESET */
 
+  do
 
+  {
 
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+    counter++;
 
+  }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+  if (busystatus != RESET)
 
+  {
 
+     status = ERROR;
 
+  }
 
+  else
 
+  {
 
+    /* Read the message digest */
 
+    HASH_GetDigest(&MD5_MessageDigest);
 
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[0]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[1]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[2]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[3]);
 
+  }
 
+  return status; 
+}
 
+
 
+/**
 
+  * @brief  Compute the HMAC MD5 digest.
 
+  * @param  Key: pointer to the Key used for HMAC.
 
+  * @param  Keylen: length of the Key used for HMAC.
 
+  * @param  Input: pointer to the Input buffer to be treated.
 
+  * @param  Ilen: length of the Input buffer.
 
+  * @param  Output: the returned digest  
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: digest computation done
 
+  *          - ERROR: digest computation failed
 
+  */
 
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, 
+                     uint32_t Ilen, uint8_t Output[16])
 
+{
 
+  HASH_InitTypeDef MD5_HASH_InitStructure;
 
+  HASH_MsgDigest MD5_MessageDigest;
 
+  __IO uint16_t nbvalidbitsdata = 0;
 
+  __IO uint16_t nbvalidbitskey = 0;
 
+  uint32_t i = 0;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+
 
+  /* Number of valid bits in last word of the Input data */
 
+  nbvalidbitsdata = 8 * (Ilen % 4);
 
+
 
+  /* Number of valid bits in last word of the Key */
 
+  nbvalidbitskey = 8 * (Keylen % 4);
 
+   
+  /* HASH peripheral initialization */
 
+  HASH_DeInit();
 
+
 
+  /* HASH Configuration */
 
+  MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
 
+  MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
 
+  MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
 
+  if(Keylen > 64)
 
+  {
 
+    /* HMAC long Key */
 
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
 
+  }
 
+  else
 
+  {
 
+    /* HMAC short Key */
 
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
 
+  }
 
+  HASH_Init(&MD5_HASH_InitStructure);
 
+
 
+  /* Configure the number of valid bits in last word of the Key */
 
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
 
+
 
+  /* Write the Key */
 
+  for(i=0; i<Keylen; i+=4)
 
+  {
 
+    HASH_DataIn(*(uint32_t*)keyaddr);
 
+    keyaddr+=4;
 
+  }
 
+  
+  /* Start the HASH processor */
 
+  HASH_StartDigest();
 
+
 
+  /* wait until the Busy flag is RESET */
 
+  do
 
+  {
 
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+    counter++;
 
+  }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+  if (busystatus != RESET)
 
+  {
 
+     status = ERROR;
 
+  }
 
+  else
 
+  {
 
+    /* Configure the number of valid bits in last word of the Input data */
 
+    HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
 
+
 
+    /* Write the Input block in the IN FIFO */
 
+    for(i=0; i<Ilen; i+=4)
 
+    {
 
+      HASH_DataIn(*(uint32_t*)inputaddr);
 
+      inputaddr+=4;
 
+    }
 
+
 
+    /* Start the HASH processor */
 
+    HASH_StartDigest();
 
+
 
+    /* wait until the Busy flag is RESET */
 
+    counter =0;
 
+    do
 
+    {
 
+       busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+       counter++;
 
+    }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+    {
 
+      status = ERROR;
 
+    }
 
+    else
 
+    {  
+      /* Configure the number of valid bits in last word of the Key */
 
+      HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
 
+
 
+      /* Write the Key */
 
+      keyaddr = (uint32_t)Key;
 
+      for(i=0; i<Keylen; i+=4)
 
+      {
 
+        HASH_DataIn(*(uint32_t*)keyaddr);
 
+        keyaddr+=4;
 
+      }
 
+  
+       /* Start the HASH processor */
 
+       HASH_StartDigest();
 
+
 
+       /* wait until the Busy flag is RESET */
 
+       counter =0;
 
+       do
 
+       {
 
+          busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+          counter++;
 
+      }while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+      if (busystatus != RESET)
 
+      {
 
+         status = ERROR;
 
+      }
 
+      else
 
+      {
 
+         /* Read the message digest */
 
+         HASH_GetDigest(&MD5_MessageDigest);
 
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[0]);
 
+         outputaddr+=4;
 
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[1]);
 
+         outputaddr+=4;
 
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[2]);
 
+         outputaddr+=4;
 
+         *(uint32_t*)(outputaddr)  = __REV(MD5_MessageDigest.Data[3]);
 
+      }
 
+    }
 
+  }
 
+  return status;  
+}
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
+

+ 323 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_hash_sha1.c
Ver arquivo 

@@ -0,0 +1,323 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_hash_sha1.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides high level functions to compute the HASH SHA1 and
 
+  *          HMAC SHA1 Digest of an input message.
 
+  *          It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
 
+  *          peripheral.
 
+  *
 
+  *  @verbatim
 
+  * 
+  *          ===================================================================
 
+  *                                   How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable The HASH controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
 
+  *
 
+  *          2. Calculate the HASH SHA1 Digest using HASH_SHA1() function.
 
+  *
 
+  *          3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_hash.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup HASH 
+  * @brief HASH driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+#define SHA1BUSY_TIMEOUT    ((uint32_t) 0x00010000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup HASH_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup HASH_Group6 High Level SHA1 functions
 
+ *  @brief   High Level SHA1 Hash and HMAC functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          High Level SHA1 Hash and HMAC functions
 
+ ===============================================================================
 
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Compute the HASH SHA1 digest.
 
+  * @param  Input: pointer to the Input buffer to be treated.
 
+  * @param  Ilen: length of the Input buffer.
 
+  * @param  Output: the returned digest
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: digest computation done
 
+  *          - ERROR: digest computation failed
 
+  */
 
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 
+{
 
+  HASH_InitTypeDef SHA1_HASH_InitStructure;
 
+  HASH_MsgDigest SHA1_MessageDigest;
 
+  __IO uint16_t nbvalidbitsdata = 0;
 
+  uint32_t i = 0;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+
 
+  /* Number of valid bits in last word of the Input data */
 
+  nbvalidbitsdata = 8 * (Ilen % 4);
 
+
 
+  /* HASH peripheral initialization */
 
+  HASH_DeInit();
 
+
 
+  /* HASH Configuration */
 
+  SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
 
+  SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
 
+  SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
 
+  HASH_Init(&SHA1_HASH_InitStructure);
 
+
 
+  /* Configure the number of valid bits in last word of the data */
 
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
 
+
 
+  /* Write the Input block in the IN FIFO */
 
+  for(i=0; i<Ilen; i+=4)
 
+  {
 
+    HASH_DataIn(*(uint32_t*)inputaddr);
 
+    inputaddr+=4;
 
+  }
 
+
 
+  /* Start the HASH processor */
 
+  HASH_StartDigest();
 
+
 
+  /* wait until the Busy flag is RESET */
 
+  do
 
+  {
 
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+    counter++;
 
+  }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+  if (busystatus != RESET)
 
+  {
 
+     status = ERROR;
 
+  }
 
+  else
 
+  {
 
+    /* Read the message digest */
 
+    HASH_GetDigest(&SHA1_MessageDigest);
 
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[0]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[1]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[2]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[3]);
 
+    outputaddr+=4;
 
+    *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[4]);
 
+  }
 
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Compute the HMAC SHA1 digest.
 
+  * @param  Key: pointer to the Key used for HMAC.
 
+  * @param  Keylen: length of the Key used for HMAC.  
+  * @param  Input: pointer to the Input buffer to be treated.
 
+  * @param  Ilen: length of the Input buffer.
 
+  * @param  Output: the returned digest
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: digest computation done
 
+  *          - ERROR: digest computation failed
 
+  */
 
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
 
+                      uint32_t Ilen, uint8_t Output[20])
 
+{
 
+  HASH_InitTypeDef SHA1_HASH_InitStructure;
 
+  HASH_MsgDigest SHA1_MessageDigest;
 
+  __IO uint16_t nbvalidbitsdata = 0;
 
+  __IO uint16_t nbvalidbitskey = 0;
 
+  uint32_t i = 0;
 
+  __IO uint32_t counter = 0;
 
+  uint32_t busystatus = 0;
 
+  ErrorStatus status = SUCCESS;
 
+  uint32_t keyaddr    = (uint32_t)Key;
 
+  uint32_t inputaddr  = (uint32_t)Input;
 
+  uint32_t outputaddr = (uint32_t)Output;
 
+
 
+  /* Number of valid bits in last word of the Input data */
 
+  nbvalidbitsdata = 8 * (Ilen % 4);
 
+
 
+  /* Number of valid bits in last word of the Key */
 
+  nbvalidbitskey = 8 * (Keylen % 4);
 
+
 
+  /* HASH peripheral initialization */
 
+  HASH_DeInit();
 
+
 
+  /* HASH Configuration */
 
+  SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
 
+  SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
 
+  SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
 
+  if(Keylen > 64)
 
+  {
 
+    /* HMAC long Key */
 
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
 
+  }
 
+  else
 
+  {
 
+    /* HMAC short Key */
 
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
 
+  }
 
+  HASH_Init(&SHA1_HASH_InitStructure);
 
+
 
+  /* Configure the number of valid bits in last word of the Key */
 
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
 
+
 
+  /* Write the Key */
 
+  for(i=0; i<Keylen; i+=4)
 
+  {
 
+    HASH_DataIn(*(uint32_t*)keyaddr);
 
+    keyaddr+=4;
 
+  }
 
+
 
+  /* Start the HASH processor */
 
+  HASH_StartDigest();
 
+
 
+  /* wait until the Busy flag is RESET */
 
+  do
 
+  {
 
+    busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+    counter++;
 
+  }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+  if (busystatus != RESET)
 
+  {
 
+     status = ERROR;
 
+  }
 
+  else
 
+  {
 
+    /* Configure the number of valid bits in last word of the Input data */
 
+    HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
 
+
 
+    /* Write the Input block in the IN FIFO */
 
+    for(i=0; i<Ilen; i+=4)
 
+    {
 
+      HASH_DataIn(*(uint32_t*)inputaddr);
 
+      inputaddr+=4;
 
+    }
 
+
 
+    /* Start the HASH processor */
 
+    HASH_StartDigest();
 
+
 
+
 
+    /* wait until the Busy flag is RESET */
 
+    counter =0;
 
+    do
 
+    {
 
+      busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+      counter++;
 
+    }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+    if (busystatus != RESET)
 
+    {
 
+      status = ERROR;
 
+    }
 
+    else
 
+    {  
+      /* Configure the number of valid bits in last word of the Key */
 
+      HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
 
+
 
+      /* Write the Key */
 
+      keyaddr = (uint32_t)Key;
 
+      for(i=0; i<Keylen; i+=4)
 
+      {
 
+        HASH_DataIn(*(uint32_t*)keyaddr);
 
+        keyaddr+=4;
 
+      }
 
+
 
+      /* Start the HASH processor */
 
+      HASH_StartDigest();
 
+
 
+      /* wait until the Busy flag is RESET */
 
+      counter =0;
 
+      do
 
+      {
 
+        busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
 
+        counter++;
 
+      }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
 
+
 
+      if (busystatus != RESET)
 
+      {
 
+        status = ERROR;
 
+      }
 
+      else
 
+      {
 
+        /* Read the message digest */
 
+        HASH_GetDigest(&SHA1_MessageDigest);
 
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[0]);
 
+        outputaddr+=4;
 
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[1]);
 
+        outputaddr+=4;
 
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[2]);
 
+        outputaddr+=4;
 
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[3]);
 
+        outputaddr+=4;
 
+        *(uint32_t*)(outputaddr)  = __REV(SHA1_MessageDigest.Data[4]);
 
+      }
 
+    }  
+  }
 
+  return status;  
+}
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1401 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_i2c.c
Ver arquivo 

@@ -0,0 +1,1401 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_i2c.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Inter-integrated circuit (I2C)
 
+  *           - Initialization and Configuration
 
+  *           - Data transfers
 
+  *           - PEC management
 
+  *           - DMA transfers management
 
+  *           - Interrupts, events and flags management 
+  *           
+  *  @verbatim
 
+  *    
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
 
+  *             function for I2C1, I2C2 or I2C3.
 
+  *
 
+  *          2. Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+  *             RCC_AHBPeriphClockCmd() function. 
+  *
 
+  *          3. Peripherals alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
 
+  *                 - Configure the desired pin in alternate function by:
 
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
 
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
 
+  *                 - Call GPIO_Init() function
 
+  *                 Recommended configuration is Push-Pull, Pull-up, Open-Drain.
 
+  *                 Add an external pull up if necessary (typically 4.7 KOhm).      
+  *        
+  *          4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
 
+  *             Address using the I2C_Init() function.
 
+  *
 
+  *          5. Optionally you can enable/configure the following parameters without
 
+  *             re-initialization (i.e there is no need to call again I2C_Init() function):
 
+  *              - Enable the acknowledge feature using I2C_AcknowledgeConfig() function
 
+  *              - Enable the dual addressing mode using I2C_DualAddressCmd() function
 
+  *              - Enable the general call using the I2C_GeneralCallCmd() function
 
+  *              - Enable the clock stretching using I2C_StretchClockCmd() function
 
+  *              - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
 
+  *                function.
 
+  *              - Configure the NACK position for Master Receiver mode in case of 
+  *                2 bytes reception using the function I2C_NACKPositionConfig().  
+  *              - Enable the PEC Calculation using I2C_CalculatePEC() function
 
+  *              - For SMBus Mode: 
+  *                   - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
 
+  *                   - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
 
+  *
 
+  *          6. Enable the NVIC and the corresponding interrupt using the function 
+  *             I2C_ITConfig() if you need to use interrupt mode. 
+  *
 
+  *          7. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
 
+  *                   - Active the needed channel Request using I2C_DMACmd() or
 
+  *                     I2C_DMALastTransferCmd() function.
 
+  *              @note When using DMA mode, I2C interrupts may be used at the same time to
 
+  *                    control the communication flow (Start/Stop/Ack... events and errors).
 
+  * 
+  *          8. Enable the I2C using the I2C_Cmd() function.
 
+  * 
+  *          9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+  *             transfers. 
+  *
 
+  *  @endverbatim
 
+  *  
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_i2c.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup I2C 
+  * @brief I2C driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+#define CR1_CLEAR_MASK    ((uint16_t)0xFBF5)      /*<! I2C registers Masks */
 
+#define FLAG_MASK         ((uint32_t)0x00FFFFFF)  /*<! I2C FLAG mask */
 
+#define ITEN_MASK         ((uint32_t)0x07000000)  /*<! I2C Interrupt Enable mask */
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup I2C_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup I2C_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitialize the I2Cx peripheral registers to their default reset values.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @retval None
 
+  */
 
+void I2C_DeInit(I2C_TypeDef* I2Cx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+
 
+  if (I2Cx == I2C1)
 
+  {
 
+    /* Enable I2C1 reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
 
+    /* Release I2C1 from reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);    
+  }
 
+  else if (I2Cx == I2C2)
 
+  {
 
+    /* Enable I2C2 reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
 
+    /* Release I2C2 from reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);      
+  }
 
+  else 
+  {
 
+    if (I2Cx == I2C3)
 
+    {
 
+      /* Enable I2C3 reset state */
 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE);
 
+      /* Release I2C3 from reset state */
 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, DISABLE);     
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the I2Cx peripheral according to the specified 
+  *         parameters in the I2C_InitStruct.
 
+  *           
+  * @note   To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency 
+  *         (I2C peripheral input clock) must be a multiple of 10 MHz.  
+  *           
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains 
+  *         the configuration information for the specified I2C peripheral.
 
+  * @retval None
 
+  */
 
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
 
+{
 
+  uint16_t tmpreg = 0, freqrange = 0;
 
+  uint16_t result = 0x04;
 
+  uint32_t pclk1 = 8000000;
 
+  RCC_ClocksTypeDef  rcc_clocks;
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
 
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
 
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
 
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
 
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
 
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
 
+
 
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
 
+  /* Get the I2Cx CR2 value */
 
+  tmpreg = I2Cx->CR2;
 
+  /* Clear frequency FREQ[5:0] bits */
 
+  tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
 
+  /* Get pclk1 frequency value */
 
+  RCC_GetClocksFreq(&rcc_clocks);
 
+  pclk1 = rcc_clocks.PCLK1_Frequency;
 
+  /* Set frequency bits depending on pclk1 value */
 
+  freqrange = (uint16_t)(pclk1 / 1000000);
 
+  tmpreg |= freqrange;
 
+  /* Write to I2Cx CR2 */
 
+  I2Cx->CR2 = tmpreg;
 
+
 
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
 
+  /* Disable the selected I2C peripheral to configure TRISE */
 
+  I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
 
+  /* Reset tmpreg value */
 
+  /* Clear F/S, DUTY and CCR[11:0] bits */
 
+  tmpreg = 0;
 
+
 
+  /* Configure speed in standard mode */
 
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
 
+  {
 
+    /* Standard mode speed calculate */
 
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
 
+    /* Test if CCR value is under 0x4*/
 
+    if (result < 0x04)
 
+    {
 
+      /* Set minimum allowed value */
 
+      result = 0x04;  
+    }
 
+    /* Set speed value for standard mode */
 
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time for standard mode */
 
+    I2Cx->TRISE = freqrange + 1; 
+  }
 
+  /* Configure speed in fast mode */
 
+  /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
 
+     input clock) must be a multiple of 10 MHz */
 
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
 
+  {
 
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
 
+    {
 
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
 
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
 
+    }
 
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
 
+    {
 
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
 
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
 
+      /* Set DUTY bit */
 
+      result |= I2C_DutyCycle_16_9;
 
+    }
 
+
 
+    /* Test if CCR value is under 0x1*/
 
+    if ((result & I2C_CCR_CCR) == 0)
 
+    {
 
+      /* Set minimum allowed value */
 
+      result |= (uint16_t)0x0001;  
+    }
 
+    /* Set speed value and set F/S bit for fast mode */
 
+    tmpreg |= (uint16_t)(result | I2C_CCR_FS);
 
+    /* Set Maximum Rise Time for fast mode */
 
+    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
+  }
 
+
 
+  /* Write to I2Cx CCR */
 
+  I2Cx->CCR = tmpreg;
 
+  /* Enable the selected I2C peripheral */
 
+  I2Cx->CR1 |= I2C_CR1_PE;
 
+
 
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
 
+  /* Get the I2Cx CR1 value */
 
+  tmpreg = I2Cx->CR1;
 
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
 
+  tmpreg &= CR1_CLEAR_MASK;
 
+  /* Configure I2Cx: mode and acknowledgement */
 
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
 
+  /* Set ACK bit according to I2C_Ack value */
 
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
 
+  /* Write to I2Cx CR1 */
 
+  I2Cx->CR1 = tmpreg;
 
+
 
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
 
+  /* Set I2Cx Own Address1 and acknowledged address */
 
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
 
+}
 
+
 
+/**
 
+  * @brief  Fills each I2C_InitStruct member with its default value.
 
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
 
+{
 
+/*---------------- Reset I2C init structure parameters values ----------------*/
 
+  /* initialize the I2C_ClockSpeed member */
 
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
 
+  /* Initialize the I2C_Mode member */
 
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
 
+  /* Initialize the I2C_DutyCycle member */
 
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
 
+  /* Initialize the I2C_OwnAddress1 member */
 
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
 
+  /* Initialize the I2C_Ack member */
 
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
 
+  /* Initialize the I2C_AcknowledgedAddress member */
 
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C peripheral.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C peripheral */
 
+    I2Cx->CR1 |= I2C_CR1_PE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C peripheral */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Generates I2Cx communication START condition.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C START condition generation.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None.
 
+  */
 
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Generate a START condition */
 
+    I2Cx->CR1 |= I2C_CR1_START;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the START condition generation */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Generates I2Cx communication STOP condition.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C STOP condition generation.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None.
 
+  */
 
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Generate a STOP condition */
 
+    I2Cx->CR1 |= I2C_CR1_STOP;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the STOP condition generation */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Transmits the address byte to select the slave device.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  Address: specifies the slave address which will be transmitted
 
+  * @param  I2C_Direction: specifies whether the I2C device will be a Transmitter
 
+  *         or a Receiver. 
+  *          This parameter can be one of the following values
 
+  *            @arg I2C_Direction_Transmitter: Transmitter mode
 
+  *            @arg I2C_Direction_Receiver: Receiver mode
 
+  * @retval None.
 
+  */
 
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
 
+  /* Test on the direction to set/reset the read/write bit */
 
+  if (I2C_Direction != I2C_Direction_Transmitter)
 
+  {
 
+    /* Set the address bit0 for read */
 
+    Address |= I2C_OAR1_ADD0;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the address bit0 for write */
 
+    Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
 
+  }
 
+  /* Send the address */
 
+  I2Cx->DR = Address;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C acknowledge feature.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C Acknowledgement.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None.
 
+  */
 
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the acknowledgement */
 
+    I2Cx->CR1 |= I2C_CR1_ACK;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the acknowledgement */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the specified I2C own address2.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  Address: specifies the 7bit I2C own address2.
 
+  * @retval None.
 
+  */
 
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
 
+{
 
+  uint16_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+
 
+  /* Get the old register value */
 
+  tmpreg = I2Cx->OAR2;
 
+
 
+  /* Reset I2Cx Own address2 bit [7:1] */
 
+  tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
 
+
 
+  /* Set I2Cx Own address2 */
 
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
 
+
 
+  /* Store the new register value */
 
+  I2Cx->OAR2 = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C dual addressing mode.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C dual addressing mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable dual addressing mode */
 
+    I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
 
+  }
 
+  else
 
+  {
 
+    /* Disable dual addressing mode */
 
+    I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C general call feature.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C General call.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable generall call */
 
+    I2Cx->CR1 |= I2C_CR1_ENGC;
 
+  }
 
+  else
 
+  {
 
+    /* Disable generall call */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C software reset.
 
+  * @note   When software reset is enabled, the I2C IOs are released (this can
 
+  *         be useful to recover from bus errors).  
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C software reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Peripheral under reset */
 
+    I2Cx->CR1 |= I2C_CR1_SWRST;
 
+  }
 
+  else
 
+  {
 
+    /* Peripheral not under reset */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C Clock stretching.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2Cx Clock stretching.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState == DISABLE)
 
+  {
 
+    /* Enable the selected I2C Clock stretching */
 
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C Clock stretching */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Selects the specified I2C fast mode duty cycle.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
 
+  *            @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
 
+  * @retval None
 
+  */
 
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
 
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
 
+  {
 
+    /* I2C fast mode Tlow/Thigh=2 */
 
+    I2Cx->CCR &= I2C_DutyCycle_2;
 
+  }
 
+  else
 
+  {
 
+    /* I2C fast mode Tlow/Thigh=16/9 */
 
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
 
+  * @note   This function is useful in I2C Master Receiver mode when the number
 
+  *         of data to be received is equal to 2. In this case, this function 
+  *         should be called (with parameter I2C_NACKPosition_Next) before data 
+  *         reception starts,as described in the 2-byte reception procedure 
+  *         recommended in Reference Manual in Section: Master receiver.                
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_NACKPosition: specifies the NACK position. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
 
+  *                                        received byte.  
+  *            @arg I2C_NACKPosition_Current: indicates that current byte is the last 
+  *                                           received byte.
 
+  *            
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
+  *          is intended to used in SMBUS mode. 
+  *            
+  * @retval None
 
+  */
 
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
 
+  
+  /* Check the input parameter */
 
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
 
+  {
 
+    /* Next byte in shift register is the last received byte */
 
+    I2Cx->CR1 |= I2C_NACKPosition_Next;
 
+  }
 
+  else
 
+  {
 
+    /* Current byte in shift register is the last received byte */
 
+    I2Cx->CR1 &= I2C_NACKPosition_Current;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
 
+  *            @arg I2C_SMBusAlert_High: SMBAlert pin driven high
 
+  * @retval None
 
+  */
 
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
 
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
 
+  {
 
+    /* Drive the SMBusAlert pin Low */
 
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
 
+  }
 
+  else
 
+  {
 
+    /* Drive the SMBusAlert pin High  */
 
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C ARP.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2Cx ARP. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C ARP */
 
+    I2Cx->CR1 |= I2C_CR1_ENARP;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C ARP */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_Group2 Data transfers functions
 
+ *  @brief   Data transfers functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                        Data transfers functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Sends a data byte through the I2Cx peripheral.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  Data: Byte to be transmitted..
 
+  * @retval None
 
+  */
 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  /* Write in the DR register the data to be sent */
 
+  I2Cx->DR = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @retval The value of the received data.
 
+  */
 
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  /* Return the data in the DR register */
 
+  return (uint8_t)I2Cx->DR;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_Group3 PEC management functions
 
+ *  @brief   PEC management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         PEC management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C PEC transfer.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C PEC transmission.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C PEC transmission */
 
+    I2Cx->CR1 |= I2C_CR1_PEC;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C PEC transmission */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Selects the specified I2C PEC position.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_PECPosition: specifies the PEC position. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_PECPosition_Next: indicates that the next byte is PEC
 
+  *            @arg I2C_PECPosition_Current: indicates that current byte is PEC
 
+  *       
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
 
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
+  *          is intended to used in I2C mode.
 
+  *                
+  * @retval None
 
+  */
 
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
 
+  if (I2C_PECPosition == I2C_PECPosition_Next)
 
+  {
 
+    /* Next byte in shift register is PEC */
 
+    I2Cx->CR1 |= I2C_PECPosition_Next;
 
+  }
 
+  else
 
+  {
 
+    /* Current byte in shift register is PEC */
 
+    I2Cx->CR1 &= I2C_PECPosition_Current;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2Cx PEC value calculation.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C PEC calculation */
 
+    I2Cx->CR1 |= I2C_CR1_ENPEC;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C PEC calculation */
 
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Returns the PEC value for the specified I2C.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @retval The PEC value.
 
+  */
 
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  /* Return the selected I2C PEC value */
 
+  return ((I2Cx->SR2) >> 8);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_Group4 DMA transfers management functions
 
+ *  @brief   DMA transfers management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         DMA transfers management functions
 
+ ===============================================================================  
+  This section provides functions allowing to configure the I2C DMA channels 
+  requests.
 
+  
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C DMA requests.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C DMA transfer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C DMA requests */
 
+    I2Cx->CR2 |= I2C_CR2_DMAEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C DMA requests */
 
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Specifies that the next DMA transfer is the last one.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  NewState: new state of the I2C DMA last transfer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Next DMA transfer is the last transfer */
 
+    I2Cx->CR2 |= I2C_CR2_LAST;
 
+  }
 
+  else
 
+  {
 
+    /* Next DMA transfer is not the last transfer */
 
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup I2C_Group5 Interrupts events and flags management functions
 
+ *  @brief   Interrupts, events and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                Interrupts, events and flags management functions
 
+ ===============================================================================  
+  This section provides functions allowing to configure the I2C Interrupts 
+  sources and check or clear the flags or pending bits status.
 
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+
 
+ ===============================================================================
 
+                          I2C State Monitoring Functions                    
+ ===============================================================================   
+  This I2C driver provides three different ways for I2C state monitoring
 
+  depending on the application requirements and constraints:
 
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
 
+     -----------------------------------------------------------
 
+        It compares the status registers (SR1 and SR2) content to a given event
 
+        (can be the combination of one or more flags).
 
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
 
+
 
+          - When to use
 
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
 
+             - It is also suitable for users who need to define their own events.
 
+
 
+          - Limitations
 
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
 
+         
+     @note 
+         For error management, it is advised to use the following functions:
 
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
 
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
 
+             Where x is the peripheral instance (I2C1, I2C2 ...)
 
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
 
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
 
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
 
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
 
+
 
+          - When to use
 
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
 
+             - The returned value could be compared to events already defined in 
+               the library (stm32f4xx_i2c.h) or to custom values defined by user.
 
+               This function is suitable when multiple flags are monitored at the 
+               same time.
 
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
 
+
 
+          - Limitations
 
+             - User may need to define his own events.
 
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
 
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
 
+     -----------------------------------------------------------------------
 
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
 
+          - When to use
 
+             - This function could be used for specific applications or in debug 
+               phase.
 
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
 
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
 
+             - Function may need to be called twice or more in order to monitor 
+               one single event.
 
+ 
+   For detailed description of Events, please refer to section I2C_Events in 
+   stm32f4xx_i2c.h file.
 
+       
+@endverbatim
 
+  * @{
 
+  */
 
+   
+/**
 
+  * @brief  Reads the specified I2C register and returns its value.
 
+  * @param  I2C_Register: specifies the register to read.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_Register_CR1:  CR1 register.
 
+  *            @arg I2C_Register_CR2:   CR2 register.
 
+  *            @arg I2C_Register_OAR1:  OAR1 register.
 
+  *            @arg I2C_Register_OAR2:  OAR2 register.
 
+  *            @arg I2C_Register_DR:    DR register.
 
+  *            @arg I2C_Register_SR1:   SR1 register.
 
+  *            @arg I2C_Register_SR2:   SR2 register.
 
+  *            @arg I2C_Register_CCR:   CCR register.
 
+  *            @arg I2C_Register_TRISE: TRISE register.
 
+  * @retval The value of the read register.
 
+  */
 
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_REGISTER(I2C_Register));
 
+
 
+  tmp = (uint32_t) I2Cx;
 
+  tmp += I2C_Register;
 
+
 
+  /* Return the selected register value */
 
+  return (*(__IO uint16_t *) tmp);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified I2C interrupts.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg I2C_IT_BUF: Buffer interrupt mask
 
+  *            @arg I2C_IT_EVT: Event interrupt mask
 
+  *            @arg I2C_IT_ERR: Error interrupt mask
 
+  * @param  NewState: new state of the specified I2C interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected I2C interrupts */
 
+    I2Cx->CR2 |= I2C_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected I2C interrupts */
 
+    I2Cx->CR2 &= (uint16_t)~I2C_IT;
 
+  }
 
+}
 
+
 
+/*
 
+ ===============================================================================
 
+                          1. Basic state monitoring                    
+ ===============================================================================  
+ */
 
+
 
+/**
 
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
 
+  *         as parameter.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_EVENT: specifies the event to be checked. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
 
+  *            @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
 
+  *            @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
 
+  *            @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
 
+  *            @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
 
+  *            @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
 
+  *            @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
 
+  *            @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
 
+  *            @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
 
+  *            @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
 
+  *            @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
 
+  *            @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
 
+  *            @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
 
+  *            @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
 
+  *            @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6     
+  *            @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
 
+  *            @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
 
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
 
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
 
+  *            @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
 
+  *     
+  * @note   For detailed description of Events, please refer to section I2C_Events
 
+  *         in stm32f4xx_i2c.h file.
 
+  *    
+  * @retval An ErrorStatus enumeration value:
 
+  *           - SUCCESS: Last event is equal to the I2C_EVENT
 
+  *           - ERROR: Last event is different from the I2C_EVENT
 
+  */
 
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
 
+{
 
+  uint32_t lastevent = 0;
 
+  uint32_t flag1 = 0, flag2 = 0;
 
+  ErrorStatus status = ERROR;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
 
+
 
+  /* Read the I2Cx status register */
 
+  flag1 = I2Cx->SR1;
 
+  flag2 = I2Cx->SR2;
 
+  flag2 = flag2 << 16;
 
+
 
+  /* Get the last event value from I2C status register */
 
+  lastevent = (flag1 | flag2) & FLAG_MASK;
 
+
 
+  /* Check whether the last event contains the I2C_EVENT */
 
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
 
+  {
 
+    /* SUCCESS: last event is equal to I2C_EVENT */
 
+    status = SUCCESS;
 
+  }
 
+  else
 
+  {
 
+    /* ERROR: last event is different from I2C_EVENT */
 
+    status = ERROR;
 
+  }
 
+  /* Return status */
 
+  return status;
 
+}
 
+
 
+/*
 
+ ===============================================================================
 
+                          2. Advanced state monitoring                   
+ ===============================================================================  
+ */
 
+
 
+/**
 
+  * @brief  Returns the last I2Cx Event.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  *     
+  * @note   For detailed description of Events, please refer to section I2C_Events
 
+  *         in stm32f4xx_i2c.h file.
 
+  *    
+  * @retval The last event
 
+  */
 
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
 
+{
 
+  uint32_t lastevent = 0;
 
+  uint32_t flag1 = 0, flag2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+
 
+  /* Read the I2Cx status register */
 
+  flag1 = I2Cx->SR1;
 
+  flag2 = I2Cx->SR2;
 
+  flag2 = flag2 << 16;
 
+
 
+  /* Get the last event value from I2C status register */
 
+  lastevent = (flag1 | flag2) & FLAG_MASK;
 
+
 
+  /* Return status */
 
+  return lastevent;
 
+}
 
+
 
+/*
 
+ ===============================================================================
 
+                          3. Flag-based state monitoring                   
+ ===============================================================================  
+ */
 
+
 
+/**
 
+  * @brief  Checks whether the specified I2C flag is set or not.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
 
+  *            @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
 
+  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
 
+  *            @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
 
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
 
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
 
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
 
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
 
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
 
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
 
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
 
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
 
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
 
+  *            @arg I2C_FLAG_BERR: Bus error flag
 
+  *            @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
 
+  *            @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
 
+  *            @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
 
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
 
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
 
+  *            @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
 
+  *                                Address matched flag (Slave mode)"ENDAD"
 
+  *            @arg I2C_FLAG_SB: Start bit flag (Master mode)
 
+  * @retval The new state of I2C_FLAG (SET or RESET).
 
+  */
 
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
 
+
 
+  /* Get the I2Cx peripheral base address */
 
+  i2cxbase = (uint32_t)I2Cx;
 
+  
+  /* Read flag register index */
 
+  i2creg = I2C_FLAG >> 28;
 
+  
+  /* Get bit[23:0] of the flag */
 
+  I2C_FLAG &= FLAG_MASK;
 
+  
+  if(i2creg != 0)
 
+  {
 
+    /* Get the I2Cx SR1 register address */
 
+    i2cxbase += 0x14;
 
+  }
 
+  else
 
+  {
 
+    /* Flag in I2Cx SR2 Register */
 
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
 
+    /* Get the I2Cx SR2 register address */
 
+    i2cxbase += 0x18;
 
+  }
 
+  
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
 
+  {
 
+    /* I2C_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* I2C_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  
+  /* Return the I2C_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the I2Cx's pending flags.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
 
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
 
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
 
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
 
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
 
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
 
+  *            @arg I2C_FLAG_BERR: Bus error flag
 
+  *   
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *          to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
+  *          to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
 
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
+  *          second byte of the address in DR register.
 
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
+  *          read/write to I2C_DR register (I2C_SendData()).
 
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
+  *          I2C_SR2 register ((void)(I2Cx->SR2)).
 
+  * @note   SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
 
+  *          register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
 
+  *          register (I2C_SendData()).
 
+  *  
+  * @retval None
 
+  */
 
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
 
+{
 
+  uint32_t flagpos = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
 
+  /* Get the I2C flag position */
 
+  flagpos = I2C_FLAG & FLAG_MASK;
 
+  /* Clear the selected I2C flag */
 
+  I2Cx->SR1 = (uint16_t)~flagpos;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_IT: specifies the interrupt source to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg I2C_IT_SMBALERT: SMBus Alert flag
 
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
 
+  *            @arg I2C_IT_PECERR: PEC error in reception flag
 
+  *            @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
 
+  *            @arg I2C_IT_AF: Acknowledge failure flag
 
+  *            @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
 
+  *            @arg I2C_IT_BERR: Bus error flag
 
+  *            @arg I2C_IT_TXE: Data register empty flag (Transmitter)
 
+  *            @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
 
+  *            @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
 
+  *            @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
 
+  *            @arg I2C_IT_BTF: Byte transfer finished flag
 
+  *            @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
 
+  *                              Address matched flag (Slave mode)"ENDAD"
 
+  *            @arg I2C_IT_SB: Start bit flag (Master mode)
 
+  * @retval The new state of I2C_IT (SET or RESET).
 
+  */
 
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t enablestatus = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_GET_IT(I2C_IT));
 
+
 
+  /* Check if the interrupt source is enabled or not */
 
+  enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
 
+  
+  /* Get bit[23:0] of the flag */
 
+  I2C_IT &= FLAG_MASK;
 
+
 
+  /* Check the status of the specified I2C flag */
 
+  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
 
+  {
 
+    /* I2C_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* I2C_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the I2C_IT status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the I2Cx's interrupt pending bits.
 
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
 
+  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg I2C_IT_SMBALERT: SMBus Alert interrupt
 
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
 
+  *            @arg I2C_IT_PECERR: PEC error in reception  interrupt
 
+  *            @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
 
+  *            @arg I2C_IT_AF: Acknowledge failure interrupt
 
+  *            @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
 
+  *            @arg I2C_IT_BERR: Bus error interrupt
 
+  * 
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *          to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *          I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
 
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
+  *          byte of the address in I2C_DR register.
 
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
+  *          read/write to I2C_DR register (I2C_SendData()).
 
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
+  *          I2C_SR2 register ((void)(I2Cx->SR2)).
 
+  * @note   SB (Start Bit) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *          I2C_DR register (I2C_SendData()).
 
+  * @retval None
 
+  */
 
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
 
+{
 
+  uint32_t flagpos = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
 
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
 
+
 
+  /* Get the I2C flag position */
 
+  flagpos = I2C_IT & FLAG_MASK;
 
+
 
+  /* Clear the selected I2C flag */
 
+  I2Cx->SR1 = (uint16_t)~flagpos;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 269 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_iwdg.c
Ver arquivo 

@@ -0,0 +1,269 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_iwdg.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           - Prescaler and Counter configuration
 
+  *           - IWDG activation
 
+  *           - Flag management
 
+  *
 
+  *  @verbatim  
+  *  
+  *          ===================================================================
 
+  *                                     IWDG features
 
+  *          ===================================================================
 
+  *    
+  *          The IWDG can be started by either software or hardware (configurable
 
+  *          through option byte).
 
+  *            
+  *          The IWDG is clocked by its own dedicated low-speed clock (LSI) and
 
+  *          thus stays active even if the main clock fails.
 
+  *          Once the IWDG is started, the LSI is forced ON and cannot be disabled
 
+  *          (LSI cannot be disabled too), and the counter starts counting down from 
+  *          the reset value of 0xFFF. When it reaches the end of count value (0x000)
 
+  *          a system reset is generated.
 
+  *          The IWDG counter should be reloaded at regular intervals to prevent
 
+  *          an MCU reset.
 
+  *                           
+  *          The IWDG is implemented in the VDD voltage domain that is still functional
 
+  *          in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).          
+  *            
+  *          IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
 
+  *          reset occurs.
 
+  *            
+  *          Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
 
+  *          The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
 
+  *          devices provide the capability to measure the LSI frequency (LSI clock
 
+  *          connected internally to TIM5 CH4 input capture). The measured value
 
+  *          can be used to have an IWDG timeout with an acceptable accuracy. 
+  *          For more information, please refer to the STM32F4xx Reference manual
 
+  *          
+  *                            
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable write access to IWDG_PR and IWDG_RLR registers using
 
+  *             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
 
+  *               
+  *          2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
 
+  *            
+  *          3. Configure the IWDG counter value using IWDG_SetReload() function.
 
+  *             This value will be loaded in the IWDG counter each time the counter
 
+  *             is reloaded, then the IWDG will start counting down from this value.
 
+  *            
+  *          4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
 
+  *             in software mode (no need to enable the LSI, it will be enabled
 
+  *             by hardware)
 
+  *             
+  *          5. Then the application program must reload the IWDG counter at regular
 
+  *             intervals during normal operation to prevent an MCU reset, using
 
+  *             IWDG_ReloadCounter() function.      
+  *          
+  *  @endverbatim
 
+  *    
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_iwdg.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* KR register bit mask */
 
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
 
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup IWDG_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
 
+ *  @brief   Prescaler and Counter configuration functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Prescaler and Counter configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
 
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
 
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
 
+  * @retval None
 
+  */
 
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
 
+  IWDG->KR = IWDG_WriteAccess;
 
+}
 
+
 
+/**
 
+  * @brief  Sets IWDG Prescaler value.
 
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
 
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
 
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
 
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
 
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
 
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
 
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
 
+  * @retval None
 
+  */
 
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
 
+  IWDG->PR = IWDG_Prescaler;
 
+}
 
+
 
+/**
 
+  * @brief  Sets IWDG Reload value.
 
+  * @param  Reload: specifies the IWDG Reload value.
 
+  *          This parameter must be a number between 0 and 0x0FFF.
 
+  * @retval None
 
+  */
 
+void IWDG_SetReload(uint16_t Reload)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_IWDG_RELOAD(Reload));
 
+  IWDG->RLR = Reload;
 
+}
 
+
 
+/**
 
+  * @brief  Reloads IWDG counter with value defined in the reload register
 
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void IWDG_ReloadCounter(void)
 
+{
 
+  IWDG->KR = KR_KEY_RELOAD;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup IWDG_Group2 IWDG activation function
 
+ *  @brief   IWDG activation function 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                          IWDG activation function
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void IWDG_Enable(void)
 
+{
 
+  IWDG->KR = KR_KEY_ENABLE;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
 
+@verbatim   
+ ===============================================================================
 
+                            Flag management function 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Checks whether the specified IWDG flag is set or not.
 
+  * @param  IWDG_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
 
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
 
+  * @retval The new state of IWDG_FLAG (SET or RESET).
 
+  */
 
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
 
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the flag status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 664 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_pwr.c
Ver arquivo 

@@ -0,0 +1,664 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_pwr.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           - Backup Domain Access
 
+  *           - PVD configuration
 
+  *           - WakeUp pin configuration
 
+  *           - Main and Backup Regulators configuration
 
+  *           - FLASH Power Down configuration
 
+  *           - Low Power modes configuration
 
+  *           - Flags management
 
+  *               
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_pwr.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup PWR 
+  * @brief PWR driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* --------- PWR registers bit address in the alias region ---------- */
 
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
 
+
 
+/* --- CR Register ---*/
 
+
 
+/* Alias word address of DBP bit */
 
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
 
+#define DBP_BitNumber            0x08
 
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
 
+
 
+/* Alias word address of PVDE bit */
 
+#define PVDE_BitNumber           0x04
 
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
 
+
 
+/* Alias word address of FPDS bit */
 
+#define FPDS_BitNumber           0x09
 
+#define CR_FPDS_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
 
+
 
+/* Alias word address of PMODE bit */
 
+#define PMODE_BitNumber           0x0E
 
+#define CR_PMODE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
 
+
 
+
 
+/* --- CSR Register ---*/
 
+
 
+/* Alias word address of EWUP bit */
 
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
 
+#define EWUP_BitNumber           0x08
 
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
 
+
 
+/* Alias word address of BRE bit */
 
+#define BRE_BitNumber            0x09
 
+#define CSR_BRE_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
 
+
 
+/* ------------------ PWR registers bit mask ------------------------ */
 
+
 
+/* CR register bit mask */
 
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
 
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup PWR_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function  
+ *
 
+@verbatim   
+ ===============================================================================
 
+                            Backup Domain Access function 
+ ===============================================================================  
+
 
+  After reset, the backup domain (RTC registers, RTC backup data 
+  registers and backup SRAM) is protected against possible unwanted 
+  write accesses. 
+  To enable access to the RTC Domain and RTC registers, proceed as follows:
 
+    - Enable the Power Controller (PWR) APB1 interface clock using the
 
+      RCC_APB1PeriphClockCmd() function.
 
+    - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.     
+  * @param  None
 
+  * @retval None
 
+  */
 
+void PWR_DeInit(void)
 
+{
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
 
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
 
+  * @param  NewState: new state of the access to the backup domain.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void PWR_BackupAccessCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group2 PVD configuration functions
 
+ *  @brief   PVD configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                           PVD configuration functions
 
+ ===============================================================================  
+
 
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold
 
+   selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
 
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+   PVD threshold. This event is internally connected to the EXTI line16
 
+   and can generate an interrupt if enabled through the EXTI registers.
 
+ - The PVD is stopped in Standby mode.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
 
+  * @param  PWR_PVDLevel: specifies the PVD detection level
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_PVDLevel_0
 
+  *            @arg PWR_PVDLevel_1
 
+  *            @arg PWR_PVDLevel_2
 
+  *            @arg PWR_PVDLevel_3
 
+  *            @arg PWR_PVDLevel_4
 
+  *            @arg PWR_PVDLevel_5
 
+  *            @arg PWR_PVDLevel_6
 
+  *            @arg PWR_PVDLevel_7
 
+  * @note   Refer to the electrical characteristics of your device datasheet for
 
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
 
+  * @retval None
 
+  */
 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
 
+  
+  tmpreg = PWR->CR;
 
+  
+  /* Clear PLS[7:5] bits */
 
+  tmpreg &= CR_PLS_MASK;
 
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
 
+  tmpreg |= PWR_PVDLevel;
 
+  
+  /* Store the new value */
 
+  PWR->CR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
 
+  * @param  NewState: new state of the PVD.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void PWR_PVDCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group3 WakeUp pin configuration functions
 
+ *  @brief   WakeUp pin configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    WakeUp pin configuration functions
 
+ ===============================================================================  
+
 
+ - WakeUp pin is used to wakeup the system from Standby mode. This pin is 
+   forced in input pull down configuration and is active on rising edges.
 
+ - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the WakeUp Pin functionality.
 
+  * @param  NewState: new state of the WakeUp Pin functionality.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void PWR_WakeUpPinCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
 
+ *  @brief   Main and Backup Regulators configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Main and Backup Regulators configuration functions
 
+ ===============================================================================  
+
 
+ - The backup domain includes 4 Kbytes of backup SRAM accessible only from the 
+   CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained 
+   even in Standby or VBAT mode when the low power backup regulator is enabled. 
+   It can be considered as an internal EEPROM when VBAT is always present.
 
+   You can use the PWR_BackupRegulatorCmd() function to enable the low power
 
+   backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
 
+   ready or not. 
+
 
+ - When the backup domain is supplied by VDD (analog switch connected to VDD) 
+   the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+   save battery life.
 
+
 
+ - The backup SRAM is not mass erased by an tamper event. It is read protected 
+   to prevent confidential data, such as cryptographic private key, from being 
+   accessed. The backup SRAM can be erased only through the Flash interface when
 
+   a protection level change from level 1 to level 0 is requested. 
+   Refer to the description of Read protection (RDP) in the Flash programming manual.
 
+
 
+ - The main internal regulator can be configured to have a tradeoff between performance
 
+   and power consumption when the device does not operate at the maximum frequency. 
+   This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
 
+   in PWR_CR register: 
+      - When this bit is set (Regulator voltage output Scale 1 mode selected) the System
 
+        frequency can go up to 168 MHz. 
+      - When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
 
+        frequency can go up to 144 MHz. 
+   Refer to the datasheets for more details.
 
+           
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the Backup Regulator.
 
+  * @param  NewState: new state of the Backup Regulator.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void PWR_BackupRegulatorCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the main internal regulator output voltage.
 
+  * @param  PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
 
+  *         a tradeoff between performance and power consumption when the device does
 
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, 
+  *                                                System frequency up to 168 MHz. 
+  *            @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, 
+  *                                                System frequency up to 144 MHz.    
+  * @retval None
 
+  */
 
+void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
 
+
 
+  if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
 
+  {
 
+    PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
 
+  }
 
+  else
 
+  {    
+    PWR->CR |= PWR_Regulator_Voltage_Scale1;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group5 FLASH Power Down configuration functions
 
+ *  @brief   FLASH Power Down configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+           FLASH Power Down configuration functions
 
+ ===============================================================================  
+
 
+ - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
 
+   function, the Flash memory also enters power down mode when the device enters 
+   Stop mode. When the Flash memory is in power down mode, an additional startup 
+   delay is incurred when waking up from Stop mode.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the Flash Power Down in STOP mode.
 
+  * @param  NewState: new state of the Flash power mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void PWR_FlashPowerDownCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group6 Low Power modes configuration functions
 
+ *  @brief   Low Power modes configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Low Power modes configuration functions
 
+ ===============================================================================  
+
 
+  The devices feature 3 low-power modes:
 
+   - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
 
+   - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
 
+   - Standby mode: 1.2V domain powered off.
 
+   
+   Sleep mode
 
+   ===========
 
+    - Entry:
 
+      - The Sleep mode is entered by using the __WFI() or __WFE() functions.
 
+    - Exit:
 
+      - Any peripheral interrupt acknowledged by the nested vectored interrupt 
+        controller (NVIC) can wake up the device from Sleep mode.
 
+
 
+   Stop mode
 
+   ==========
 
+   In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
 
+   and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+   are preserved.
 
+   The voltage regulator can be configured either in normal or low-power mode.
 
+   To minimize the consumption In Stop mode, FLASH can be powered off before 
+   entering the Stop mode. It can be switched on again by software after exiting 
+   the Stop mode using the PWR_FlashPowerDownCmd() function. 
+   
+    - Entry:
 
+      - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+        function with regulator in LowPower or with Regulator ON.
 
+    - Exit:
 
+      - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
 
+      
+   Standby mode
 
+   ============
 
+   The Standby mode allows to achieve the lowest power consumption. It is based 
+   on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+   The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+   the HSE oscillator are also switched off. SRAM and register contents are lost 
+   except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+   circuitry.
 
+   
+   The voltage regulator is OFF.
 
+      
+    - Entry:
 
+      - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
 
+    - Exit:
 
+      - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
 
+        tamper event, time-stamp event, external reset in NRST pin, IWDG reset.              
+
 
+   Auto-wakeup (AWU) from low-power mode
 
+   =====================================
 
+   The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+   Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+   without depending on an external interrupt (Auto-wakeup mode).
 
+
 
+   - RTC auto-wakeup (AWU) from the Stop mode
 
+     ----------------------------------------
 
+     
+     - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
 
+       - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
 
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
 
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
 
+     - To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
 
+       - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
 
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
 
+       - Configure the RTC to detect the tamper or time stamp event using the
 
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
 
+         functions.
 
+     - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
 
+       - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
 
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
 
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
 
+
 
+   - RTC auto-wakeup (AWU) from the Standby mode
 
+     -------------------------------------------
 
+     - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
 
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
 
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
 
+     - To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
 
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
 
+       - Configure the RTC to detect the tamper or time stamp event using the
 
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
 
+         functions.
 
+     - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
 
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
 
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enters STOP mode.
 
+  *   
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
 
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
 
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.           
+  *     
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_Regulator_ON: STOP mode with regulator ON
 
+  *            @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
 
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
 
+  *            @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
 
+  * @retval None
 
+  */
 
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
 
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
 
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
 
+  tmpreg = PWR->CR;
 
+  /* Clear PDDS and LPDSR bits */
 
+  tmpreg &= CR_DS_MASK;
 
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
 
+  tmpreg |= PWR_Regulator;
 
+  
+  /* Store the new value */
 
+  PWR->CR = tmpreg;
 
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
 
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
+  
+  /* Select STOP mode entry --------------------------------------------------*/
 
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
 
+  {   
+    /* Request Wait For Interrupt */
 
+    __WFI();
 
+  }
 
+  else
 
+  {
 
+    /* Request Wait For Event */
 
+    __WFE();
 
+  }
 
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
 
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
 
+
 
+/**
 
+  * @brief  Enters STANDBY mode.
 
+  * @note   In Standby mode, all I/O pins are high impedance except for:
 
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
 
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @param  None
 
+  * @retval None
 
+  */
 
+void PWR_EnterSTANDBYMode(void)
 
+{
 
+  /* Clear Wakeup flag */
 
+  PWR->CR |= PWR_CR_CWUF;
 
+  
+  /* Select STANDBY mode */
 
+  PWR->CR |= PWR_CR_PDDS;
 
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
 
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
+  
+/* This option is used to ensure that store operations are completed */
 
+#if defined ( __CC_ARM   )
 
+  __force_stores();
 
+#endif
 
+  /* Request Wait For Interrupt */
 
+  __WFI();
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup PWR_Group7 Flags management functions
 
+ *  @brief   Flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                           Flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Checks whether the specified PWR flag is set or not.
 
+  * @param  PWR_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
 
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
 
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the PWR_PVDCmd() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
 
+  *                  until the PVDE bit is set.
 
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready. 
+  * @retval The new state of PWR_FLAG (SET or RESET).
 
+  */
 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
 
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the flag status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the PWR's pending flags.
 
+  * @param  PWR_FLAG: specifies the flag to clear.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg PWR_FLAG_WU: Wake Up flag
 
+  *            @arg PWR_FLAG_SB: StandBy flag
 
+  * @retval None
 
+  */
 
+void PWR_ClearFlag(uint32_t PWR_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
 
+         
+  PWR->CR |=  PWR_FLAG << 2;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1814 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_rcc.c
Ver arquivo 

@@ -0,0 +1,1814 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rcc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Reset and clock control (RCC) peripheral:
 
+  *           - Internal/external clocks, PLL, CSS and MCO configuration
 
+  *           - System, AHB and APB busses clocks configuration
 
+  *           - Peripheral clocks configuration
 
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim
 
+  *               
+  *          ===================================================================
 
+  *                               RCC specific features
 
+  *          ===================================================================
 
+  *    
+  *          After reset the device is running from Internal High Speed oscillator 
+  *          (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+  *          and I-Cache are disabled, and all peripherals are off except internal
 
+  *          SRAM, Flash and JTAG.
 
+  *           - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
 
+  *             all peripherals mapped on these busses are running at HSI speed.
 
+  *       	  - The clock for all peripherals is switched off, except the SRAM and FLASH.
 
+  *           - All GPIOs are in input floating state, except the JTAG pins which
 
+  *             are assigned to be used for debug purpose.
 
+  *        
+  *          Once the device started from reset, the user application has to:        
+  *           - Configure the clock source to be used to drive the System clock
 
+  *             (if the application needs higher frequency/performance)
 
+  *           - Configure the System clock frequency and Flash settings  
+  *           - Configure the AHB and APB busses prescalers
 
+  *           - Enable the clock for the peripheral(s) to be used
 
+  *           - Configure the clock source(s) for peripherals which clocks are not
 
+  *             derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)      
+  *                        
+  *  @endverbatim
 
+  *    
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup RCC 
+  * @brief RCC driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* ------------ RCC registers bit address in the alias region ----------- */
 
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
 
+/* --- CR Register ---*/
 
+/* Alias word address of HSION bit */
 
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
 
+#define HSION_BitNumber           0x00
 
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
 
+/* Alias word address of CSSON bit */
 
+#define CSSON_BitNumber           0x13
 
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
 
+/* Alias word address of PLLON bit */
 
+#define PLLON_BitNumber           0x18
 
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
 
+/* Alias word address of PLLI2SON bit */
 
+#define PLLI2SON_BitNumber        0x1A
 
+#define CR_PLLI2SON_BB            (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
 
+
 
+/* --- CFGR Register ---*/
 
+/* Alias word address of I2SSRC bit */
 
+#define CFGR_OFFSET               (RCC_OFFSET + 0x08)
 
+#define I2SSRC_BitNumber          0x17
 
+#define CFGR_I2SSRC_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
 
+
 
+/* --- BDCR Register ---*/
 
+/* Alias word address of RTCEN bit */
 
+#define BDCR_OFFSET               (RCC_OFFSET + 0x70)
 
+#define RTCEN_BitNumber           0x0F
 
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
 
+/* Alias word address of BDRST bit */
 
+#define BDRST_BitNumber           0x10
 
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
 
+/* --- CSR Register ---*/
 
+/* Alias word address of LSION bit */
 
+#define CSR_OFFSET                (RCC_OFFSET + 0x74)
 
+#define LSION_BitNumber           0x00
 
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
 
+/* ---------------------- RCC registers bit mask ------------------------ */
 
+/* CFGR register bit mask */
 
+#define CFGR_MCO2_RESET_MASK      ((uint32_t)0x07FFFFFF)
 
+#define CFGR_MCO1_RESET_MASK      ((uint32_t)0xF89FFFFF)
 
+
 
+/* RCC Flag Mask */
 
+#define FLAG_MASK                 ((uint8_t)0x1F)
 
+
 
+/* CR register byte 3 (Bits[23:16]) base address */
 
+#define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)
 
+
 
+/* CIR register byte 2 (Bits[15:8]) base address */
 
+#define CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
 
+
 
+/* CIR register byte 3 (Bits[23:16]) base address */
 
+#define CIR_BYTE3_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
 
+
 
+/* BDCR register base address */
 
+#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
 
+
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup RCC_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
 
+ *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+      Internal/external clocks, PLL, CSS and MCO configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the internal/external clocks,
 
+  PLLs, CSS and MCO pins.
 
+  
+  1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
 
+     the PLL as System clock source.
 
+
 
+  2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
 
+     clock source.
 
+
 
+  3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
 
+     through the PLL as System clock source. Can be used also as RTC clock source.
 
+
 
+  4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+
 
+  5. PLL (clocked by HSI or HSE), featuring two different output clocks:
 
+      - The first output is used to generate the high speed system clock (up to 168 MHz)
 
+      - The second output is used to generate the clock for the USB OTG FS (48 MHz),
 
+        the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
 
+
 
+  6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
+     high-quality audio performance on the I2S interface.
 
+  
+  7. CSS (Clock security system), once enable and if a HSE clock failure occurs 
+     (HSE used directly or through PLL as System clock source), the System clock
 
+     is automatically switched to HSI and an interrupt is generated if enabled. 
+     The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
+     exception vector.   
+
 
+  8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
 
+     clock (through a configurable prescaler) on PA8 pin.
 
+
 
+  9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
 
+     clock (through a configurable prescaler) on PC9 pin.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Resets the RCC clock configuration to the default reset state.
 
+  * @note   The default reset state of the clock configuration is given below:
 
+  *            - HSI ON and used as system clock source
 
+  *            - HSE, PLL and PLLI2S OFF
 
+  *            - AHB, APB1 and APB2 prescaler set to 1.
 
+  *            - CSS, MCO1 and MCO2 OFF
 
+  *            - All interrupts disabled
 
+  * @note   This function doesn't modify the configuration of the
 
+  *            - Peripheral clocks
 
+  *            - LSI, LSE and RTC clocks 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void RCC_DeInit(void)
 
+{
 
+  /* Set HSION bit */
 
+  RCC->CR |= (uint32_t)0x00000001;
 
+
 
+  /* Reset CFGR register */
 
+  RCC->CFGR = 0x00000000;
 
+
 
+  /* Reset HSEON, CSSON and PLLON bits */
 
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
 
+
 
+  /* Reset PLLCFGR register */
 
+  RCC->PLLCFGR = 0x24003010;
 
+
 
+  /* Reset HSEBYP bit */
 
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
 
+
 
+  /* Disable all interrupts */
 
+  RCC->CIR = 0x00000000;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the External High Speed oscillator (HSE).
 
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
 
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
 
+  *         is stable and can be used to clock the PLL and/or system clock.
 
+  * @note   HSE state can not be changed if it is used directly or through the
 
+  *         PLL as system clock. In this case, you have to select another source
 
+  *         of the system clock then change the HSE state (ex. disable it).
 
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
+  * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
 
+  *         was previously enabled you have to enable it again after calling this
 
+  *         function.    
+  * @param  RCC_HSE: specifies the new state of the HSE.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
 
+  *                              6 HSE oscillator clock cycles.
 
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
 
+  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
 
+  * @retval None
 
+  */
 
+void RCC_HSEConfig(uint8_t RCC_HSE)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_HSE(RCC_HSE));
 
+
 
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
 
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
 
+
 
+  /* Set the new HSE configuration -------------------------------------------*/
 
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
 
+}
 
+
 
+/**
 
+  * @brief  Waits for HSE start-up.
 
+  * @note   This functions waits on HSERDY flag to be set and return SUCCESS if 
+  *         this flag is set, otherwise returns ERROR if the timeout is reached 
+  *         and this flag is not set. The timeout value is defined by the constant
 
+  *         HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
 
+  *         on the HSE crystal used in your application. 
+  * @param  None
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: HSE oscillator is stable and ready to use
 
+  *          - ERROR: HSE oscillator not yet ready
 
+  */
 
+ErrorStatus RCC_WaitForHSEStartUp(void)
 
+{
 
+  __IO uint32_t startupcounter = 0;
 
+  ErrorStatus status = ERROR;
 
+  FlagStatus hsestatus = RESET;
 
+  /* Wait till HSE is ready and if Time out is reached exit */
 
+  do
 
+  {
 
+    hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
 
+    startupcounter++;
 
+  } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
 
+
 
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
 
+  {
 
+    status = SUCCESS;
 
+  }
 
+  else
 
+  {
 
+    status = ERROR;
 
+  }
 
+  return (status);
 
+}
 
+
 
+/**
 
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
 
+  * @note   The calibration is used to compensate for the variations in voltage
 
+  *         and temperature that influence the frequency of the internal HSI RC.
 
+  * @param  HSICalibrationValue: specifies the calibration trimming value.
 
+  *         This parameter must be a number between 0 and 0x1F.
 
+  * @retval None
 
+  */
 
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
 
+
 
+  tmpreg = RCC->CR;
 
+
 
+  /* Clear HSITRIM[4:0] bits */
 
+  tmpreg &= ~RCC_CR_HSITRIM;
 
+
 
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
 
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
 
+
 
+  /* Store the new value */
 
+  RCC->CR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
 
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
 
+  *         It is used (enabled by hardware) as system clock source after startup
 
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
 
+  *         of the HSE used directly or indirectly as system clock (if the Clock
 
+  *         Security System CSS is enabled).             
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
 
+  *         you have to select another source of the system clock then stop the HSI.  
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
 
+  *         flag to be set indicating that HSI clock is stable and can be used as
 
+  *         system clock source.  
+  * @param  NewState: new state of the HSI.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
 
+  *         clock cycles.  
+  * @retval None
 
+  */
 
+void RCC_HSICmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the External Low Speed oscillator (LSE).
 
+  * @note   As the LSE is in the Backup domain and write access is denied to
 
+  *         this domain after reset, you have to enable write access using 
+  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
 
+  *         (to be done once after reset).  
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
 
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
 
+  *         is stable and can be used to clock the RTC.
 
+  * @param  RCC_LSE: specifies the new state of the LSE.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
 
+  *                              6 LSE oscillator clock cycles.
 
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
 
+  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
 
+  * @retval None
 
+  */
 
+void RCC_LSEConfig(uint8_t RCC_LSE)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_LSE(RCC_LSE));
 
+
 
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
 
+  /* Reset LSEON bit */
 
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
 
+
 
+  /* Reset LSEBYP bit */
 
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
 
+
 
+  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
 
+  switch (RCC_LSE)
 
+  {
 
+    case RCC_LSE_ON:
 
+      /* Set LSEON bit */
 
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
 
+      break;
 
+    case RCC_LSE_Bypass:
 
+      /* Set LSEBYP and LSEON bits */
 
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
 
+      break;
 
+    default:
 
+      break;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
 
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
 
+  *         be used to clock the IWDG and/or the RTC.
 
+  * @note   LSI can not be disabled if the IWDG is running.  
+  * @param  NewState: new state of the LSI.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
 
+  *         clock cycles. 
+  * @retval None
 
+  */
 
+void RCC_LSICmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the main PLL clock source, multiplication and division factors.
 
+  * @note   This function must be used only when the main PLL is disabled.
 
+  *  
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
 
+  *            @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
 
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  *  
+  * @param  PLLM: specifies the division factor for PLL VCO input clock
 
+  *          This parameter must be a number between 0 and 63.
 
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
 
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
 
+  *         of 2 MHz to limit PLL jitter.
 
+  *  
+  * @param  PLLN: specifies the multiplication factor for PLL VCO output clock
 
+  *          This parameter must be a number between 192 and 432.
 
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
 
+  *         output frequency is between 192 and 432 MHz.
 
+  *   
+  * @param  PLLP: specifies the division factor for main system clock (SYSCLK)
 
+  *          This parameter must be a number in the range {2, 4, 6, or 8}.
 
+  * @note   You have to set the PLLP parameter correctly to not exceed 168 MHz on
 
+  *         the System clock frequency.
 
+  *  
+  * @param  PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
 
+  *          This parameter must be a number between 4 and 15.
 
+  * @note   If the USB OTG FS is used in your application, you have to set the
 
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
 
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
 
+  *         correctly.
 
+  *   
+  * @retval None
 
+  */
 
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
 
+  assert_param(IS_RCC_PLLM_VALUE(PLLM));
 
+  assert_param(IS_RCC_PLLN_VALUE(PLLN));
 
+  assert_param(IS_RCC_PLLP_VALUE(PLLP));
 
+  assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
 
+
 
+  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
 
+                 (PLLQ << 24);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the main PLL.
 
+  * @note   After enabling the main PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
 
+  *         be used as system clock source.
 
+  * @note   The main PLL can not be disabled if it is used as system clock source
 
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
 
+  * @param  NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_PLLCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the PLLI2S clock multiplication and division factors.
 
+  *  
+  * @note   This function must be used only when the PLLI2S is disabled.
 
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         RCC_PLLConfig function )  
+  *             
+  * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
 
+  *          This parameter must be a number between 192 and 432.
 
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between 192 and 432 MHz.
 
+  *    
+  * @param  PLLI2SR: specifies the division factor for I2S clock
 
+  *          This parameter must be a number between 2 and 7.
 
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
 
+  *         on the I2S clock frequency.
 
+  *   
+  * @retval None
 
+  */
 
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
 
+  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
 
+
 
+  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the PLLI2S. 
+  * @note   The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.  
+  * @param  NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_PLLI2SCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Clock Security System.
 
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
 
+  *         is automatically disabled and an interrupt is generated to inform the
 
+  *         software about the failure (Clock Security System Interrupt, CSSI),
 
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
+  * @param  NewState: new state of the Clock Security System.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the clock source to output on MCO1 pin(PA8).
 
+  * @note   PA8 should be configured in alternate function mode.
 
+  * @param  RCC_MCO1Source: specifies the clock source to output.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
 
+  *            @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
 
+  *            @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
 
+  *            @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
 
+  * @param  RCC_MCO1Div: specifies the MCO1 prescaler.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_MCO1Div_1: no division applied to MCO1 clock
 
+  *            @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
 
+  *            @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
 
+  *            @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
 
+  *            @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
 
+  * @retval None
 
+  */
 
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
 
+  assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
+
 
+  tmpreg = RCC->CFGR;
 
+
 
+  /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
 
+  tmpreg &= CFGR_MCO1_RESET_MASK;
 
+
 
+  /* Select MCO1 clock source and prescaler */
 
+  tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;  
+}
 
+
 
+/**
 
+  * @brief  Selects the clock source to output on MCO2 pin(PC9).
 
+  * @note   PC9 should be configured in alternate function mode.
 
+  * @param  RCC_MCO2Source: specifies the clock source to output.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
 
+  *            @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
 
+  *            @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
 
+  *            @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
 
+  * @param  RCC_MCO2Div: specifies the MCO2 prescaler.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_MCO2Div_1: no division applied to MCO2 clock
 
+  *            @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
 
+  *            @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
 
+  *            @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
 
+  *            @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
 
+  * @retval None
 
+  */
 
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
 
+  assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
 
+  
+  tmpreg = RCC->CFGR;
 
+  
+  /* Clear MCO2 and MCO2PRE[2:0] bits */
 
+  tmpreg &= CFGR_MCO2_RESET_MASK;
 
+
 
+  /* Select MCO2 clock source and prescaler */
 
+  tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;  
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
 
+ *  @brief   System, AHB and APB busses clocks configuration functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+             System, AHB and APB busses clocks configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the System, AHB, APB1 and 
+  APB2 busses clocks.
 
+  
+  1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
 
+     HSE and PLL.
 
+     The AHB clock (HCLK) is derived from System clock through configurable prescaler
 
+     and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
 
+     APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through 
+     configurable prescalers and used to clock the peripherals mapped on these busses.
 
+     You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
+
 
+@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
 
+       - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
 
+          from an external clock mapped on the I2S_CKIN pin. 
+          You have to use RCC_I2SCLKConfig() function to configure this clock. 
+       - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
 
+          divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
 
+          functions to configure this clock. 
+       - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
 
+          to work correctly, while the SDIO require a frequency equal or lower than
 
+          to 48. This clock is derived of the main PLL through PLLQ divider.
 
+       - IWDG clock which is always the LSI clock.
 
+       
+  2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.
 
+     Depending on the device voltage range, the maximum frequency should be 
+     adapted accordingly:
 
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
 
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
 
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
 
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96  | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |      NA        |120 < HCLK <= 138|112 < HCLK <= 120| 
+ +-------------------------------------------------------------------------------------+    
+   @note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
 
+         You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the system clock (SYSCLK).
 
+  * @note   The HSI is used (enabled by hardware) as system clock source after
 
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
 
+  *         of failure of the HSE used directly or indirectly as system clock
 
+  *         (if the Clock Security System CSS is enabled).
 
+  * @note   A switch from one clock source to another occurs only if the target
 
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         If a clock source which is not yet ready is selected, the switch will
 
+  *         occur when the clock source will be ready. 
+  *         You can use RCC_GetSYSCLKSource() function to know which clock is
 
+  *         currently used as system clock source. 
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
 
+  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
 
+  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
 
+  * @retval None
 
+  */
 
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
 
+
 
+  tmpreg = RCC->CFGR;
 
+
 
+  /* Clear SW[1:0] bits */
 
+  tmpreg &= ~RCC_CFGR_SW;
 
+
 
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
 
+  tmpreg |= RCC_SYSCLKSource;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the clock source used as system clock.
 
+  * @param  None
 
+  * @retval The clock source used as system clock. The returned value can be one
 
+  *         of the following:
 
+  *              - 0x00: HSI used as system clock
 
+  *              - 0x04: HSE used as system clock
 
+  *              - 0x08: PLL used as system clock
 
+  */
 
+uint8_t RCC_GetSYSCLKSource(void)
 
+{
 
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
 
+}
 
+
 
+/**
 
+  * @brief  Configures the AHB clock (HCLK).
 
+  * @note   Depending on the device voltage range, the software has to set correctly
 
+  *         these bits to ensure that HCLK not exceed the maximum allowed frequency
 
+  *         (for more details refer to section above
 
+  *           "CPU, AHB and APB busses clocks configuration functions")
 
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
+  *         the system clock (SYSCLK).
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
 
+  *            @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
 
+  *            @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
 
+  *            @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
 
+  *            @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
 
+  *            @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
 
+  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
 
+  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
 
+  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
 
+  * @retval None
 
+  */
 
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
 
+
 
+  tmpreg = RCC->CFGR;
 
+
 
+  /* Clear HPRE[3:0] bits */
 
+  tmpreg &= ~RCC_CFGR_HPRE;
 
+
 
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
 
+  tmpreg |= RCC_SYSCLK;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Configures the Low Speed APB clock (PCLK1).
 
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_HCLK_Div1:  APB1 clock = HCLK
 
+  *            @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2
 
+  *            @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4
 
+  *            @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8
 
+  *            @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
 
+  * @retval None
 
+  */
 
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
 
+
 
+  tmpreg = RCC->CFGR;
 
+
 
+  /* Clear PPRE1[2:0] bits */
 
+  tmpreg &= ~RCC_CFGR_PPRE1;
 
+
 
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
 
+  tmpreg |= RCC_HCLK;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the High Speed APB clock (PCLK2).
 
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_HCLK_Div1:  APB2 clock = HCLK
 
+  *            @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2
 
+  *            @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4
 
+  *            @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8
 
+  *            @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
 
+  * @retval None
 
+  */
 
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
 
+
 
+  tmpreg = RCC->CFGR;
 
+
 
+  /* Clear PPRE2[2:0] bits */
 
+  tmpreg &= ~RCC_CFGR_PPRE2;
 
+
 
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
 
+  tmpreg |= RCC_HCLK << 3;
 
+
 
+  /* Store the new value */
 
+  RCC->CFGR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the frequencies of different on chip clocks; SYSCLK, HCLK, 
+  *         PCLK1 and PCLK2.       
+  * 
+  * @note   The system frequency computed by this function is not the real 
+  *         frequency in the chip. It is calculated based on the predefined 
+  *         constant and the selected clock source:
 
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
 
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
 
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
 
+  *               16 MHz) but the real value may vary depending on the variations
 
+  *               in voltage and temperature.
 
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
 
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
 
+  *                frequency of the crystal used. Otherwise, this function may
 
+  *                have wrong result.
 
+  *                
+  * @note   The result of this function could be not correct when using fractional
 
+  *         value for HSE crystal.
 
+  *   
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
 
+  *          the clocks frequencies.
 
+  *     
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
 
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
 
+  *         must be called to update the structure's field. Otherwise, any
 
+  *         configuration based on this function will be incorrect.
 
+  *    
+  * @retval None
 
+  */
 
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
 
+{
 
+  uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 
+
 
+  /* Get SYSCLK source -------------------------------------------------------*/
 
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
 
+
 
+  switch (tmp)
 
+  {
 
+    case 0x00:  /* HSI used as system clock source */
 
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
 
+      break;
 
+    case 0x04:  /* HSE used as system clock  source */
 
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
 
+      break;
 
+    case 0x08:  /* PLL used as system clock  source */
 
+
 
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
 
+         SYSCLK = PLL_VCO / PLLP
 
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 
+      
+      if (pllsource != 0)
 
+      {
 
+        /* HSE used as PLL clock source */
 
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 
+      }
 
+      else
 
+      {
 
+        /* HSI used as PLL clock source */
 
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
 
+
 
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 
+      RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
 
+      break;
 
+    default:
 
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
 
+      break;
 
+  }
 
+  /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
 
+
 
+  /* Get HCLK prescaler */
 
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;
 
+  tmp = tmp >> 4;
 
+  presc = APBAHBPrescTable[tmp];
 
+  /* HCLK clock frequency */
 
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
 
+
 
+  /* Get PCLK1 prescaler */
 
+  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
 
+  tmp = tmp >> 10;
 
+  presc = APBAHBPrescTable[tmp];
 
+  /* PCLK1 clock frequency */
 
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
 
+
 
+  /* Get PCLK2 prescaler */
 
+  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
 
+  tmp = tmp >> 13;
 
+  presc = APBAHBPrescTable[tmp];
 
+  /* PCLK2 clock frequency */
 
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
 
+ *  @brief   Peripheral clocks configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Peripheral clocks configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the Peripheral clocks. 
+  
+  1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
 
+     
+  2. After restart from Reset or wakeup from STANDBY, all peripherals are off
 
+     except internal SRAM, Flash and JTAG. Before to start using a peripheral you
 
+     have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
 
+     , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
 
+
 
+  3. To reset the peripherals configuration (to the default state after device reset)
 
+     you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
+     RCC_APB1PeriphResetCmd() functions.
 
+     
+  4. To further reduce power consumption in SLEEP mode the peripheral clocks can
 
+     be disabled prior to executing the WFI or WFE instructions. You can do this
 
+     using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
 
+     RCC_APB1PeriphClockLPModeCmd() functions.  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the RTC clock (RTCCLK).
 
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
 
+  *         access is denied to this domain after reset, you have to enable write
 
+  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
 
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the  
+  *         Backup domain is reset using RCC_BackupResetCmd() function, or by
 
+  *         a Power On Reset (POR).
 
+  *    
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
 
+  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
 
+  *            @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
 
+  *                                            as RTC clock, where x:[2,31]
 
+  *  
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
 
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
 
+  *         However, when the HSE clock is used as RTC clock source, the RTC
 
+  *         cannot be used in STOP and STANDBY modes.    
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
 
+  *         RTC clock source).
 
+  *  
+  * @retval None
 
+  */
 
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
 
+
 
+  if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
 
+  { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
 
+    tmpreg = RCC->CFGR;
 
+
 
+    /* Clear RTCPRE[4:0] bits */
 
+    tmpreg &= ~RCC_CFGR_RTCPRE;
 
+
 
+    /* Configure HSE division factor for RTC clock */
 
+    tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
 
+
 
+    /* Store the new value */
 
+    RCC->CFGR = tmpreg;
 
+  }
 
+    
+  /* Select the RTC clock source */
 
+  RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the RTC clock.
 
+  * @note   This function must be used only after the RTC clock source was selected
 
+  *         using the RCC_RTCCLKConfig function.
 
+  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_RTCCLKCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases the Backup domain reset.
 
+  * @note   This function resets the RTC peripheral (including the backup registers)
 
+  *         and the RTC clock source selection in RCC_CSR register.
 
+  * @note   The BKPSRAM is not affected by this reset.    
+  * @param  NewState: new state of the Backup domain reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_BackupResetCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the I2S clock source (I2SCLK).
 
+  * @note   This function must be called before enabling the I2S APB clock.
 
+  * @param  RCC_I2SCLKSource: specifies the I2S clock source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
 
+  *            @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
 
+  *                                        used as I2S clock source
 
+  * @retval None
 
+  */
 
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
 
+
 
+  *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB1 peripheral clock.
 
+  * @note   After reset, the peripheral clock (used for registers read/write access)
 
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
 
+  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
 
+  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
 
+  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
 
+  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
 
+  *            @arg RCC_AHB1Periph_CRC:         CRC clock
 
+  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
 
+  *            @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
 
+  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
 
+  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
 
+  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
 
+  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
 
+
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB1ENR |= RCC_AHB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB1ENR &= ~RCC_AHB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB2 peripheral clock.
 
+  * @note   After reset, the peripheral clock (used for registers read/write access)
 
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
 
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
 
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
 
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
 
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB2ENR |= RCC_AHB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB2ENR &= ~RCC_AHB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB3 peripheral clock.
 
+  * @note   After reset, the peripheral clock (used for registers read/write access)
 
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
 
+  *          This parameter must be: RCC_AHB3Periph_FSMC
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB3ENR |= RCC_AHB3Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB3ENR &= ~RCC_AHB3Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
 
+  * @note   After reset, the peripheral clock (used for registers read/write access)
 
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
 
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
 
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
 
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
 
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
 
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
 
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
 
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
 
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
 
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
 
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
 
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
 
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
 
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
 
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
 
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
 
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
 
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
 
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
 
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
 
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
 
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
 
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB1ENR |= RCC_APB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB1ENR &= ~RCC_APB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
 
+  * @note   After reset, the peripheral clock (used for registers read/write access)
 
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
 
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
 
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
 
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
 
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
 
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
 
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
 
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
 
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
 
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
 
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
 
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
 
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
 
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB2ENR |= RCC_APB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB2ENR &= ~RCC_APB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases AHB1 peripheral reset.
 
+  * @param  RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB1Periph_GPIOA:   GPIOA clock
 
+  *            @arg RCC_AHB1Periph_GPIOB:   GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:   GPIOC clock
 
+  *            @arg RCC_AHB1Periph_GPIOD:   GPIOD clock
 
+  *            @arg RCC_AHB1Periph_GPIOE:   GPIOE clock
 
+  *            @arg RCC_AHB1Periph_GPIOF:   GPIOF clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOI:   GPIOI clock
 
+  *            @arg RCC_AHB1Periph_CRC:     CRC clock
 
+  *            @arg RCC_AHB1Periph_DMA1:    DMA1 clock
 
+  *            @arg RCC_AHB1Periph_DMA2:    DMA2 clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
 
+  *            @arg RCC_AHB1Periph_OTG_HS:  USB OTG HS clock
 
+  *                  
+  * @param  NewState: new state of the specified peripheral reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB1RSTR |= RCC_AHB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB1RSTR &= ~RCC_AHB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases AHB2 peripheral reset.
 
+  * @param  RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
 
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
 
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
 
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
 
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
 
+  * @param  NewState: new state of the specified peripheral reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB2RSTR |= RCC_AHB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB2RSTR &= ~RCC_AHB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases AHB3 peripheral reset.
 
+  * @param  RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
 
+  *          This parameter must be: RCC_AHB3Periph_FSMC
 
+  * @param  NewState: new state of the specified peripheral reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB3RSTR |= RCC_AHB3Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB3RSTR &= ~RCC_AHB3Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
 
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
 
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
 
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
 
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
 
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
 
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
 
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
 
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
 
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
 
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
 
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
 
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
 
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
 
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
 
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
 
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
 
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
 
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
 
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
 
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
 
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
 
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
 
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
 
+  * @param  NewState: new state of the specified peripheral reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB1RSTR |= RCC_APB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
 
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
 
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
 
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
 
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
 
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
 
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
 
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
 
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
 
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
 
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
 
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
 
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
 
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
 
+  * @param  NewState: new state of the specified peripheral reset.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB2RSTR |= RCC_APB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
 
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 
+  *         power consumption.
 
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 
+  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
 
+  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
 
+  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
 
+  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
 
+  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
 
+  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
 
+  *            @arg RCC_AHB1Periph_CRC:         CRC clock
 
+  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
 
+  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
 
+  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
 
+  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
 
+  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
 
+  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB1LPENR |= RCC_AHB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB1LPENR &= ~RCC_AHB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
 
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 
+  *           power consumption.
 
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 
+  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
 
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
 
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
 
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
 
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock  
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB2LPENR |= RCC_AHB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB2LPENR &= ~RCC_AHB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
 
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 
+  *         power consumption.
 
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 
+  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
 
+  *          This parameter must be: RCC_AHB3Periph_FSMC
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->AHB3LPENR |= RCC_AHB3Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->AHB3LPENR &= ~RCC_AHB3Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
 
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 
+  *         power consumption.
 
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
 
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
 
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
 
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
 
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
 
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
 
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
 
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
 
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
 
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
 
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
 
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
 
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
 
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
 
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
 
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
 
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
 
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
 
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
 
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
 
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
 
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
 
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB1LPENR |= RCC_APB1Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB1LPENR &= ~RCC_APB1Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
 
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
 
+  *         power consumption.
 
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
 
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
 
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
 
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
 
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
 
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
 
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
 
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
 
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
 
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
 
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
 
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
 
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
 
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
 
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
 
+  * @param  NewState: new state of the specified peripheral clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    RCC->APB2LPENR |= RCC_APB2Periph;
 
+  }
 
+  else
 
+  {
 
+    RCC->APB2LPENR &= ~RCC_APB2Periph;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RCC_Group4 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified RCC interrupts.
 
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
 
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
 
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
 
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
 
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
 
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  * @param  NewState: new state of the specified RCC interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_IT(RCC_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
 
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
 
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RCC flag is set or not.
 
+  * @param  RCC_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
 
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
 
+  *            @arg RCC_FLAG_PLLRDY: main PLL clock ready
 
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
 
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
 
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
 
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
 
+  *            @arg RCC_FLAG_PINRST: Pin reset
 
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset
 
+  *            @arg RCC_FLAG_SFTRST: Software reset
 
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
 
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset
 
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset
 
+  * @retval The new state of RCC_FLAG (SET or RESET).
 
+  */
 
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
 
+{
 
+  uint32_t tmp = 0;
 
+  uint32_t statusreg = 0;
 
+  FlagStatus bitstatus = RESET;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
 
+
 
+  /* Get the RCC register index */
 
+  tmp = RCC_FLAG >> 5;
 
+  if (tmp == 1)               /* The flag to check is in CR register */
 
+  {
 
+    statusreg = RCC->CR;
 
+  }
 
+  else if (tmp == 2)          /* The flag to check is in BDCR register */
 
+  {
 
+    statusreg = RCC->BDCR;
 
+  }
 
+  else                       /* The flag to check is in CSR register */
 
+  {
 
+    statusreg = RCC->CSR;
 
+  }
 
+
 
+  /* Get the flag position */
 
+  tmp = RCC_FLAG & FLAG_MASK;
 
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the flag status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the RCC reset flags.
 
+  *         The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,  RCC_FLAG_SFTRST,
 
+  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void RCC_ClearFlag(void)
 
+{
 
+  /* Set RMVF bit to clear the reset flags */
 
+  RCC->CSR |= RCC_CSR_RMVF;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
 
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
 
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
 
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
 
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
 
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
 
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
 
+  * @retval The new state of RCC_IT (SET or RESET).
 
+  */
 
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_GET_IT(RCC_IT));
 
+
 
+  /* Check the status of the specified RCC interrupt */
 
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the RCC_IT status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the RCC's interrupt pending bits.
 
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
 
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
 
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
 
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
 
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
 
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
 
+  * @retval None
 
+  */
 
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
 
+
 
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
 
+     pending bits */
 
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 405 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_rng.c
Ver arquivo 

@@ -0,0 +1,405 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rng.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+    * @brief This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:           
+  *           - Initialization and Configuration 
+  *           - Get 32 bit Random number      
+  *           - Interrupts and flags management       
+  *         
+  *  @verbatim
 
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
 
+  *          ===================================================================          
+  *          1. Enable The RNG controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
 
+  *              
+  *          2. Activate the RNG peripheral using RNG_Cmd() function.
 
+  *          
+  *          3. Wait until the 32 bit Random number Generator contains a valid 
+  *            random data (using polling/interrupt mode). For more details, 
+  *            refer to "Interrupts and flags management functions" module 
+  *            description.
 
+  *           
+  *          4. Get the 32 bit Random number using RNG_GetRandomNumber() function
 
+  *          
+  *          5. To get another 32 bit Random number, go to step 3.       
+  *
 
+  *         
+  *              
+  *  @endverbatim
 
+  *         
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_rng.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup RNG 
+  * @brief RNG driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup RNG_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup RNG_Group1 Initialization and Configuration functions
 
+ *  @brief    Initialization and Configuration functions 
+ *
 
+@verbatim    
+ ===============================================================================
 
+                      Initialization and Configuration functions
 
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the RNG peripheral
 
+   - Enable or disable the RNG peripheral
 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the RNG peripheral registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void RNG_DeInit(void)
 
+{
 
+  /* Enable RNG reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
 
+
 
+  /* Release RNG from reset state */
 
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the RNG peripheral.
 
+  * @param  NewState: new state of the RNG peripheral.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RNG_Cmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the RNG */
 
+    RNG->CR |= RNG_CR_RNGEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the RNG */
 
+    RNG->CR &= ~RNG_CR_RNGEN;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RNG_Group2 Get 32 bit Random number function
 
+ *  @brief    Get 32 bit Random number function 
+ *
 
+
 
+@verbatim    
+ ===============================================================================
 
+                      Get 32 bit Random number function
 
+ ===============================================================================  
+  This section provides a function allowing to get the 32 bit Random number  
+  
+  @note  Before to call this function you have to wait till DRDY flag is set,
 
+         using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. 
+   
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+
 
+/**
 
+  * @brief  Returns a 32-bit random number.
 
+  *   
+  * @note   Before to call this function you have to wait till DRDY (data ready)
 
+  *         flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
 
+  * @note   Each time the the Random number data is read (using RNG_GetRandomNumber()
 
+  *         function), the RNG_FLAG_DRDY flag is automatically cleared.
 
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted for as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable 
+  *         and enable the RNG peripheral (using RNG_Cmd() function) to 
+  *         reinitialize and restart the RNG.
 
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User have 
+  *         to check that the clock controller is correctly configured to provide
 
+  *         the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) 
+  *         function) . The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
 
+  *         
+  * @param  None
 
+  * @retval 32-bit random number.
 
+  */
 
+uint32_t RNG_GetRandomNumber(void)
 
+{
 
+  /* Return the 32 bit random number from the DR register */
 
+  return RNG->DR;
 
+}
 
+
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RNG_Group3 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides functions allowing to configure the RNG Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
 
+  
+  The RNG provides 3 Interrupts sources and 3 Flags:
 
+  
+  Flags :
 
+  ---------- 
+     1. RNG_FLAG_DRDY :  In the case of the RNG_DR register contains valid 
+                         random data. it is cleared by reading the valid data 
+                         (using RNG_GetRandomNumber() function).
 
+
 
+     2. RNG_FLAG_CECS : In the case of a seed error detection. 
+      
+     3. RNG_FLAG_SECS : In the case of a clock error detection.
 
+              
+
 
+  Interrupts :
 
+  ------------
 
+   if enabled, an RNG interrupt is pending :
 
+    
+   1.  In the case of the RNG_DR register contains valid random data. 
+       This interrupt source is cleared once the RNG_DR register has been read 
+       (using RNG_GetRandomNumber() function) until a new valid value is 
+       computed. 
+   
+   or 
+   2. In the case of a seed error : One of the following faulty sequences has 
+      been detected:
 
+      - More than 64 consecutive bits at the same value (0 or 1)
 
+      - More than 32 consecutive alternance of 0 and 1 (0101010101...01)
 
+      This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
 
+      function.
 
+   
+   or
 
+   3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) 
+      was not correctly detected (fPLL48CLK< fHCLK/16).
 
+      This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)
 
+      function.
 
+      @note In this case, User have to check that the clock controller is 
+            correctly configured to provide the RNG clock. 
+
 
+  Managing the RNG controller events :
 
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the RNG controller events: Polling mode or Interrupt mode.
 
+  
+  1.  In the Polling Mode it is advised to use the following functions:
 
+      - RNG_GetFlagStatus() : to check if flags events occur. 
+      - RNG_ClearFlag()     : to clear the flags events.
 
+  
+  @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only 
+        by reading the Random number data.      
+  
+  2.  In the Interrupt Mode it is advised to use the following functions:
 
+      - RNG_ITConfig()       : to enable or disable the interrupt source.
 
+      - RNG_GetITStatus()    : to check if Interrupt occurs.
 
+      - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                (corresponding Flag). 
+  
+
 
+@endverbatim
 
+  * @{
 
+  */ 
+
 
+/**
 
+  * @brief  Enables or disables the RNG interrupt.
 
+  * @note   The RNG provides 3 interrupt sources,
 
+  *           - Computed data is ready event (DRDY), and           
+  *           - Seed error Interrupt (SEI) and 
+  *           - Clock error Interrupt (CEI), 
+  *         all these interrupts sources are enabled by setting the IE bit in 
+  *         CR register. However, each interrupt have its specific status bit
 
+  *         (see RNG_GetITStatus() function) and clear bit except the DRDY event
 
+  *         (see RNG_ClearITPendingBit() function).
 
+  * @param  NewState: new state of the RNG interrupt.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RNG_ITConfig(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the RNG interrupt */
 
+    RNG->CR |= RNG_CR_IE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the RNG interrupt */
 
+    RNG->CR &= ~RNG_CR_IE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RNG flag is set or not.
 
+  * @param  RNG_FLAG: specifies the RNG flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RNG_FLAG_DRDY: Data Ready flag.
 
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
 
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
 
+  * @retval The new state of RNG_FLAG (SET or RESET).
 
+  */
 
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
 
+
 
+  /* Check the status of the specified RNG flag */
 
+  if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
 
+  {
 
+    /* RNG_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* RNG_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the RNG_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Clears the RNG flags.
 
+  * @param  RNG_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
 
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
 
+  * @note   RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. 
+  *         This flag is cleared only by reading the Random number data (using 
+  *         RNG_GetRandomNumber() function).                           
+  * @retval None
 
+  */
 
+void RNG_ClearFlag(uint8_t RNG_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
 
+  /* Clear the selected RNG flags */
 
+  RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
 
+  * @param  RNG_IT: specifies the RNG interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
 
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.                   
+  * @retval The new state of RNG_IT (SET or RESET).
 
+  */
 
+ITStatus RNG_GetITStatus(uint8_t RNG_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_RNG_GET_IT(RNG_IT));
 
+
 
+  /* Check the status of the specified RNG interrupt */
 
+  if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
 
+  {
 
+    /* RNG_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* RNG_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the RNG_IT status */
 
+  return bitstatus;
 
+}
 
+
 
+
 
+/**
 
+  * @brief  Clears the RNG interrupt pending bit(s).
 
+  * @param  RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
 
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.
 
+  * @retval None
 
+  */
 
+void RNG_ClearITPendingBit(uint8_t RNG_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RNG_IT(RNG_IT));
 
+
 
+  /* Clear the selected RNG interrupt pending bit */
 
+  RNG->SR = (uint8_t)~RNG_IT;
 
+}
 
+/**
 
+  * @}
 
+  */ 
+  
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 2759 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_rtc.c
Ver arquivo 

@@ -0,0 +1,2759 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_rtc.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
 
+  *           - Initialization
 
+  *           - Calendar (Time and Date) configuration
 
+  *           - Alarms (Alarm A and Alarm B) configuration
 
+  *           - WakeUp Timer configuration
 
+  *           - Daylight Saving configuration
 
+  *           - Output pin Configuration
 
+  *           - Coarse digital Calibration configuration
 
+  *           - Smooth digital Calibration configuration
 
+  *           - TimeStamp configuration
 
+  *           - Tampers configuration
 
+  *           - Backup Data Registers configuration
 
+  *           - Shift control synchronisation    
+  *           - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
 
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim
 
+  *
 
+  *          ===================================================================
 
+  *                               Backup Domain Operating Condition
 
+  *          ===================================================================
 
+  *          The real-time clock (RTC), the RTC backup registers, and the backup 
+  *          SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
+  *          VDD supply is powered off.
 
+  *          To retain the content of the RTC backup registers, backup SRAM, 
+  *          and supply the RTC when VDD is turned off, VBAT pin can be connected 
+  *          to an optional standby voltage supplied by a battery or by another 
+  *          source.
 
+  *
 
+  *          To allow the RTC to operate even when the main digital supply (VDD) 
+  *          is turned off, the VBAT pin powers the following blocks:
 
+  *            1 - The RTC
 
+  *            2 - The LSE oscillator
 
+  *            3 - The backup SRAM when the low power backup regulator is enabled
 
+  *            4 - PC13 to PC15 I/Os, plus PI8 I/O (when available)
 
+  *
 
+  *          When the backup domain is supplied by VDD (analog switch connected 
+  *          to VDD), the following functions are available:
 
+  *            1 - PC14 and PC15 can be used as either GPIO or LSE pins
 
+  *            2 - PC13 can be used as a GPIO or as the RTC_AF1 pin
 
+  *            3 - PI8 can be used as a GPIO or as the RTC_AF2 pin
 
+  *
 
+  *          When the backup domain is supplied by VBAT (analog switch connected 
+  *          to VBAT because VDD is not present), the following functions are available:
 
+  *            1 - PC14 and PC15 can be used as LSE pins only
 
+  *            2 - PC13 can be used as the RTC_AF1 pin 
+  *            3 - PI8 can be used as the RTC_AF2 pin
 
+  *
 
+  *          ===================================================================
 
+  *                                    Backup Domain Reset
 
+  *          ===================================================================
 
+  *          The backup domain reset sets all RTC registers and the RCC_BDCR 
+  *          register to their reset values. The BKPSRAM is not affected by this
 
+  *          reset. The only way of resetting the BKPSRAM is through the Flash 
+  *          interface by requesting a protection level change from 1 to 0.
 
+  *          A backup domain reset is generated when one of the following events
 
+  *          occurs:
 
+  *            1 - Software reset, triggered by setting the BDRST bit in the 
+  *                RCC Backup domain control register (RCC_BDCR). You can use the
 
+  *                RCC_BackupResetCmd().
 
+  *            2 - VDD or VBAT power on, if both supplies have previously been
 
+  *                powered off.
 
+  *
 
+  *          ===================================================================
 
+  *                                   Backup Domain Access
 
+  *          ===================================================================
 
+  *          After reset, the backup domain (RTC registers, RTC backup data 
+  *          registers and backup SRAM) is protected against possible unwanted 
+  *          write accesses. 
+  *          To enable access to the RTC Domain and RTC registers, proceed as follows:
 
+  *            - Enable the Power Controller (PWR) APB1 interface clock using the
 
+  *              RCC_APB1PeriphClockCmd() function.
 
+  *            - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
 
+  *            - Select the RTC clock source using the RCC_RTCCLKConfig() function.
 
+  *            - Enable RTC Clock using the RCC_RTCCLKCmd() function.
 
+  *
 
+  *          ===================================================================
 
+  *                                   RTC Driver: how to use it
 
+  *          ===================================================================
 
+  *            - Enable the RTC domain access (see description in the section above)
 
+  *            - Configure the RTC Prescaler (Asynchronous and Synchronous) and
 
+  *              RTC hour format using the RTC_Init() function.
 
+  *
 
+  *          Time and Date configuration
 
+  *          ===========================
 
+  *            - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
 
+  *              and RTC_SetDate() functions.
 
+  *            - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
 
+  *              functions.
 
+  *            - Use the RTC_DayLightSavingConfig() function to add or sub one
 
+  *              hour to the RTC Calendar.    
+  *
 
+  *          Alarm configuration
 
+  *          ===================
 
+  *            - To configure the RTC Alarm use the RTC_SetAlarm() function.
 
+  *            - Enable the selected RTC Alarm using the RTC_AlarmCmd() function
 
+  *            - To read the RTC Alarm, use the RTC_GetAlarm() function.
 
+  *            - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
 
+  *
 
+  *          RTC Wakeup configuration
 
+  *          ========================
 
+  *            - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
 
+  *              function.
 
+  *            - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+  *              function  
+  *            - Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+  *            - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+  *              function.
 
+  *
 
+  *          Outputs configuration
 
+  *          =====================
 
+  *          The RTC has 2 different outputs:
 
+  *            - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
 
+  *              and WaKeUp signals.          
+  *              To output the selected RTC signal on RTC_AF1 pin, use the 
+  *              RTC_OutputConfig() function.                
+  *            - AFO_CALIB: this output is 512Hz signal or 1Hz .  
+  *              To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
 
+  *              function.
 
+  *
 
+  *          Smooth digital Calibration configuration
 
+  *          =================================    
+  *            - Configure the RTC Original Digital Calibration Value and the corresponding
 
+  *              calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() 
+  *              function.
 
+  *
 
+  *          Coarse digital Calibration configuration
 
+  *          =================================
 
+  *            - Configure the RTC Coarse Calibration Value and the corresponding
 
+  *              sign using the RTC_CoarseCalibConfig() function.
 
+  *            - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() 
+  *              function  
+  *
 
+  *          TimeStamp configuration
 
+  *          =======================
 
+  *            - Configure the RTC_AF1 trigger and enables the RTC TimeStamp 
+  *              using the RTC_TimeStampCmd() function.
 
+  *            - To read the RTC TimeStamp Time and Date register, use the 
+  *              RTC_GetTimeStamp() function.
 
+  *            - To read the RTC TimeStamp SubSecond register, use the 
+  *              RTC_GetTimeStampSubSecond() function.
 
+  *            - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
 
+  *              or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in 
+  *              RTC_TAFCR register. You can use the  RTC_TamperPinSelection()
 
+  *              function to select the corresponding pin.     
+  *
 
+  *          Tamper configuration
 
+  *          ====================
 
+  *            - Enable the RTC Tamper using the RTC_TamperCmd() function.
 
+  *             - Configure the Tamper filter count using RTC_TamperFilterConfig()
 
+  *              function. 
+  *            - Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+  *              filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
 
+  *            - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
 
+  *              function.
 
+  *            - Configure the Tamper precharge or discharge duration using 
+  *              RTC_TamperPinsPrechargeDuration() function.
 
+  *            - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
 
+  *            - Enable the Time stamp on Tamper detection event using  
+  *              RTC_TSOnTamperDetecCmd() function.
 
+  *            - The TIMESTAMP alternate function can be mapped to either RTC_AF1 
+  *              or RTC_AF2 depending on the value of the TSINSEL bit in the 
+  *              RTC_TAFCR register. You can use the  RTC_TimeStampPinSelection()
 
+  *              function to select the corresponding pin. 
+  *
 
+  *          Backup Data Registers configuration
 
+  *          ===================================
 
+  *            - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
 
+  *              function.  
+  *            - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
 
+  *              function.
 
+  * 
+  *          ===================================================================
 
+  *                                  RTC and low power modes
 
+  *          ===================================================================
 
+  *           The MCU can be woken up from a low power mode by an RTC alternate 
+  *           function.
 
+  *           The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+  *           RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
 
+  *           These RTC alternate functions can wake up the system from the Stop 
+  *           and Standby lowpower modes.
 
+  *           The system can also wake up from low power modes without depending 
+  *           on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+  *           or the RTC wakeup events.
 
+  *           The RTC provides a programmable time base for waking up from the 
+  *           Stop or Standby mode at regular intervals.
 
+  *           Wakeup from STOP and Standby modes is possible only when the RTC 
+  *           clock source is LSE or LSI.
 
+  *
 
+  *          ===================================================================
 
+  *                            Selection of RTC_AF1 alternate functions
 
+  *          ===================================================================
 
+  *          The RTC_AF1 pin (PC13) can be used for the following purposes:
 
+  *            - AFO_ALARM output
 
+  *            - AFO_CALIB output
 
+  *            - AFI_TAMPER
 
+  *            - AFI_TIMESTAMP
 
+  *
 
+  * +-------------------------------------------------------------------------------------------------------------+
 
+  * |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
 
+  * |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
 
+  * |  and function   |          |          |           |              | selection  |  selection   |Configuration |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
 
+  * |   output OD     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      0       |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
 
+  * |   output PP     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      1       |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * | Calibration out |          |          |           |              |    Don't   |     Don't    |              |
 
+  * |   output PP     |     0    |    1     |Don't care | Don't care   |    care    |     care     |  Don't care  |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * |  TAMPER input   |          |          |           |              |            |     Don't    |              |
 
+  * |   floating      |     0    |    0     |     1     |      0       |      0     |     care     |  Don't care  |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * |  TIMESTAMP and  |          |          |           |              |            |              |              |
 
+  * |  TAMPER input   |     0    |    0     |     1     |      1       |      0     |      0       |  Don't care  |
 
+  * |   floating      |          |          |           |              |            |              |              |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * | TIMESTAMP input |          |          |           |              |    Don't   |              |              |
 
+  * |    floating     |     0    |    0     |     0     |      1       |    care    |      0       |  Don't care  |
 
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
 
+  * |  Standard GPIO  |     0    |    0     |     0     |      0       | Don't care |  Don't care  |  Don't care  |
 
+  * +-------------------------------------------------------------------------------------------------------------+
 
+  *
 
+  *
 
+  *          ===================================================================
 
+  *                            Selection of RTC_AF2 alternate functions
 
+  *          ===================================================================
 
+  *          The RTC_AF2 pin (PI8) can be used for the following purposes:
 
+  *            - AFI_TAMPER
 
+  *            - AFI_TIMESTAMP
 
+  *
 
+  * +---------------------------------------------------------------------------------------+
 
+  * |     Pin         |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
 
+  * |  configuration  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
 
+  * |  and function   |           |              | selection  |  selection   |Configuration |
 
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
 
+  * |  TAMPER input   |           |              |            |     Don't    |              |
 
+  * |   floating      |     1     |      0       |      1     |     care     |  Don't care  |
 
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
 
+  * |  TIMESTAMP and  |           |              |            |              |              |
 
+  * |  TAMPER input   |     1     |      1       |      1     |      1       |  Don't care  |
 
+  * |   floating      |           |              |            |              |              |
 
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
 
+  * | TIMESTAMP input |           |              |    Don't   |              |              |
 
+  * |    floating     |     0     |      1       |    care    |      1       |  Don't care  |
 
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
 
+  * |  Standard GPIO  |     0     |      0       | Don't care |  Don't care  |  Don't care  |
 
+  * +---------------------------------------------------------------------------------------+
 
+  * 
+  *
 
+  *  @endverbatim
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_rtc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup RTC 
+  * @brief RTC driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* Masks Definition */
 
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
 
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
 
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
 
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
 
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
 
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
 
+                                            RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
 
+
 
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00010000)
 
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00020000)
 
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00020000)
 
+#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
 
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
 
+
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup RTC_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/** @defgroup RTC_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                 Initialization and Configuration functions
 
+ ===============================================================================
 
+
 
+  This section provide functions allowing to initialize and configure the RTC
 
+  Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
 
+  Write protection, enter and exit the RTC initialization mode, RTC registers
 
+  synchronization check and reference clock detection enable.
 
+  
+  1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
 
+     split into 2 programmable prescalers to minimize power consumption.
 
+     - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
 
+     - When both prescalers are used, it is recommended to configure the asynchronous
 
+       prescaler to a high value to minimize consumption.
 
+
 
+  2. All RTC registers are Write protected. Writing to the RTC registers
 
+     is enabled by writing a key into the Write Protection register, RTC_WPR.
 
+
 
+  3. To Configure the RTC Calendar, user application should enter initialization
 
+     mode. In this mode, the calendar counter is stopped and its value can be 
+     updated. When the initialization sequence is complete, the calendar restarts 
+     counting after 4 RTCCLK cycles.
 
+
 
+  4. To read the calendar through the shadow registers after Calendar initialization,
 
+     calendar update or after wakeup from low power modes the software must first 
+     clear the RSF flag. The software must then wait until it is set again before 
+     reading the calendar, which means that the calendar registers have been 
+     correctly copied into the RTC_TR and RTC_DR shadow registers.
 
+     The RTC_WaitForSynchro() function implements the above software sequence 
+     (RSF clear and RSF check).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the RTC registers to their default reset values.
 
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
 
+  *         registers.       
+  * @param  None
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC registers are deinitialized
 
+  *          - ERROR: RTC registers are not deinitialized
 
+  */
 
+ErrorStatus RTC_DeInit(void)
 
+{
 
+  __IO uint32_t wutcounter = 0x00;
 
+  uint32_t wutwfstatus = 0x00;
 
+  ErrorStatus status = ERROR;
 
+  
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  }  
+  else
 
+  {
 
+    /* Reset TR, DR and CR registers */
 
+    RTC->TR = (uint32_t)0x00000000;
 
+    RTC->DR = (uint32_t)0x00002101;
 
+    /* Reset All CR bits except CR[2:0] */
 
+    RTC->CR &= (uint32_t)0x00000007;
 
+  
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
 
+    do
 
+    {
 
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
 
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
 
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
 
+    {
 
+      status = ERROR;
 
+    }
 
+    else
 
+    {
 
+      /* Reset all RTC CR register bits */
 
+      RTC->CR &= (uint32_t)0x00000000;
 
+      RTC->WUTR = (uint32_t)0x0000FFFF;
 
+      RTC->PRER = (uint32_t)0x007F00FF;
 
+      RTC->CALIBR = (uint32_t)0x00000000;
 
+      RTC->ALRMAR = (uint32_t)0x00000000;        
+      RTC->ALRMBR = (uint32_t)0x00000000;
 
+      RTC->SHIFTR = (uint32_t)0x00000000;
 
+      RTC->CALR = (uint32_t)0x00000000;
 
+      RTC->ALRMASSR = (uint32_t)0x00000000;
 
+      RTC->ALRMBSSR = (uint32_t)0x00000000;
 
+      
+      /* Reset ISR register and exit initialization mode */
 
+      RTC->ISR = (uint32_t)0x00000000;
 
+      
+      /* Reset Tamper and alternate functions configuration register */
 
+      RTC->TAFCR = 0x00000000;
 
+  
+      if(RTC_WaitForSynchro() == ERROR)
 
+      {
 
+        status = ERROR;
 
+      }
 
+      else
 
+      {
 
+        status = SUCCESS;      
+      }
 
+    }
 
+  }
 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;  
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
 
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
 
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC registers are initialized
 
+  *          - ERROR: RTC registers are not initialized  
+  */
 
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
 
+{
 
+  ErrorStatus status = ERROR;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
 
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
 
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  } 
+  else
 
+  {
 
+    /* Clear RTC CR FMT Bit */
 
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
 
+    /* Set RTC_CR register */
 
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
 
+  
+    /* Configure the RTC PRER */
 
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
 
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
 
+
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode();
 
+
 
+    status = SUCCESS;    
+  }
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each RTC_InitStruct member with its default value.
 
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
 
+  * @retval None
 
+  */
 
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
 
+{
 
+  /* Initialize the RTC_HourFormat member */
 
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
 
+    
+  /* Initialize the RTC_AsynchPrediv member */
 
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
 
+
 
+  /* Initialize the RTC_SynchPrediv member */
 
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the RTC registers write protection.
 
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
 
+  * @note   Writing a wrong key reactivates the write protection.
 
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RTC_WriteProtectionCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the write protection for RTC registers */
 
+    RTC->WPR = 0xFF;   
+  }
 
+  else
 
+  {
 
+    /* Disable the write protection for RTC registers */
 
+    RTC->WPR = 0xCA;
 
+    RTC->WPR = 0x53;    
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enters the RTC Initialization mode.
 
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC is in Init mode
 
+  *          - ERROR: RTC is not in Init mode  
+  */
 
+ErrorStatus RTC_EnterInitMode(void)
 
+{
 
+  __IO uint32_t initcounter = 0x00;
 
+  ErrorStatus status = ERROR;
 
+  uint32_t initstatus = 0x00;
 
+     
+  /* Check if the Initialization mode is set */
 
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
 
+  {
 
+    /* Set the Initialization mode */
 
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
 
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
 
+    do
 
+    {
 
+      initstatus = RTC->ISR & RTC_ISR_INITF;
 
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
 
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
 
+    {
 
+      status = SUCCESS;
 
+    }
 
+    else
 
+    {
 
+      status = ERROR;
 
+    }        
+  }
 
+  else
 
+  {
 
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
 
+
 
+/**
 
+  * @brief  Exits the RTC Initialization mode.
 
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
 
+  * @retval None
 
+  */
 
+void RTC_ExitInitMode(void)
 
+{ 
+  /* Exit Initialization mode */
 
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;  
+}
 
+
 
+/**
 
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
 
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC registers are synchronised
 
+  *          - ERROR: RTC registers are not synchronised
 
+  */
 
+ErrorStatus RTC_WaitForSynchro(void)
 
+{
 
+  __IO uint32_t synchrocounter = 0;
 
+  ErrorStatus status = ERROR;
 
+  uint32_t synchrostatus = 0x00;
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+    
+  /* Clear RSF flag */
 
+  RTC->ISR &= (uint32_t)RTC_RSF_MASK;
 
+    
+  /* Wait the registers to be synchronised */
 
+  do
 
+  {
 
+    synchrostatus = RTC->ISR & RTC_ISR_RSF;
 
+    synchrocounter++;  
+  } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
 
+    
+  if ((RTC->ISR & RTC_ISR_RSF) != RESET)
 
+  {
 
+    status = SUCCESS;
 
+  }
 
+  else
 
+  {
 
+    status = ERROR;
 
+  }        
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+    
+  return (status); 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the RTC reference clock detection.
 
+  * @param  NewState: new state of the RTC reference clock.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC reference clock detection is enabled
 
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
 
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
 
+{ 
+  ErrorStatus status = ERROR;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+    
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  } 
+  else
 
+  {  
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the RTC reference clock detection */
 
+      RTC->CR |= RTC_CR_REFCKON;   
+    }
 
+    else
 
+    {
 
+      /* Disable the RTC reference clock detection */
 
+      RTC->CR &= ~RTC_CR_REFCKON;    
+    }
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode();
 
+    
+    status = SUCCESS;
 
+  }
 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;  
+  
+  return status; 
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the Bypass Shadow feature.
 
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
 
+  * @param  NewState: new state of the Bypass Shadow feature.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+*/
 
+void RTC_BypassShadowCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the BYPSHAD bit */
 
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the BYPSHAD bit */
 
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
 
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group2 Time and Date configuration functions
 
+ *  @brief   Time and Date configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Time and Date configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the RTC Calendar
 
+  (Time and Date).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Set the RTC current time.
 
+  * @param  RTC_Format: specifies the format of the entered parameters.
 
+  *          This parameter can be  one of the following values:
 
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
 
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.     
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Time register is configured
 
+  *          - ERROR: RTC Time register is not configured
 
+  */
 
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  ErrorStatus status = ERROR;
 
+    
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+  
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
 
+    {
 
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
 
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
 
+    } 
+    else
 
+    {
 
+      RTC_TimeStruct->RTC_H12 = 0x00;
 
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
 
+    }
 
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
 
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
 
+  }
 
+  else
 
+  {
 
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
 
+    {
 
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
 
+      assert_param(IS_RTC_HOUR12(tmpreg));
 
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
 
+    {
 
+      RTC_TimeStruct->RTC_H12 = 0x00;
 
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
 
+    }
 
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
 
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
 
+  }
 
+  
+  /* Check the input parameters format */
 
+  if (RTC_Format != RTC_Format_BIN)
 
+  {
 
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
 
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
 
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
 
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }  
+  else
 
+  {
 
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
 
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
 
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
 
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
 
+  }  
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  } 
+  else
 
+  {
 
+    /* Set the RTC_TR register */
 
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
 
+
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode(); 
+
 
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
 
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
 
+    {
 
+      if (RTC_WaitForSynchro() == ERROR)
 
+      {
 
+        status = ERROR;
 
+      }
 
+      else
 
+      {
 
+        status = SUCCESS;
 
+      }
 
+    }
 
+    else
 
+    {
 
+      status = SUCCESS;
 
+    }
 
+  }
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+    
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each RTC_TimeStruct member with its default value
 
+  *         (Time = 00h:00min:00sec).
 
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
 
+  * @retval None
 
+  */
 
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
 
+{
 
+  /* Time = 00h:00min:00sec */
 
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
 
+  RTC_TimeStruct->RTC_Hours = 0;
 
+  RTC_TimeStruct->RTC_Minutes = 0;
 
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
 
+
 
+/**
 
+  * @brief  Get the RTC current Time.
 
+  * @param  RTC_Format: specifies the format of the returned parameters.
 
+  *          This parameter can be  one of the following values:
 
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
 
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.     
+  * @retval None
 
+  */
 
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+
 
+  /* Get the RTC_TR register */
 
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
 
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
 
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
 
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
 
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
 
+  /* Check the input parameters format */
 
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    /* Convert the structure parameters to Binary format */
 
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
 
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
 
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);   
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Gets the RTC current Calendar Subseconds value.
 
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
 
+  * @param  None
 
+  * @retval RTC current Calendar Subseconds value.
 
+  */
 
+uint32_t RTC_GetSubSecond(void)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Get subseconds values from the correspondent registers*/
 
+  tmpreg = (uint32_t)(RTC->SSR);
 
+  
+  /* Read DR register to unfroze calendar registers */
 
+  (void) (RTC->DR);
 
+  
+  return (tmpreg);
 
+}
 
+
 
+/**
 
+  * @brief  Set the RTC current date.
 
+  * @param  RTC_Format: specifies the format of the entered parameters.
 
+  *          This parameter can be  one of the following values:
 
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
 
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Date register is configured
 
+  *          - ERROR: RTC Date register is not configured
 
+  */
 
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  ErrorStatus status = ERROR;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+
 
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
 
+  {
 
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
 
+  }  
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
 
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
 
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
 
+  }
 
+  else
 
+  {
 
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
 
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
 
+    assert_param(IS_RTC_MONTH(tmpreg));
 
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
 
+    assert_param(IS_RTC_DATE(tmpreg));
 
+  }
 
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
 
+
 
+  /* Check the input parameters format */
 
+  if (RTC_Format != RTC_Format_BIN)
 
+  {
 
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
 
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
 
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
 
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
 
+  {
 
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
 
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
 
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
 
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
 
+  }
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  } 
+  else
 
+  {
 
+    /* Set the RTC_DR register */
 
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
 
+
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode(); 
+
 
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
 
+    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
 
+    {
 
+      if (RTC_WaitForSynchro() == ERROR)
 
+      {
 
+        status = ERROR;
 
+      }
 
+      else
 
+      {
 
+        status = SUCCESS;
 
+      }
 
+    }
 
+    else
 
+    {
 
+      status = SUCCESS;
 
+    }
 
+  }
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;   
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each RTC_DateStruct member with its default value
 
+  *         (Monday, January 01 xx00).
 
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
 
+  * @retval None
 
+  */
 
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
 
+{
 
+  /* Monday, January 01 xx00 */
 
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
 
+  RTC_DateStruct->RTC_Date = 1;
 
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
 
+  RTC_DateStruct->RTC_Year = 0;
 
+}
 
+
 
+/**
 
+  * @brief  Get the RTC current date. 
+  * @param  RTC_Format: specifies the format of the returned parameters.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
 
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.     
+  * @retval None
 
+  */
 
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+  
+  /* Get the RTC_TR register */
 
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
 
+  /* Fill the structure fields with the read parameters */
 
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
 
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
 
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
 
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
 
+
 
+  /* Check the input parameters format */
 
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    /* Convert the structure parameters to Binary format */
 
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
 
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
 
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group3 Alarms configuration functions
 
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              Alarms (Alarm A and Alarm B) configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the RTC Alarms.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Set the specified RTC Alarm.
 
+  * @note   The Alarm register can only be written when the corresponding Alarm
 
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Alarm_A: to select Alarm A
 
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.     
+  * @retval None
 
+  */
 
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
 
+  assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
 
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
 
+
 
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
 
+    {
 
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
 
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
 
+    } 
+    else
 
+    {
 
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
 
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
 
+    }
 
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
 
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
 
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
 
+    {
 
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
 
+    }
 
+    else
 
+    {
 
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
 
+    }
 
+  }
 
+  else
 
+  {
 
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
 
+    {
 
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
 
+      assert_param(IS_RTC_HOUR12(tmpreg));
 
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
 
+    } 
+    else
 
+    {
 
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
 
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
 
+    }
 
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
 
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
 
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
 
+    {
 
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
 
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
 
+    else
 
+    {
 
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
 
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
 
+
 
+  /* Check the input parameters format */
 
+  if (RTC_Format != RTC_Format_BIN)
 
+  {
 
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
 
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
 
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
 
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
 
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
 
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
 
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
 
+  {
 
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
 
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
 
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
 
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
 
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
 
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
 
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  } 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Configure the Alarm register */
 
+  if (RTC_Alarm == RTC_Alarm_A)
 
+  {
 
+    RTC->ALRMAR = (uint32_t)tmpreg;
 
+  }
 
+  else
 
+  {
 
+    RTC->ALRMBR = (uint32_t)tmpreg;
 
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;   
+}
 
+
 
+/**
 
+  * @brief  Fills each RTC_AlarmStruct member with its default value
 
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
 
+  *         all fields are masked).
 
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
 
+  *         will be initialized.
 
+  * @retval None
 
+  */
 
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
 
+{
 
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
 
+
 
+  /* Alarm Date Settings : Date = 1st day of the month */
 
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
 
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
 
+
 
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
 
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
 
+}
 
+
 
+/**
 
+  * @brief  Get the RTC Alarm value and masks.
 
+  * @param  RTC_Format: specifies the format of the output parameters.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
 
+  * @param  RTC_Alarm: specifies the alarm to be read.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Alarm_A: to select Alarm A
 
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
 
+  */
 
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
 
+  /* Get the RTC_ALRMxR register */
 
+  if (RTC_Alarm == RTC_Alarm_A)
 
+  {
 
+    tmpreg = (uint32_t)(RTC->ALRMAR);
 
+  }
 
+  else
 
+  {
 
+    tmpreg = (uint32_t)(RTC->ALRMBR);
 
+  }
 
+
 
+  /* Fill the structure with the read parameters */
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
 
+                                                     RTC_ALRMAR_HU)) >> 16);
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
 
+                                                     RTC_ALRMAR_MNU)) >> 8);
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
 
+                                                     RTC_ALRMAR_SU));
 
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
 
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
 
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
 
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
 
+
 
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
 
+                                                        RTC_AlarmTime.RTC_Hours);
 
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
 
+                                                        RTC_AlarmTime.RTC_Minutes);
 
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
 
+                                                        RTC_AlarmTime.RTC_Seconds);
 
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified RTC Alarm.
 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RTC_Alarm_A: to select Alarm A
 
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  NewState: new state of the specified alarm.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Alarm is enabled/disabled
 
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
 
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
 
+{
 
+  __IO uint32_t alarmcounter = 0x00;
 
+  uint32_t alarmstatus = 0x00;
 
+  ErrorStatus status = ERROR;
 
+    
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Configure the Alarm state */
 
+  if (NewState != DISABLE)
 
+  {
 
+    RTC->CR |= (uint32_t)RTC_Alarm;
 
+
 
+    status = SUCCESS;    
+  }
 
+  else
 
+  { 
+    /* Disable the Alarm in RTC_CR register */
 
+    RTC->CR &= (uint32_t)~RTC_Alarm;
 
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
 
+    do
 
+    {
 
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
 
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
 
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
 
+    {
 
+      status = ERROR;
 
+    } 
+    else
 
+    {
 
+      status = SUCCESS;
 
+    }        
+  } 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.*
 
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_Alarm_A: to select Alarm A
 
+  *     @arg RTC_Alarm_B: to select Alarm B
 
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
 
+  *   This parameter can be a value from 0 to 0x00007FFF.
 
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
 
+  *   This parameter can be any combination of the following values:
 
+  *     @arg RTC_AlarmSubSecondMask_All    : All Alarm SS fields are masked.
 
+  *                                          There is no comparison on sub seconds for Alarm.
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
 
+  *                                          Only SS[0] is compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
 
+  *                                          Only SS[1:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
 
+  *                                          Only SS[2:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
 
+  *                                          Only SS[3:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
 
+  *                                          Only SS[4:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
 
+  *                                          Only SS[5:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
 
+  *                                          Only SS[6:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
 
+  *                                          Only SS[7:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
 
+  *                                          Only SS[8:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
 
+  *                                          Only SS[9:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
 
+  *                                          Only SS[10:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
 
+  *                                          Only SS[11:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
 
+  *                                          Only SS[12:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_SS14   : SS[14] is don't care in Alarm comparison.
 
+  *                                          Only SS[13:0] are compared
 
+  *     @arg RTC_AlarmSubSecondMask_None   : SS[14:0] are compared and must match
 
+  *                                          to activate alarm
 
+  * @retval None
 
+  */
 
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
 
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
 
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
 
+  
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
 
+  tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
 
+  
+  if (RTC_Alarm == RTC_Alarm_A)
 
+  {
 
+    /* Configure the AlarmA SubSecond register */
 
+    RTC->ALRMASSR = tmpreg;
 
+  }
 
+  else
 
+  {
 
+    /* Configure the Alarm B SubSecond register */
 
+    RTC->ALRMBSSR = tmpreg;
 
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;
 
+
 
+}
 
+
 
+/**
 
+  * @brief  Gets the RTC Alarm Subseconds value.
 
+  * @param  RTC_Alarm: specifies the alarm to be read.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_Alarm_A: to select Alarm A
 
+  *     @arg RTC_Alarm_B: to select Alarm B
 
+  * @param  None
 
+  * @retval RTC Alarm Subseconds value.
 
+  */
 
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Get the RTC_ALRMxR register */
 
+  if (RTC_Alarm == RTC_Alarm_A)
 
+  {
 
+    tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
 
+  }
 
+  else
 
+  {
 
+    tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
 
+  } 
+  
+  return (tmpreg);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
 
+ *  @brief   WakeUp Timer configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                     WakeUp Timer configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the RTC WakeUp.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the RTC Wakeup clock source.
 
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
 
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).      
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
 
+  *            @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
 
+  *            @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
 
+  *            @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
 
+  *            @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
 
+  *            @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
 
+  * @retval None
 
+  */
 
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Clear the Wakeup Timer clock source bits in CR register */
 
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
 
+
 
+  /* Configure the clock source */
 
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Configures the RTC Wakeup counter.
 
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp
 
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).        
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
 
+  *          This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
 
+  */
 
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
 
+  
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /* Configure the Wakeup Timer counter */
 
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Returns the RTC WakeUp timer counter value.
 
+  * @param  None
 
+  * @retval The RTC WakeUp Counter value.
 
+  */
 
+uint32_t RTC_GetWakeUpCounter(void)
 
+{
 
+  /* Get the counter value */
 
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
 
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the RTC WakeUp timer.
 
+  * @param  NewState: new state of the WakeUp timer.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
 
+{
 
+  __IO uint32_t wutcounter = 0x00;
 
+  uint32_t wutwfstatus = 0x00;
 
+  ErrorStatus status = ERROR;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Wakeup Timer */
 
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
 
+    status = SUCCESS;    
+  }
 
+  else
 
+  {
 
+    /* Disable the Wakeup Timer */
 
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
 
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
 
+    do
 
+    {
 
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
 
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
 
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
 
+    {
 
+      status = ERROR;
 
+    }
 
+    else
 
+    {
 
+      status = SUCCESS;
 
+    }    
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
 
+ *  @brief   Daylight Saving configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Daylight Saving configuration functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the RTC DayLight Saving.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Adds or substract one hour from the current time.
 
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
 
+  *            @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
 
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                            in CR register to store the operation.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset
 
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set
 
+  * @retval None
 
+  */
 
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
 
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Clear the bits to be configured */
 
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
 
+
 
+  /* Configure the RTC_CR register */
 
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Returns the RTC Day Light Saving stored operation.
 
+  * @param  None
 
+  * @retval RTC Day Light Saving stored operation.
 
+  *          - RTC_StoreOperation_Reset
 
+  *          - RTC_StoreOperation_Set       
+  */
 
+uint32_t RTC_GetStoreOperation(void)
 
+{
 
+  return (RTC->CR & RTC_CR_BCK);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group6 Output pin Configuration function
 
+ *  @brief   Output pin Configuration function 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Output pin Configuration function
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to configure the RTC Output source.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the RTC output source (AFO_ALARM).
 
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Output_Disable: No output selected
 
+  *            @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
 
+  *            @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
 
+  *            @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
 
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *          This parameter can be one of the following:
 
+  *            @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
 
+  *            @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
 
+  * @retval None
 
+  */
 
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
 
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Clear the bits to be configured */
 
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
 
+
 
+  /* Configure the output selection and polarity */
 
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
 
+ *  @brief   Coarse Calibration configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Digital Calibration configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the Coarse calibration parameters.
 
+  * @param  RTC_CalibSign: specifies the sign of the coarse calibration value.
 
+  *          This parameter can be  one of the following values:
 
+  *            @arg RTC_CalibSign_Positive: The value sign is positive 
+  *            @arg RTC_CalibSign_Negative: The value sign is negative
 
+  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
 
+  *    
+  * @note   This Calibration value should be between 0 and 63 when using negative
 
+  *         sign with a 2-ppm step.
 
+  *           
+  * @note   This Calibration value should be between 0 and 126 when using positive
 
+  *         sign with a 4-ppm step.
 
+  *           
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Coarse calibration are initialized
 
+  *          - ERROR: RTC Coarse calibration are not initialized     
+  */
 
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
 
+{
 
+  ErrorStatus status = ERROR;
 
+   
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
 
+  assert_param(IS_RTC_CALIB_VALUE(Value)); 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status = ERROR;
 
+  } 
+  else
 
+  {
 
+    /* Set the coarse calibration value */
 
+    RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode();
 
+    
+    status = SUCCESS;
 
+  } 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the Coarse calibration process.
 
+  * @param  NewState: new state of the Coarse calibration.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Coarse calibration are enabled/disabled
 
+  *          - ERROR: RTC Coarse calibration are not enabled/disabled    
+  */
 
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
 
+{
 
+  ErrorStatus status = ERROR;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /* Set Initialization mode */
 
+  if (RTC_EnterInitMode() == ERROR)
 
+  {
 
+    status =  ERROR;
 
+  }
 
+  else
 
+  {
 
+    if (NewState != DISABLE)
 
+    {
 
+      /* Enable the Coarse Calibration */
 
+      RTC->CR |= (uint32_t)RTC_CR_DCE;
 
+    }
 
+    else
 
+    { 
+      /* Disable the Coarse Calibration */
 
+      RTC->CR &= (uint32_t)~RTC_CR_DCE;
 
+    }
 
+    /* Exit Initialization mode */
 
+    RTC_ExitInitMode();
 
+    
+    status = SUCCESS;
 
+  } 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+  
+  return status;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the RTC clock to be output through the relative pin.
 
+  * @param  NewState: new state of the digital calibration Output.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RTC_CalibOutputCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the RTC clock output */
 
+    RTC->CR |= (uint32_t)RTC_CR_COE;
 
+  }
 
+  else
 
+  { 
+    /* Disable the RTC clock output */
 
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
 
+  }
 
+  
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
 
+  * @param  RTC_CalibOutput : Select the Calibration output Selection .
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *     @arg RTC_CalibOutput_1Hz  : A signal has a regular waveform at 1Hz.
 
+  * @retval None
 
+*/
 
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /*clear flags before config*/
 
+  RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
 
+
 
+  /* Configure the RTC_CR register */
 
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the Smooth Calibration Settings.
 
+  * @param  RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
 
+  *   This parameter can be can be one of the following values:
 
+  *     @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
 
+  *     @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
 
+  *     @arg RTC_SmoothCalibPeriod_8sec  : The smooth calibartion periode is 8s.
 
+  * @param  RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_SmoothCalibPlusPulses_Set  : Add one RTCCLK puls every 2**11 pulses.
 
+  *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
 
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
 
+  *   This parameter can be one any value from 0 to 0x000001FF.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Calib registers are configured
 
+  *          - ERROR: RTC Calib registers are not configured
 
+*/
 
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
 
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
 
+{
 
+  ErrorStatus status = ERROR;
 
+  uint32_t recalpfcount = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
 
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
 
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /* check if a calibration is pending*/
 
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
 
+  {
 
+    /* wait until the Calibration is completed*/
 
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
 
+    {
 
+      recalpfcount++;
 
+    }
 
+  }
 
+
 
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
 
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
 
+  {
 
+    /* Configure the Smooth calibration settings */
 
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
 
+
 
+    status = SUCCESS;
 
+  }
 
+  else
 
+  {
 
+    status = ERROR;
 
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;
 
+  
+  return (ErrorStatus)(status);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup RTC_Group8 TimeStamp configuration functions
 
+ *  @brief   TimeStamp configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       TimeStamp configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
 
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
 
+  *          This parameter can be one of the following:
 
+  *            @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                    edge of the related pin.
 
+  *            @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                     falling edge of the related pin.
 
+  * @param  NewState: new state of the TimeStamp.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Get the RTC_CR register and clear the bits to be configured */
 
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
 
+
 
+  /* Get the new configuration */
 
+  if (NewState != DISABLE)
 
+  {
 
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
 
+  }
 
+  else
 
+  {
 
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
 
+  }
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  /* Configure the Time Stamp TSEDGE and Enable bits */
 
+  RTC->CR = (uint32_t)tmpreg;
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Get the RTC TimeStamp value and masks.
 
+  * @param  RTC_Format: specifies the format of the output parameters.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
 
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
 
+  */
 
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
 
+{
 
+  uint32_t tmptime = 0, tmpdate = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_FORMAT(RTC_Format));
 
+
 
+  /* Get the TimeStamp time and date registers values */
 
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
 
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
 
+
 
+  /* Fill the Time structure fields with the read parameters */
 
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
 
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
 
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
 
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
 
+  /* Fill the Date structure fields with the read parameters */
 
+  RTC_StampDateStruct->RTC_Year = 0;
 
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
 
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
 
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
 
+
 
+  /* Check the input parameters format */
 
+  if (RTC_Format == RTC_Format_BIN)
 
+  {
 
+    /* Convert the Time structure parameters to Binary format */
 
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
 
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
 
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
 
+
 
+    /* Convert the Date structure parameters to Binary format */
 
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
 
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
 
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Get the RTC timestamp Subseconds value.
 
+  * @param  None
 
+  * @retval RTC current timestamp Subseconds value.
 
+  */
 
+uint32_t RTC_GetTimeStampSubSecond(void)
 
+{
 
+  /* Get timestamp subseconds values from the correspondent registers */
 
+  return (uint32_t)(RTC->TSSSR);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group9 Tampers configuration functions
 
+ *  @brief   Tampers configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       Tampers configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the select Tamper pin edge.
 
+  * @param  RTC_Tamper: Selected tamper pin.
 
+  *          This parameter can be RTC_Tamper_1.
 
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *         stimulates tamper event. 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
 
+  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
 
+  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
 
+  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
 
+  * @retval None
 
+  */
 
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
 
+ 
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
 
+  {  
+    /* Configure the RTC_TAFCR register */
 
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
+  }
 
+  else
 
+  { 
+    /* Configure the RTC_TAFCR register */
 
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the Tamper detection.
 
+  * @param  RTC_Tamper: Selected tamper pin.
 
+  *          This parameter can be RTC_Tamper_1.
 
+  * @param  NewState: new state of the tamper pin.
 
+  *          This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
 
+  */
 
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected Tamper pin */
 
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected Tamper pin */
 
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
 
+
 
+/**
 
+  * @brief  Configures the Tampers Filter.
 
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
 
+  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                    samples at the active level 
+  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                    samples at the active level
 
+  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                    samples at the active level 
+  * @retval None
 
+  */
 
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
 
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
 
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
 
+
 
+  /* Configure the RTC_TAFCR register */
 
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the Tampers Sampling Frequency.
 
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 32768
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 16384
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 8192
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 4096
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 2048
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 1024
 
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 512  
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
 
+  *                                           with a frequency =  RTCCLK / 256  
+  * @retval None
 
+  */
 
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
 
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
 
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
 
+
 
+  /* Configure the RTC_TAFCR register */
 
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the Tampers Pins input Precharge Duration.
 
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
 
+  *         Precharge Duration.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
 
+  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
 
+  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
+  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
 
+  * @retval None
 
+  */
 
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
 
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
 
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
 
+
 
+  /* Configure the RTC_TAFCR register */
 
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
 
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+   
+  if (NewState != DISABLE)
 
+  {
 
+    /* Save timestamp on tamper detection event */
 
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
 
+  }
 
+  else
 
+  {
 
+    /* Tamper detection does not cause a timestamp to be saved */
 
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the Precharge of Tamper pin.
 
+  * @param  NewState: new state of tamper pull up.
 
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
 
+  */
 
+void RTC_TamperPullUpCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+ if (NewState != DISABLE)
 
+  {
 
+    /* Enable precharge of the selected Tamper pin */
 
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
 
+  else
 
+  {
 
+    /* Disable precharge of the selected Tamper pin */
 
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
 
+ *  @brief   Backup Data Registers configuration functions  
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       Backup Data Registers configuration functions 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Writes a data in a specified RTC Backup data register.
 
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
 
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.
 
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
 
+  */
 
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
 
+
 
+  tmp = RTC_BASE + 0x50;
 
+  tmp += (RTC_BKP_DR * 4);
 
+
 
+  /* Write the specified register */
 
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
 
+}
 
+
 
+/**
 
+  * @brief  Reads data from the specified RTC Backup data Register.
 
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
 
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
 
+  */
 
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
 
+
 
+  tmp = RTC_BASE + 0x50;
 
+  tmp += (RTC_BKP_DR * 4);
 
+  
+  /* Read the specified register */
 
+  return (*(__IO uint32_t *)tmp);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
 
+ *  @brief   RTC Tamper and TimeStamp Pins Selection and Output Type Config 
+ *           configuration functions  
+ *
 
+@verbatim   
+ ===============================================================================
 
+  RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration 
+  functions 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Selects the RTC Tamper Pin.
 
+  * @param  RTC_TamperPin: specifies the RTC Tamper Pin.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
 
+  *            @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.    
+  * @retval None
 
+  */
 
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin));
 
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL);
 
+  RTC->TAFCR |= (uint32_t)(RTC_TamperPin);  
+}
 
+
 
+/**
 
+  * @brief  Selects the RTC TimeStamp Pin.
 
+  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
 
+  *            @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.    
+  * @retval None
 
+  */
 
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
 
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL);
 
+  RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin);  
+}
 
+
 
+/**
 
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
 
+  *            @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
 
+  */
 
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
 
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
 
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group12 Shift control synchronisation functions
 
+ *  @brief   Shift control synchronisation functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Shift control synchronisation functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the Synchronization Shift Control Settings.
 
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
 
+  *   This parameter can be one of the following values :
 
+  *     @arg RTC_ShiftAdd1S_Set  : Add one second to the clock calendar. 
+  *     @arg RTC_ShiftAdd1S_Reset: No effect.
 
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
 
+  *         This parameter can be one any value from 0 to 0x7FFF.
 
+  * @retval An ErrorStatus enumeration value:
 
+  *          - SUCCESS: RTC Shift registers are configured
 
+  *          - ERROR: RTC Shift registers are not configured
 
+*/
 
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
 
+{
 
+  ErrorStatus status = ERROR;
 
+  uint32_t shpfcount = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
 
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+  
+  /* Check if a Shift is pending*/
 
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
 
+  {
 
+    /* Wait until the shift is completed*/
 
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
 
+    {
 
+      shpfcount++;
 
+    }
 
+  }
 
+
 
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
 
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
 
+  {
 
+    /* check if the reference clock detection is disabled */
 
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
 
+    {
 
+      /* Configure the Shift settings */
 
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
 
+    
+      if(RTC_WaitForSynchro() == ERROR)
 
+      {
 
+        status = ERROR;
 
+      }
 
+      else
 
+      {
 
+        status = SUCCESS;
 
+      }
 
+    }
 
+    else
 
+    {
 
+      status = ERROR;
 
+    }
 
+  }
 
+  else
 
+  {
 
+    status = ERROR;
 
+  }
 
+
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF;
 
+  
+  return (ErrorStatus)(status);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup RTC_Group13 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions  
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       Interrupts and flags management functions
 
+ ===============================================================================  
+ All RTC interrupts are connected to the EXTI controller.
 
+ 
+ - To enable the RTC Alarm interrupt, the following sequence is required:
 
+   - Configure and enable the EXTI Line 17 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
 
+   - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
 
+     function.
 
+   - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
 
+     the RTC_SetAlarm() and RTC_AlarmCmd() functions.
 
+
 
+ - To enable the RTC Wakeup interrupt, the following sequence is required:
 
+   - Configure and enable the EXTI Line 22 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
 
+   - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()
 
+     function.
 
+   - Configure the RTC to generate the RTC wakeup timer event using the 
+     RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
 
+
 
+ - To enable the RTC Tamper interrupt, the following sequence is required:
 
+   - Configure and enable the EXTI Line 21 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
 
+   - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
 
+     function.
 
+   - Configure the RTC to detect the RTC tamper event using the 
+     RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
 
+
 
+ - To enable the RTC TimeStamp interrupt, the following sequence is required:
 
+   - Configure and enable the EXTI Line 21 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
 
+   - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
 
+     function.
 
+   - Configure the RTC to detect the RTC time-stamp event using the 
+     RTC_TimeStampCmd() functions.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified RTC interrupts.
 
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RTC_IT_TS:  Time Stamp interrupt mask
 
+  *            @arg RTC_IT_WUT:  WakeUp Timer interrupt mask
 
+  *            @arg RTC_IT_ALRB:  Alarm B interrupt mask
 
+  *            @arg RTC_IT_ALRA:  Alarm A interrupt mask
 
+  *            @arg RTC_IT_TAMP: Tamper event interrupt mask
 
+  * @param  NewState: new state of the specified RTC interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* Disable the write protection for RTC registers */
 
+  RTC->WPR = 0xCA;
 
+  RTC->WPR = 0x53;
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Configure the Interrupts in the RTC_CR register */
 
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
 
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
 
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
 
+  }
 
+  else
 
+  {
 
+    /* Configure the Interrupts in the RTC_CR register */
 
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
 
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
 
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
 
+  }
 
+  /* Enable the write protection for RTC registers */
 
+  RTC->WPR = 0xFF; 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RTC flag is set or not.
 
+  * @param  RTC_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_FLAG_RECALPF: RECALPF event flag.
 
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
 
+  *            @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
 
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
 
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
 
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
 
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
 
+  *            @arg RTC_FLAG_INITF: Initialization mode flag
 
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
 
+  *            @arg RTC_FLAG_INITS: Registers Configured flag
 
+  *            @arg RTC_FLAG_SHPF: Shift operation pending flag.
 
+  *            @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
 
+  *            @arg RTC_FLAG_ALRBWF: Alarm B Write flag
 
+  *            @arg RTC_FLAG_ALRAWF: Alarm A write flag
 
+  * @retval The new state of RTC_FLAG (SET or RESET).
 
+  */
 
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
 
+  
+  /* Get all the flags */
 
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
 
+  
+  /* Return the status of the flag */
 
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the RTC's pending flags.
 
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
 
+  *            @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
 
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
 
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
 
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
 
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
 
+  * @retval None
 
+  */
 
+void RTC_ClearFlag(uint32_t RTC_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
 
+
 
+  /* Clear the Flags in the RTC_ISR register */
 
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));  
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
 
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper 1 event interrupt 
+  * @retval The new state of RTC_IT (SET or RESET).
 
+  */
 
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint32_t tmpreg = 0, enablestatus = 0;
 
+ 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_GET_IT(RTC_IT));
 
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
 
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
 
+ 
+  /* Get the Interrupt enable Status */
 
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));
 
+  
+  /* Get the Interrupt pending bit */
 
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
 
+  
+  /* Get the status of the Interrupt */
 
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the RTC's interrupt pending bits.
 
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper 1 event interrupt 
+  * @retval None
 
+  */
 
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
 
+{
 
+  uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
 
+
 
+  /* Get the RTC_ISR Interrupt pending bits mask */
 
+  tmpreg = (uint32_t)(RTC_IT >> 4);
 
+
 
+  /* Clear the interrupt pending bits in the RTC_ISR register */
 
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @brief  Converts a 2 digit decimal to BCD format.
 
+  * @param  Value: Byte to be converted.
 
+  * @retval Converted byte
 
+  */
 
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
 
+{
 
+  uint8_t bcdhigh = 0;
 
+  
+  while (Value >= 10)
 
+  {
 
+    bcdhigh++;
 
+    Value -= 10;
 
+  }
 
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
 
+}
 
+
 
+/**
 
+  * @brief  Convert from 2 digit BCD to Binary.
 
+  * @param  Value: BCD value to be converted.
 
+  * @retval Converted word
 
+  */
 
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
 
+{
 
+  uint8_t tmp = 0;
 
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
 
+  return (tmp + (Value & (uint8_t)0x0F));
 
+}
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1010 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_sdio.c
Ver arquivo 

@@ -0,0 +1,1010 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_sdio.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Secure digital input/output interface (SDIO) 
+  *          peripheral:
 
+  *           - Initialization and Configuration
 
+  *           - Command path state machine (CPSM) management
 
+  *           - Data path state machine (DPSM) management
 
+  *           - SDIO IO Cards mode management
 
+  *           - CE-ATA mode management
 
+  *           - DMA transfers management
 
+  *           - Interrupts and flags management
 
+  *
 
+  *  @verbatim
 
+  *
 
+  *
 
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *          1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output
 
+  *             of PLL (PLL48CLK). Before to start working with SDIO peripheral
 
+  *             make sure that the PLL is well configured.
 
+  *          The SDIO peripheral uses two clock signals:
 
+  *              - SDIO adapter clock (SDIOCLK = 48 MHz)
 
+  *              - APB2 bus clock (PCLK2)
 
+  *          PCLK2 and SDIO_CK clock frequencies must respect the following condition:
 
+  *                   Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
 
+  *
 
+  *          2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
 
+  *
 
+  *          3.  According to the SDIO mode, enable the GPIO clocks using 
+  *              RCC_AHB1PeriphClockCmd() function. 
+  *              The I/O can be one of the following configurations:
 
+  *                 - 1-bit data length: SDIO_CMD, SDIO_CK and D0.
 
+  *                 - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
 
+  *                 - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].      
+  *
 
+  *          4. Peripheral's alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
 
+  *                 - Configure the desired pin in alternate function by:
 
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
 
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
 
+  *                 - Call GPIO_Init() function
 
+  *
 
+  *          5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, 
+  *             hardware, flow control and the Clock Divider using the SDIO_Init()
 
+  *             function.
 
+  *
 
+  *          6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) 
+  *             function.
 
+  *              
+  *          7. Enable the clock using the SDIO_ClockCmd() function.
 
+  *
 
+  *          8. Enable the NVIC and the corresponding interrupt using the function 
+  *             SDIO_ITConfig() if you need to use interrupt mode. 
+  *
 
+  *          9. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
 
+  *                   - Active the needed channel Request using SDIO_DMACmd() function
 
+  *
 
+  *          10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  *
 
+  *          11. To control the CPSM (Command Path State Machine) and send 
+  *              commands to the card use the SDIO_SendCommand(), 
+  *              SDIO_GetCommandResponse() and SDIO_GetResponse() functions.     
+  *              First, user has to fill the command structure (pointer to
 
+  *              SDIO_CmdInitTypeDef) according to the selected command to be sent.
 
+  *                 The parameters that should be filled are:
 
+  *                   - Command Argument
 
+  *                   - Command Index
 
+  *                   - Command Response type
 
+  *                   - Command Wait
 
+  *                   - CPSM Status (Enable or Disable)
 
+  *
 
+  *              To check if the command is well received, read the SDIO_CMDRESP
 
+  *              register using the SDIO_GetCommandResponse().
 
+  *              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
 
+  *              SDIO_GetResponse() function.
 
+  *
 
+  *          12. To control the DPSM (Data Path State Machine) and send/receive 
+  *              data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
+  *              SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
 
+  *
 
+  *              Read Operations
 
+  *              ---------------
 
+  *              a) First, user has to fill the data structure (pointer to
 
+  *                 SDIO_DataInitTypeDef) according to the selected data type to
 
+  *                 be received.
 
+  *                 The parameters that should be filled are:
 
+  *                   - Data TimeOut
 
+  *                   - Data Length
 
+  *                   - Data Block size
 
+  *                   - Data Transfer direction: should be from card (To SDIO)
 
+  *                   - Data Transfer mode
 
+  *                   - DPSM Status (Enable or Disable)
 
+  *                                   
+  *              b) Configure the SDIO resources to receive the data from the card
 
+  *                 according to selected transfer mode (Refer to Step 8, 9 and 10).
 
+  *
 
+  *              c) Send the selected Read command (refer to step 11).
 
+  *                  
+  *              d) Use the SDIO flags/interrupts to check the transfer status.
 
+  *
 
+  *              Write Operations
 
+  *              ---------------
 
+  *              a) First, user has to fill the data structure (pointer to
 
+  *                 SDIO_DataInitTypeDef) according to the selected data type to
 
+  *                 be received.
 
+  *                 The parameters that should be filled are:
 
+  *                   - Data TimeOut
 
+  *                   - Data Length
 
+  *                   - Data Block size
 
+  *                   - Data Transfer direction:  should be to card (To CARD)
 
+  *                   - Data Transfer mode
 
+  *                   - DPSM Status (Enable or Disable)
 
+  *
 
+  *              b) Configure the SDIO resources to send the data to the card
 
+  *                 according to selected transfer mode (Refer to Step 8, 9 and 10).
 
+  *                   
+  *              c) Send the selected Write command (refer to step 11).
 
+  *                  
+  *              d) Use the SDIO flags/interrupts to check the transfer status.
 
+  *
 
+  *
 
+  *  @endverbatim
 
+  *
 
+  *
 
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_sdio.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SDIO 
+  * @brief SDIO driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* ------------ SDIO registers bit address in the alias region ----------- */
 
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
 
+
 
+/* --- CLKCR Register ---*/
 
+/* Alias word address of CLKEN bit */
 
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
 
+#define CLKEN_BitNumber           0x08
 
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
 
+
 
+/* --- CMD Register ---*/
 
+/* Alias word address of SDIOSUSPEND bit */
 
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
 
+#define SDIOSUSPEND_BitNumber     0x0B
 
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
 
+
 
+/* Alias word address of ENCMDCOMPL bit */
 
+#define ENCMDCOMPL_BitNumber      0x0C
 
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
 
+
 
+/* Alias word address of NIEN bit */
 
+#define NIEN_BitNumber            0x0D
 
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
 
+
 
+/* Alias word address of ATACMD bit */
 
+#define ATACMD_BitNumber          0x0E
 
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 
+
 
+/* --- DCTRL Register ---*/
 
+/* Alias word address of DMAEN bit */
 
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
 
+#define DMAEN_BitNumber           0x03
 
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 
+
 
+/* Alias word address of RWSTART bit */
 
+#define RWSTART_BitNumber         0x08
 
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
 
+
 
+/* Alias word address of RWSTOP bit */
 
+#define RWSTOP_BitNumber          0x09
 
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 
+
 
+/* Alias word address of RWMOD bit */
 
+#define RWMOD_BitNumber           0x0A
 
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
 
+
 
+/* Alias word address of SDIOEN bit */
 
+#define SDIOEN_BitNumber          0x0B
 
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
 
+
 
+/* ---------------------- SDIO registers bit mask ------------------------ */
 
+/* --- CLKCR Register ---*/
 
+/* CLKCR register clear mask */
 
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
 
+/* --- PWRCTRL Register ---*/
 
+/* SDIO PWRCTRL Mask */
 
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
 
+
 
+/* --- DCTRL Register ---*/
 
+/* SDIO DCTRL Clear Mask */
 
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
 
+
 
+/* --- CMD Register ---*/
 
+/* CMD Register clear mask */
 
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
 
+
 
+/* SDIO RESP Registers Address */
 
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup SDIO_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SDIO_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                 Initialization and Configuration functions
 
+ ===============================================================================
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void SDIO_DeInit(void)
 
+{
 
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
 
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the SDIO peripheral according to the specified 
+  *         parameters in the SDIO_InitStruct.
 
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
+  *         that contains the configuration information for the SDIO peripheral.
 
+  * @retval None
 
+  */
 
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+    
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
 
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
 
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
 
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
 
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
+   
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
+  /* Get the SDIO CLKCR value */
 
+  tmpreg = SDIO->CLKCR;
 
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
 
+  tmpreg &= CLKCR_CLEAR_MASK;
 
+  
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
 
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
 
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
 
+  /* Set WIDBUS bits according to SDIO_BusWide value */
 
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
 
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
 
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
 
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
 
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
+  
+  /* Write to SDIO CLKCR */
 
+  SDIO->CLKCR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each SDIO_InitStruct member with its default value.
 
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
+  *         will be initialized.
 
+  * @retval None
 
+  */
 
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
 
+{
 
+  /* SDIO_InitStruct members default value */
 
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
 
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
 
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
 
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
 
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
 
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the SDIO Clock.
 
+  * @param  NewState: new state of the SDIO Clock. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_ClockCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the power status of the controller.
 
+  * @param  SDIO_PowerState: new state of the Power state. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SDIO_PowerState_OFF: SDIO Power OFF
 
+  *            @arg SDIO_PowerState_ON: SDIO Power ON
 
+  * @retval None
 
+  */
 
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
 
+  
+  SDIO->POWER = SDIO_PowerState;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the power status of the controller.
 
+  * @param  None
 
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
 
+  *            - 0x00: Power OFF
 
+  *            - 0x02: Power UP
 
+  *            - 0x03: Power ON 
+  */
 
+uint32_t SDIO_GetPowerState(void)
 
+{
 
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
 
+ *  @brief   Command path state machine (CPSM) management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              Command path state machine (CPSM) management functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the Command path 
+  state machine (CPSM).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Initializes the SDIO Command according to the specified 
+  *         parameters in the SDIO_CmdInitStruct and send the command.
 
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
+  *         structure that contains the configuration information for the SDIO 
+  *         command.
 
+  * @retval None
 
+  */
 
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
 
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
 
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
 
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
 
+  
+/*---------------------------- SDIO ARG Configuration ------------------------*/
 
+  /* Set the SDIO Argument value */
 
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
 
+  
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
+  /* Get the SDIO CMD value */
 
+  tmpreg = SDIO->CMD;
 
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
 
+  tmpreg &= CMD_CLEAR_MASK;
 
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
 
+  /* Set WAITRESP bits according to SDIO_Response value */
 
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
 
+  /* Set CPSMEN bits according to SDIO_CPSM value */
 
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
 
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
 
+  
+  /* Write to SDIO CMD */
 
+  SDIO->CMD = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
 
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
+  *         structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
 
+{
 
+  /* SDIO_CmdInitStruct members default value */
 
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
 
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
 
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
 
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
 
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
 
+}
 
+
 
+/**
 
+  * @brief  Returns command index of last command for which response received.
 
+  * @param  None
 
+  * @retval Returns the command index of the last command response received.
 
+  */
 
+uint8_t SDIO_GetCommandResponse(void)
 
+{
 
+  return (uint8_t)(SDIO->RESPCMD);
 
+}
 
+
 
+/**
 
+  * @brief  Returns response received from the card for the last command.
 
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SDIO_RESP1: Response Register 1
 
+  *            @arg SDIO_RESP2: Response Register 2
 
+  *            @arg SDIO_RESP3: Response Register 3
 
+  *            @arg SDIO_RESP4: Response Register 4
 
+  * @retval The Corresponding response register value.
 
+  */
 
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
 
+{
 
+  __IO uint32_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
 
+
 
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
 
+  
+  return (*(__IO uint32_t *) tmp); 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
 
+ *  @brief   Data path state machine (DPSM) management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              Data path state machine (DPSM) management functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the Data path 
+  state machine (DPSM).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Initializes the SDIO data path according to the specified 
+  *         parameters in the SDIO_DataInitStruct.
 
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDIO command.
 
+  * @retval None
 
+  */
 
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
 
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
 
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
 
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
 
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
 
+
 
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
 
+  /* Set the SDIO Data TimeOut value */
 
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
 
+
 
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
 
+  /* Set the SDIO DataLength value */
 
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
 
+
 
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
+  /* Get the SDIO DCTRL value */
 
+  tmpreg = SDIO->DCTRL;
 
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
 
+  tmpreg &= DCTRL_CLEAR_MASK;
 
+  /* Set DEN bit according to SDIO_DPSM value */
 
+  /* Set DTMODE bit according to SDIO_TransferMode value */
 
+  /* Set DTDIR bit according to SDIO_TransferDir value */
 
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
 
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
 
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
 
+
 
+  /* Write to SDIO DCTRL */
 
+  SDIO->DCTRL = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
 
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
 
+{
 
+  /* SDIO_DataInitStruct members default value */
 
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
 
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
 
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
 
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
 
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
 
+}
 
+
 
+/**
 
+  * @brief  Returns number of remaining data bytes to be transferred.
 
+  * @param  None
 
+  * @retval Number of remaining data bytes to be transferred
 
+  */
 
+uint32_t SDIO_GetDataCounter(void)
 
+{ 
+  return SDIO->DCOUNT;
 
+}
 
+
 
+/**
 
+  * @brief  Read one data word from Rx FIFO.
 
+  * @param  None
 
+  * @retval Data received
 
+  */
 
+uint32_t SDIO_ReadData(void)
 
+{ 
+  return SDIO->FIFO;
 
+}
 
+
 
+/**
 
+  * @brief  Write one data word to Tx FIFO.
 
+  * @param  Data: 32-bit data word to write.
 
+  * @retval None
 
+  */
 
+void SDIO_WriteData(uint32_t Data)
 
+{ 
+  SDIO->FIFO = Data;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the number of words left to be written to or read from FIFO.	
+  * @param  None
 
+  * @retval Remaining number of words.
 
+  */
 
+uint32_t SDIO_GetFIFOCount(void)
 
+{ 
+  return SDIO->FIFOCNT;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
 
+ *  @brief   SDIO IO Cards mode management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              SDIO IO Cards mode management functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the SDIO IO Cards.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Starts the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Start SDIO Read Wait operation. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Stops the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Sets one of the two options of inserting read wait interval.
 
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
 
+  *          This parameter can be:
 
+  *            @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
 
+  *            @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
 
+  * @retval None
 
+  */
 
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
 
+  
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the SD I/O Mode Operation.
 
+  * @param  NewState: new state of SDIO specific operation. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_SetSDIOOperation(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
 
+  * @param  NewState: new state of the SD I/O Mode suspend command.
 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group5 CE-ATA mode management functions
 
+ *  @brief   CE-ATA mode management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              CE-ATA mode management functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program and read the CE-ATA card.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the command completion signal.
 
+  * @param  NewState: new state of command completion signal. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the CE-ATA interrupt.
 
+  * @param  NewState: new state of CE-ATA interrupt. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_CEATAITCmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
 
+}
 
+
 
+/**
 
+  * @brief  Sends CE-ATA command (CMD61).
 
+  * @param  NewState: new state of CE-ATA command. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_SendCEATACmd(FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group6 DMA transfers management functions
 
+ *  @brief   DMA transfers management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+              DMA transfers management functions
 
+ ===============================================================================  
+
 
+  This section provide functions allowing to program SDIO DMA transfer.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the SDIO DMA request.
 
+  * @param  NewState: new state of the selected SDIO DMA request.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SDIO_DMACmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SDIO_Group7 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions  
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the SDIO interrupts.
 
+  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
 
+  *          This parameter can be one or a combination of the following values:
 
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
 
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 
+  * @param  NewState: new state of the specified SDIO interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None 
+  */
 
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_IT(SDIO_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the SDIO interrupts */
 
+    SDIO->MASK |= SDIO_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the SDIO interrupts */
 
+    SDIO->MASK &= ~SDIO_IT;
 
+  } 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified SDIO flag is set or not.
 
+  * @param  SDIO_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
 
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
 
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
 
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
 
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
 
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
 
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
 
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
 
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
 
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
 
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
 
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
 
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 
+  * @retval The new state of SDIO_FLAG (SET or RESET).
 
+  */
 
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
 
+{ 
+  FlagStatus bitstatus = RESET;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
 
+  
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the SDIO's pending flags.
 
+  * @param  SDIO_FLAG: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
 
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
 
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
 
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
 
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
 
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
 
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
 
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
 
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
 
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
 
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
 
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
 
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
 
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
 
+  * @retval None
 
+  */
 
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
 
+   
+  SDIO->ICR = SDIO_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
 
+  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
 
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
 
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
 
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
 
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
 
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
 
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
 
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
 
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
 
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
 
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
 
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
 
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
 
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
 
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
 
+  * @retval The new state of SDIO_IT (SET or RESET).
 
+  */
 
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
 
+{ 
+  ITStatus bitstatus = RESET;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
 
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the SDIO's interrupt pending bits.
 
+  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
 
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
 
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
 
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
 
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
 
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
 
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
 
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
 
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
 
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
 
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
 
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
 
+  * @retval None
 
+  */
 
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
 
+   
+  SDIO->ICR = SDIO_IT;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1292 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_spi.c
Ver arquivo 

@@ -0,0 +1,1292 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_spi.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):
 
+  *           - Initialization and Configuration
 
+  *           - Data transfers functions
 
+  *           - Hardware CRC Calculation
 
+  *           - DMA transfers management
 
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
 
+  *          
+  *                    
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *    
+  *          1. Enable peripheral clock using the following functions 
+  *             RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
 
+  *             RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
 
+  *             RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.
 
+  *
 
+  *          2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
 
+  *             function.
 
+  *             In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO
 
+  *             clock should also be enabled.
 
+  *
 
+  *          3. Peripherals alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
 
+  *                 - Configure the desired pin in alternate function by:
 
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
 
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
 
+  *                 - Call GPIO_Init() function
 
+  *              In I2S mode, if an external clock source is used then the I2S CKIN pin
 
+  *              should be also configured in Alternate function Push-pull pull-up mode. 
+  *        
+  *          4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+  *             Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
 
+  *             function.
 
+  *             In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio 
+  *             frequency and Polarity using I2S_Init() function.
 
+  *             For I2S mode, make sure that either:
 
+  *              - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), 
+  *                RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).
 
+  *              or 
+  *              - External clock source is configured using the function 
+  *                RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant
 
+  *                I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. 
+  *
 
+  *          5. Enable the NVIC and the corresponding interrupt using the function 
+  *             SPI_ITConfig() if you need to use interrupt mode. 
+  *
 
+  *          6. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
 
+  *                   - Active the needed channel Request using SPI_I2S_DMACmd() function
 
+  * 
+  *          7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
 
+  *             I2S_Cmd().
 
+  * 
+  *          8. Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  *
 
+  *          9. Optionally, you can enable/configure the following parameters without
 
+  *             re-initialization (i.e there is no need to call again SPI_Init() function):
 
+  *              - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
 
+  *                is programmed as Data direction parameter using the SPI_Init() function
 
+  *                it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
 
+  *                using the SPI_BiDirectionalLineConfig() function.
 
+  *              - When SPI_NSS_Soft is selected as Slave Select Management parameter 
+  *                using the SPI_Init() function it can be possible to manage the 
+  *                NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
 
+  *              - Reconfigure the data size using the SPI_DataSizeConfig() function  
+  *              - Enable or disable the SS output using the SPI_SSOutputCmd() function  
+  *          
+  *          10. To use the CRC Hardware calculation feature refer to the Peripheral 
+  *              CRC hardware Calculation subsection.
 
+  *   
+  *
 
+  *          It is possible to use SPI in I2S full duplex mode, in this case, each SPI 
+  *          peripheral is able to manage sending and receiving data simultaneously
 
+  *          using two data lines. Each SPI peripheral has an extended block called I2Sxext
 
+  *          (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
 
+  *          The extension block is not a full SPI IP, it is used only as I2S slave to
 
+  *          implement full duplex mode. The extension block uses the same clock sources
 
+  *          as its master.          
+  *          To configure I2S full duplex you have to:
 
+  *            
+  *          1. Configure SPIx in I2S mode (I2S_Init() function) as described above. 
+  *           
+  *          2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to  
+  *             I2S_Init() function.
 
+  *            
+  *          3. Call I2S_Cmd() for SPIx then for its extended block.
 
+  *          
+  *          4. To configure interrupts or DMA requests and to get/clear flag status, 
+  *             use I2Sxext instance for the extension block.
 
+  *             
+  *          Functions that can be called with I2Sxext instances are:
 
+  *          I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), 
+  *          SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
 
+  *          SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
 
+  *                 
+  *          Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
 
+  *            
+  *          RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);   
+  *          I2S_StructInit(&I2SInitStruct);
 
+  *          I2SInitStruct.Mode = I2S_Mode_MasterTx;     
+  *          I2S_Init(SPI3, &I2SInitStruct);
 
+  *          I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
 
+  *          I2S_Cmd(SPI3, ENABLE);
 
+  *          I2S_Cmd(SPI3ext, ENABLE);
 
+  *          ...
 
+  *          while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
 
+  *          {}
 
+  *          SPI_I2S_SendData(SPI3, txdata[i]);
 
+  *          ...  
+  *          while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
 
+  *          {}
 
+  *          rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
 
+  *          ...          
+  *              
+  *     
+  * @note    In I2S mode: if an external clock is used as source clock for the I2S,  
+  *          then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should 
+  *          be enabled and set to the value of the source clock frequency (in Hz).
 
+  * 
+  * @note    In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() 
+  *          just after calling the function SPI_Init().
 
+  *
 
+  *  @endverbatim  
+  *                                  
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_spi.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SPI 
+  * @brief SPI driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* SPI registers Masks */
 
+#define CR1_CLEAR_MASK            ((uint16_t)0x3040)
 
+#define I2SCFGR_CLEAR_MASK        ((uint16_t)0xF040)
 
+
 
+/* RCC PLLs masks */
 
+#define PLLCFGR_PPLR_MASK         ((uint32_t)0x70000000)
 
+#define PLLCFGR_PPLN_MASK         ((uint32_t)0x00007FC0)
 
+
 
+#define SPI_CR2_FRF               ((uint16_t)0x0010)
 
+#define SPI_SR_TIFRFE             ((uint16_t)0x0100)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup SPI_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SPI_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+  This section provides a set of functions allowing to initialize the SPI Direction,
 
+  SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
 
+  Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
 
+  
+  The SPI_Init() function follows the SPI configuration procedures for Master mode
 
+  and Slave mode (details for these procedures are available in reference manual
 
+  (RM0090)).
 
+  
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitialize the SPIx peripheral registers to their default reset values.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.   
+  *         
+  * @note   The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized
 
+  *         when the relative I2S peripheral is deinitialized (the extended block's clock
 
+  *         is managed by the I2S peripheral clock).
 
+  *             
+  * @retval None
 
+  */
 
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+
 
+  if (SPIx == SPI1)
 
+  {
 
+    /* Enable SPI1 reset state */
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
 
+    /* Release SPI1 from reset state */
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
 
+  }
 
+  else if (SPIx == SPI2)
 
+  {
 
+    /* Enable SPI2 reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
 
+    /* Release SPI2 from reset state */
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
 
+    }
 
+  else
 
+  {
 
+    if (SPIx == SPI3)
 
+    {
 
+      /* Enable SPI3 reset state */
 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
 
+      /* Release SPI3 from reset state */
 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
 
+  *         contains the configuration information for the specified SPI peripheral.
 
+  * @retval None
 
+  */
 
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
 
+{
 
+  uint16_t tmpreg = 0;
 
+  
+  /* check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  
+  /* Check the SPI parameters */
 
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
 
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
 
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
 
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
 
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
 
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
 
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
 
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
 
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
 
+
 
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
 
+  /* Get the SPIx CR1 value */
 
+  tmpreg = SPIx->CR1;
 
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
 
+  tmpreg &= CR1_CLEAR_MASK;
 
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
 
+     master/salve mode, CPOL and CPHA */
 
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
 
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
 
+  /* Set LSBFirst bit according to SPI_FirstBit value */
 
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
 
+  /* Set CPOL bit according to SPI_CPOL value */
 
+  /* Set CPHA bit according to SPI_CPHA value */
 
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
 
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
 
+  /* Write to SPIx CR1 */
 
+  SPIx->CR1 = tmpreg;
 
+
 
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
 
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
 
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
 
+  /* Write to SPIx CRCPOLY */
 
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
 
+  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral (configured in I2S mode).
 
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
 
+  *         contains the configuration information for the specified SPI peripheral
 
+  *         configured in I2S mode.
 
+  *           
+  * @note   The function calculates the optimal prescaler needed to obtain the most 
+  *         accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *         and the product configuration). But in case the prescaler value is greater 
+  *         than 511, the default value (0x02) will be configured instead.    
+  * 
+  * @note   if an external clock is used as source clock for the I2S, then the define
 
+  *         I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
 
+  *         to the value of the the source clock frequency (in Hz).
 
+  *  
+  * @retval None
 
+  */
 
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
 
+{
 
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
 
+  uint32_t tmp = 0, i2sclk = 0;
 
+#ifndef I2S_EXTERNAL_CLOCK_VAL
 
+  uint32_t pllm = 0, plln = 0, pllr = 0;
 
+#endif /* I2S_EXTERNAL_CLOCK_VAL */
 
+  
+  /* Check the I2S parameters */
 
+  assert_param(IS_SPI_23_PERIPH(SPIx));
 
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
 
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
 
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
 
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
 
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
 
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
 
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
 
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  SPIx->I2SPR = 0x0002;
 
+  
+  /* Get the I2SCFGR register value */
 
+  tmpreg = SPIx->I2SCFGR;
 
+  
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
 
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
 
+  {
 
+    i2sodd = (uint16_t)0;
 
+    i2sdiv = (uint16_t)2;   
+  }
 
+  /* If the requested audio frequency is not the default, compute the prescaler */
 
+  else
 
+  {
 
+    /* Check the frame length (For the Prescaler computing) *******************/
 
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
 
+    {
 
+      /* Packet length is 16 bits */
 
+      packetlength = 1;
 
+    }
 
+    else
 
+    {
 
+      /* Packet length is 32 bits */
 
+      packetlength = 2;
 
+    }
 
+
 
+    /* Get I2S source Clock frequency  ****************************************/
 
+      
+    /* If an external I2S clock has to be used, this define should be set  
+       in the project configuration or in the stm32f4xx_conf.h file */
 
+  #ifdef I2S_EXTERNAL_CLOCK_VAL     
+    /* Set external clock as I2S clock source */
 
+    if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
 
+    {
 
+      RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
 
+    }
 
+    
+    /* Set the I2S clock to the external clock  value */
 
+    i2sclk = I2S_EXTERNAL_CLOCK_VAL;
 
+
 
+  #else /* There is no define for External I2S clock source */
 
+    /* Set PLLI2S as I2S clock source */
 
+    if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
 
+    {
 
+      RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
 
+    }    
+    
+    /* Get the PLLI2SN value */
 
+    plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
 
+                      (RCC_PLLI2SCFGR_PLLI2SN >> 6));
 
+    
+    /* Get the PLLI2SR value */
 
+    pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
 
+                      (RCC_PLLI2SCFGR_PLLI2SR >> 28));
 
+    
+    /* Get the PLLM value */
 
+    pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);      
+    
+    /* Get the I2S source clock value */
 
+    i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
 
+  #endif /* I2S_EXTERNAL_CLOCK_VAL */
 
+    
+    /* Compute the Real divider depending on the MCLK output state, with a floating point */
 
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
 
+    {
 
+      /* MCLK output is enabled */
 
+      tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
 
+    }
 
+    else
 
+    {
 
+      /* MCLK output is disabled */
 
+      tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
 
+    }
 
+    
+    /* Remove the flatting point */
 
+    tmp = tmp / 10;  
+      
+    /* Check the parity of the divider */
 
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
 
+   
+    /* Compute the i2sdiv prescaler */
 
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
 
+   
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 
+    i2sodd = (uint16_t) (i2sodd << 8);
 
+  }
 
+
 
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
 
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
 
+  {
 
+    /* Set the default values */
 
+    i2sdiv = 2;
 
+    i2sodd = 0;
 
+  }
 
+
 
+  /* Write to SPIx I2SPR register the computed value */
 
+  SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
 
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
 
+  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
 
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
 
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
 
+ 
+  /* Write to SPIx I2SCFGR */  
+  SPIx->I2SCFGR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each SPI_InitStruct member with its default value.
 
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
 
+{
 
+/*--------------- Reset SPI init structure parameters values -----------------*/
 
+  /* Initialize the SPI_Direction member */
 
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
 
+  /* initialize the SPI_Mode member */
 
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
 
+  /* initialize the SPI_DataSize member */
 
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
 
+  /* Initialize the SPI_CPOL member */
 
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
 
+  /* Initialize the SPI_CPHA member */
 
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
 
+  /* Initialize the SPI_NSS member */
 
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
 
+  /* Initialize the SPI_BaudRatePrescaler member */
 
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
 
+  /* Initialize the SPI_FirstBit member */
 
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
 
+  /* Initialize the SPI_CRCPolynomial member */
 
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each I2S_InitStruct member with its default value.
 
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
 
+{
 
+/*--------------- Reset I2S init structure parameters values -----------------*/
 
+  /* Initialize the I2S_Mode member */
 
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
 
+  
+  /* Initialize the I2S_Standard member */
 
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
 
+  
+  /* Initialize the I2S_DataFormat member */
 
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
 
+  
+  /* Initialize the I2S_MCLKOutput member */
 
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
 
+  
+  /* Initialize the I2S_AudioFreq member */
 
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
 
+  
+  /* Initialize the I2S_CPOL member */
 
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified SPI peripheral.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI peripheral */
 
+    SPIx->CR1 |= SPI_CR1_SPE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI peripheral */
 
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
 
+  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext 
+  *         for full duplex mode).
 
+  * @param  NewState: new state of the SPIx peripheral. 
+  *         This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI peripheral (in I2S mode) */
 
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI peripheral in I2S mode */
 
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the data size for the selected SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  SPI_DataSize: specifies the SPI data size.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_DataSize_16b: Set data frame format to 16bit
 
+  *            @arg SPI_DataSize_8b: Set data frame format to 8bit
 
+  * @retval None
 
+  */
 
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
 
+  /* Clear DFF bit */
 
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
 
+  /* Set new DFF bit value */
 
+  SPIx->CR1 |= SPI_DataSize;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_Direction_Tx: Selects Tx transmission direction
 
+  *            @arg SPI_Direction_Rx: Selects Rx receive direction
 
+  * @retval None
 
+  */
 
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
 
+  if (SPI_Direction == SPI_Direction_Tx)
 
+  {
 
+    /* Set the Tx only mode */
 
+    SPIx->CR1 |= SPI_Direction_Tx;
 
+  }
 
+  else
 
+  {
 
+    /* Set the Rx only mode */
 
+    SPIx->CR1 &= SPI_Direction_Rx;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
 
+  *            @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
 
+  * @retval None
 
+  */
 
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
 
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
 
+  {
 
+    /* Set NSS pin internally by software */
 
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
 
+  }
 
+  else
 
+  {
 
+    /* Reset NSS pin internally by software */
 
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the SS output for the selected SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  NewState: new state of the SPIx SS output. 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI SS output */
 
+    SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI SS output */
 
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
 
+  *   
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
+  *         are not taken into consideration and are configured by hardware
 
+  *         respectively to the TI mode requirements.  
+  * 
+  * @param  SPIx: where x can be 1, 2 or 3 
+  * @param  NewState: new state of the selected SPI TI communication mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the TI mode for the selected SPI peripheral */
 
+    SPIx->CR2 |= SPI_CR2_FRF;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the TI mode for the selected SPI peripheral */
 
+    SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the full duplex mode for the I2Sx peripheral using its
 
+  *         extension I2Sxext according to the specified parameters in the 
+  *         I2S_InitStruct.
 
+  * @param  I2Sxext: where x can be  2 or 3 to select the I2S peripheral extension block.
 
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
 
+  *         contains the configuration information for the specified I2S peripheral
 
+  *         extension.
 
+  * 
+  * @note   The structure pointed by I2S_InitStruct parameter should be the same
 
+  *         used for the master I2S peripheral. In this case, if the master is 
+  *         configured as transmitter, the slave will be receiver and vice versa.
 
+  *         Or you can force a different mode by modifying the field I2S_Mode to the
 
+  *         value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.    
+  *         
+  * @note   The I2S full duplex extension can be configured in slave mode only.    
+  *  
+  * @retval None
 
+  */
 
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
 
+{
 
+  uint16_t tmpreg = 0, tmp = 0;
 
+  
+  /* Check the I2S parameters */
 
+  assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
 
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
 
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
 
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
 
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
 
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
 
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 
+  I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  I2Sxext->I2SPR = 0x0002;
 
+  
+  /* Get the I2SCFGR register value */
 
+  tmpreg = I2Sxext->I2SCFGR;
 
+  
+  /* Get the mode to be configured for the extended I2S */
 
+  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
 
+  {
 
+    tmp = I2S_Mode_SlaveRx;
 
+  }
 
+  else
 
+  {
 
+    if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
 
+    {
 
+      tmp = I2S_Mode_SlaveTx;
 
+    }
 
+  }
 
+
 
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
 
+  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
 
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
 
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
 
+ 
+  /* Write to SPIx I2SCFGR */  
+  I2Sxext->I2SCFGR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Group2 Data transfers functions
 
+ *  @brief   Data transfers functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Data transfers functions
 
+ ===============================================================================  
+
 
+  This section provides a set of functions allowing to manage the SPI data transfers
 
+  
+  In reception, data are received and then stored into an internal Rx buffer while 
+  In transmission, data are first stored into an internal Tx buffer before being 
+  transmitted.
 
+
 
+  The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
 
+  function and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+  can be done using SPI_I2S_SendData() function and stores the written data into 
+  Tx buffer.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @retval The value of the received data.
 
+  */
 
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  
+  /* Return the data in the DR register */
 
+  return SPIx->DR;
 
+}
 
+
 
+/**
 
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.     
+  * @param  Data: Data to be transmitted.
 
+  * @retval None
 
+  */
 
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  
+  /* Write in the DR register the data to be sent */
 
+  SPIx->DR = Data;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
 
+ *  @brief   Hardware CRC Calculation functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Hardware CRC Calculation functions
 
+ ===============================================================================  
+
 
+  This section provides a set of functions allowing to manage the SPI CRC hardware 
+  calculation
 
+
 
+  SPI communication using CRC is possible through the following procedure:
 
+     1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+        Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
 
+        function.
 
+     2. Enable the CRC calculation using the SPI_CalculateCRC() function.
 
+     3. Enable the SPI using the SPI_Cmd() function
 
+     4. Before writing the last data to the TX buffer, set the CRCNext bit using the 
+      SPI_TransmitCRC() function to indicate that after transmission of the last 
+      data, the CRC should be transmitted.
 
+     5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
 
+        bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+        value. 
+        If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
 
+        can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
 
+
 
+@note It is advised not to read the calculated CRC values during the communication.
 
+
 
+@note When the SPI is in slave mode, be careful to enable CRC calculation only 
+      when the clock is stable, that is, when the clock is in the steady state. 
+      If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+      to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+      the value of the SPE bit.
 
+
 
+@note With high bitrate frequencies, be careful when transmitting the CRC.
 
+      As the number of used CPU cycles has to be as low as possible in the CRC 
+      transfer phase, it is forbidden to call software functions in the CRC 
+      transmission sequence to avoid errors in the last data and CRC reception. 
+      In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+      of the last data.
 
+
 
+@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the
 
+      degradation of the SPI speed performance due to CPU accesses impacting the 
+      SPI bandwidth.
 
+
 
+@note When the STM32F4xx is configured as slave and the NSS hardware mode is 
+      used, the NSS pin needs to be kept low between the data phase and the CRC 
+      phase.
 
+
 
+@note When the SPI is configured in slave mode with the CRC feature enabled, CRC
 
+      calculation takes place even if a high level is applied on the NSS pin. 
+      This may happen for example in case of a multi-slave environment where the 
+      communication master addresses slaves alternately.
 
+
 
+@note Between a slave de-selection (high level on NSS) and a new slave selection 
+      (low level on NSS), the CRC value should be cleared on both master and slave
 
+      sides in order to resynchronize the master and slave for their respective 
+      CRC calculation.
 
+
 
+@note To clear the CRC, follow the procedure below:
 
+        1. Disable SPI using the SPI_Cmd() function
 
+        2. Disable the CRC calculation using the SPI_CalculateCRC() function.
 
+        3. Enable the CRC calculation using the SPI_CalculateCRC() function.
 
+        4. Enable SPI using the SPI_Cmd() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  NewState: new state of the SPIx CRC value calculation.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI CRC calculation */
 
+    SPIx->CR1 |= SPI_CR1_CRCEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI CRC calculation */
 
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Transmit the SPIx CRC value.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @retval None
 
+  */
 
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  
+  /* Enable the selected SPI CRC transmission */
 
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @param  SPI_CRC: specifies the CRC register to be read.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_CRC_Tx: Selects Tx CRC register
 
+  *            @arg SPI_CRC_Rx: Selects Rx CRC register
 
+  * @retval The selected CRC register value..
 
+  */
 
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
 
+{
 
+  uint16_t crcreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  assert_param(IS_SPI_CRC(SPI_CRC));
 
+  if (SPI_CRC != SPI_CRC_Rx)
 
+  {
 
+    /* Get the Tx CRC register */
 
+    crcreg = SPIx->TXCRCR;
 
+  }
 
+  else
 
+  {
 
+    /* Get the Rx CRC register */
 
+    crcreg = SPIx->RXCRCR;
 
+  }
 
+  /* Return the selected CRC register */
 
+  return crcreg;
 
+}
 
+
 
+/**
 
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
 
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
 
+  * @retval The CRC Polynomial register value.
 
+  */
 
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
 
+  
+  /* Return the CRC polynomial register */
 
+  return SPIx->CRCPR;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Group4 DMA transfers management functions
 
+ *  @brief   DMA transfers management functions
 
+  *
 
+@verbatim   
+ ===============================================================================
 
+                         DMA transfers management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
 
+  *            @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
 
+  * @param  NewState: new state of the selected SPI DMA transfer request.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI DMA requests */
 
+    SPIx->CR2 |= SPI_I2S_DMAReq;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI DMA requests */
 
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup SPI_Group5 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions
 
+  *
 
+@verbatim   
+ ===============================================================================
 
+                         Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This section provides a set of functions allowing to configure the SPI Interrupts 
+  sources and check or clear the flags or pending bits status.
 
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
 
+  =============
 
+  In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
 
+     1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
 
+     2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
 
+     3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
 
+     4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
+     5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur
 
+     6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
 
+     7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
 
+     8. I2S_FLAG_UDR: to indicate an Underrun error occurs.
 
+     9. I2S_FLAG_CHSIDE: to indicate Channel Side.
 
+
 
+@note Do not use the BSY flag to handle each data transmission or reception.  It is
 
+      better to use the TXE and RXNE flags instead.
 
+
 
+  In this Mode it is advised to use the following functions:
 
+     - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
 
+     - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
 
+
 
+  Interrupt Mode
 
+  ===============
 
+  In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
 
+  and 7 pending bits: 
+  Pending Bits:
 
+  ------------- 
+     1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
 
+     2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
 
+     3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)            
+     4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
 
+     5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur
 
+     6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
 
+     7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
 
+
 
+  Interrupt Source:
 
+  -----------------
 
+     1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+                        interrupt.  
+     2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+                          empty interrupt.
 
+     3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
 
+
 
+  In this Mode it is advised to use the following functions:
 
+     - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
 
+     - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
 
+     - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
 
+
 
+  DMA Mode
 
+  ========
 
+  In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
 
+     1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
 
+     2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
 
+
 
+  In this Mode it is advised to use the following function:
 
+    - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
 
+  *            @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
 
+  *            @arg SPI_I2S_IT_ERR: Error interrupt mask
 
+  * @param  NewState: new state of the specified SPI interrupt.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
 
+{
 
+  uint16_t itpos = 0, itmask = 0 ;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
 
+
 
+  /* Get the SPI IT index */
 
+  itpos = SPI_I2S_IT >> 4;
 
+
 
+  /* Set the IT mask */
 
+  itmask = (uint16_t)1 << (uint16_t)itpos;
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected SPI interrupt */
 
+    SPIx->CR2 |= itmask;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected SPI interrupt */
 
+    SPIx->CR2 &= (uint16_t)~itmask;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified SPIx/I2Sx flag is set or not.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
 
+  *            @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
 
+  *            @arg SPI_I2S_FLAG_BSY: Busy flag.
 
+  *            @arg SPI_I2S_FLAG_OVR: Overrun flag.
 
+  *            @arg SPI_FLAG_MODF: Mode Fault flag.
 
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.
 
+  *            @arg SPI_I2S_FLAG_TIFRFE: Format Error.
 
+  *            @arg I2S_FLAG_UDR: Underrun Error flag.
 
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag.  
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
 
+  */
 
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
 
+  
+  /* Check the status of the specified SPI flag */
 
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
 
+  {
 
+    /* SPI_I2S_FLAG is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* SPI_I2S_FLAG is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the SPI_I2S_FLAG status */
 
+  return  bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *          This function clears only CRCERR flag.
 
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.  
+  *  
+  * @note   OVR (OverRun error) flag is cleared by software sequence: a read 
+  *          operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *          operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
 
+  * @note   UDR (UnderRun error) flag is cleared by a read operation to 
+  *          SPI_SR register (SPI_I2S_GetFlagStatus()).   
+  * @note   MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *          operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *          write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
 
+  *  
+  * @retval None
 
+  */
 
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
 
+    
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
 
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *          This parameter can be one of the following values:
 
+  *            @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
 
+  *            @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
 
+  *            @arg SPI_I2S_IT_OVR: Overrun interrupt.
 
+  *            @arg SPI_IT_MODF: Mode Fault interrupt.
 
+  *            @arg SPI_IT_CRCERR: CRC Error interrupt.
 
+  *            @arg I2S_IT_UDR: Underrun interrupt.  
+  *            @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
 
+  */
 
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
 
+{
 
+  ITStatus bitstatus = RESET;
 
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
 
+
 
+  /* Get the SPI_I2S_IT index */
 
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
 
+
 
+  /* Get the SPI_I2S_IT IT mask */
 
+  itmask = SPI_I2S_IT >> 4;
 
+
 
+  /* Set the IT mask */
 
+  itmask = 0x01 << itmask;
 
+
 
+  /* Get the SPI_I2S_IT enable bit status */
 
+  enablestatus = (SPIx->CR2 & itmask) ;
 
+
 
+  /* Check the status of the specified SPI interrupt */
 
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
 
+  {
 
+    /* SPI_I2S_IT is set */
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    /* SPI_I2S_IT is reset */
 
+    bitstatus = RESET;
 
+  }
 
+  /* Return the SPI_I2S_IT status */
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
 
+  *         This function clears only CRCERR interrupt pending bit.   
+  *            @arg SPI_IT_CRCERR: CRC Error interrupt.
 
+  *   
+  * @note   OVR (OverRun Error) interrupt pending bit is cleared by software 
+  *          sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
+  *          followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
 
+  * @note   UDR (UnderRun Error) interrupt pending bit is cleared by a read 
+  *          operation to SPI_SR register (SPI_I2S_GetITStatus()).   
+  * @note   MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
 
+  *          a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
+  *          followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
+  *          the SPI).
 
+  * @retval None
 
+  */
 
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
 
+{
 
+  uint16_t itpos = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
 
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
 
+
 
+  /* Get the SPI_I2S IT index */
 
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
 
+
 
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
 
+  SPIx->SR = (uint16_t)~itpos;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/**
 
+  * @}
 
+  */ 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 203 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_syscfg.c
Ver arquivo 

@@ -0,0 +1,203 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_syscfg.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the SYSCFG peripheral.
 
+  *
 
+  *  @verbatim
 
+  *  
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *                  
+  *          This driver provides functions for:
 
+  *          
+  *          1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
 
+  *              
+  *          2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
 
+  *            
+  *          3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
 
+  *
 
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
 
+  *         using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
 
+  *                 
+  *  @endverbatim
 
+  *      
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_syscfg.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
 
+  * @{
 
+  */ 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+/* ------------ RCC registers bit address in the alias region ----------- */
 
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
 
+/* ---  PMC Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define PMC_OFFSET                (SYSCFG_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber    ((uint8_t)0x17) 
+#define PMC_MII_RMII_SEL_BB       (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 
+
 
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMP_PD_BitNumber          ((uint8_t)0x00) 
+#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup SYSCFG_Private_Functions
 
+  * @{
 
+  */ 
+
 
+/**
 
+  * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
 
+  *   registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void SYSCFG_DeInit(void)
 
+{
 
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
 
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Changes the mapping of the specified pin.
 
+  * @param  SYSCFG_Memory: selects the memory remapping.
 
+  *         This parameter can be one of the following values:
 
+  *            @arg SYSCFG_MemoryRemap_Flash:       Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
 
+  *            @arg SYSCFG_MemoryRemap_FSMC:        FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
 
+  *            @arg SYSCFG_MemoryRemap_SRAM:        Embedded SRAM (112kB) mapped at 0x00000000
 
+  * @retval None
 
+  */
 
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
 
+
 
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the GPIO pin used as EXTI Line.
 
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
 
+  *          EXTI lines where x can be (A..I).
 
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
 
+  *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
 
+  *           for EXTI_PortSourceGPIOI x can be (0..11).
 
+  * @retval None
 
+  */
 
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 
+{
 
+  uint32_t tmp = 0x00;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
 
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
 
+
 
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
 
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
 
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
 
+}
 
+
 
+/**
 
+  * @brief  Selects the ETHERNET media interface 
+  * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
+  *          This parameter can be one of the following values: 
+  *            @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
 
+  *            @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 
+  * @retval None 
+  */
 
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 
+{ 
+  assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the I/O Compensation Cell.
 
+  * @note   The I/O compensation cell can be used only when the device supply
 
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @param  NewState: new state of the I/O Compensation Cell.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg ENABLE: I/O compensation cell enabled  
+  *            @arg DISABLE: I/O compensation cell power-down mode  
+  * @retval None
 
+  */
 
+void SYSCFG_CompensationCellCmd(FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
 
+  * @param  None
 
+  * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
 
+  */
 
+FlagStatus SYSCFG_GetCompensationCellStatus(void)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+    
+  if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 3358 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_tim.c
Ver arquivo 

@@ -0,0 +1,3358 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_tim.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM peripheral:
 
+  *            - TimeBase management
 
+  *            - Output Compare management
 
+  *            - Input Capture management
 
+  *            - Advanced-control timers (TIM1 and TIM8) specific features  
+  *            - Interrupts, DMA and flags management
 
+  *            - Clocks management
 
+  *            - Synchronization management
 
+  *            - Specific interface management
 
+  *            - Specific remapping management      
+  *              
+  *  @verbatim
 
+  *  
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *          This driver provides functions to configure and program the TIM 
+  *          of all STM32F4xx devices.
 
+  *          These functions are split in 9 groups: 
+  *   
+  *          1. TIM TimeBase management: this group includes all needed functions 
+  *             to configure the TM Timebase unit:
 
+  *                   - Set/Get Prescaler
 
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
 
+  *                   - Set Clock division  
+  *                   - Select the One Pulse mode
 
+  *                   - Update Request Configuration
 
+  *                   - Update Disable Configuration
 
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter     
+  *                 
+  *          2. TIM Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
 
+  *                   - Select the output compare modes
 
+  *                   - Select the Polarities of each channel
 
+  *                   - Set/Get the Capture/Compare register values
 
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Clear Output Compare Reference
 
+  *                   - Select the OCREF Clear signal
 
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
 
+  *                   - Configure each channel in input capture mode
 
+  *                   - Configure Channel1/2 in PWM Input mode
 
+  *                   - Set the Input Capture Prescaler
 
+  *                   - Get the Capture/Compare values      
+  *                   
+  *          4. Advanced-control timers (TIM1 and TIM8) specific features
 
+  *                   - Configures the Break input, dead time, Lock level, the OSSI,
 
+  *                      the OSSR State and the AOE(automatic output enable)
 
+  *                   - Enable/Disable the TIM peripheral Main Outputs
 
+  *                   - Select the Commutation event
 
+  *                   - Set/Reset the Capture Compare Preload Control bit
 
+  *                              
+  *          5. TIM interrupts, DMA and flags management
 
+  *                   - Enable/Disable interrupt sources
 
+  *                   - Get flags status
 
+  *                   - Clear flags/ Pending bits
 
+  *                   - Enable/Disable DMA requests 
+  *                   - Configure DMA burst mode
 
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          6. TIM clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
 
+  *                   - Select internal/External clock
 
+  *                   - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
 
+  *         
+  *          7. TIM synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
 
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          8. TIM specific interface management, this group includes all 
+  *             needed functions to use the specific TIM interface:
 
+  *                   - Encoder Interface Configuration
 
+  *                   - Select Hall Sensor   
+  *         
+  *          9. TIM specific remapping management includes the Remapping 
+  *             configuration of specific timers               
+  *   
+  *  @endverbatim
 
+  *    
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_tim.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup TIM 
+  * @brief TIM driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* ---------------------- TIM registers bit mask ------------------------ */
 
+#define SMCR_ETR_MASK      ((uint16_t)0x00FF) 
+#define CCMR_OFFSET        ((uint16_t)0x0018)
 
+#define CCER_CCE_SET       ((uint16_t)0x0001)  
+#define	CCER_CCNE_SET      ((uint16_t)0x0004) 
+#define CCMR_OC13M_MASK    ((uint16_t)0xFF8F)
 
+#define CCMR_OC24M_MASK    ((uint16_t)0x8FFF) 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter);
 
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter);
 
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter);
 
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter);
 
+
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup TIM_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup TIM_Group1 TimeBase management functions
 
+ *  @brief   TimeBase management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       TimeBase management functions
 
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM Driver: how to use it in Timing(Time base) Mode
 
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
 
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
 
+                    
+       2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
 
+       
+       3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
 
+          with the corresponding configuration
 
+          
+       4. Enable the NVIC if you need to generate the update interrupt. 
+          
+       5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) 
+       
+       6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
 
+             
+       Note1: All other functions can be used separately to modify, if needed,
 
+          a specific feature of the Timer. 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @retval None
 
+
 
+  */
 
+void TIM_DeInit(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+ 
+  if (TIMx == TIM1)
 
+  {
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  } 
+  else if (TIMx == TIM2) 
+  {     
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
 
+  }  
+  else if (TIMx == TIM3)
 
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
 
+  }  
+  else if (TIMx == TIM4)
 
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
 
+  }  
+  else if (TIMx == TIM5)
 
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
 
+  }  
+  else if (TIMx == TIM6)  
+  {    
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
 
+  }  
+  else if (TIMx == TIM7)
 
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
 
+  }  
+  else if (TIMx == TIM8)
 
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
+  }  
+  else if (TIMx == TIM9)
 
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
+   }  
+  else if (TIMx == TIM10)
 
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
+  }  
+  else if (TIMx == TIM11) 
+  {     
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
+  }  
+  else if (TIMx == TIM12)
 
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
+  }  
+  else if (TIMx == TIM13) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
+  }  
+  else
 
+  { 
+    if (TIMx == TIM14) 
+    {     
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 
+    }   
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
 
+  * @param  TIMx: where x can be  1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
 
+  *         that contains the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
 
+{
 
+  uint16_t tmpcr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
 
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
 
+
 
+  tmpcr1 = TIMx->CR1;  
+
 
+  if((TIMx == TIM1) || (TIMx == TIM8)||
 
+     (TIMx == TIM2) || (TIMx == TIM3)||
 
+     (TIMx == TIM4) || (TIMx == TIM5)) 
+  {
 
+    /* Select the Counter Mode */
 
+    tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
 
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
 
+  }
 
+ 
+  if((TIMx != TIM6) && (TIMx != TIM7))
 
+  {
 
+    /* Set the clock division */
 
+    tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
 
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
 
+  }
 
+
 
+  TIMx->CR1 = tmpcr1;
 
+
 
+  /* Set the Autoreload value */
 
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
 
+ 
+  /* Set the Prescaler value */
 
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
 
+    
+  if ((TIMx == TIM1) || (TIMx == TIM8))  
+  {
 
+    /* Set the Repetition Counter value */
 
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
 
+  }
 
+
 
+  /* Generate an update event to reload the Prescaler 
+     and the repetition counter(only for TIM1 and TIM8) value immediatly */
 
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;          
+}
 
+
 
+/**
 
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
 
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
 
+  *         structure which will be initialized.
 
+  * @retval None
 
+  */
 
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
 
+{
 
+  /* Set the default configuration */
 
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
 
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
 
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
 
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
 
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Prescaler.
 
+  * @param  TIMx: where x can be  1 to 14 to select the TIM peripheral.
 
+  * @param  Prescaler: specifies the Prescaler Register value
 
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
 
+  *            @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
 
+  * @retval None
 
+  */
 
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
 
+  /* Set the Prescaler value */
 
+  TIMx->PSC = Prescaler;
 
+  /* Set or reset the UG Bit */
 
+  TIMx->EGR = TIM_PSCReloadMode;
 
+}
 
+
 
+/**
 
+  * @brief  Specifies the TIMx Counter Mode to be used.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_CounterMode_Up: TIM Up Counting Mode
 
+  *            @arg TIM_CounterMode_Down: TIM Down Counting Mode
 
+  *            @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
 
+  *            @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
 
+  *            @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
 
+  * @retval None
 
+  */
 
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
 
+{
 
+  uint16_t tmpcr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
 
+
 
+  tmpcr1 = TIMx->CR1;
 
+
 
+  /* Reset the CMS and DIR Bits */
 
+  tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
 
+
 
+  /* Set the Counter Mode */
 
+  tmpcr1 |= TIM_CounterMode;
 
+
 
+  /* Write to TIMx CR1 register */
 
+  TIMx->CR1 = tmpcr1;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Counter Register value
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  Counter: specifies the Counter register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
 
+{
 
+  /* Check the parameters */
 
+   assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+
 
+  /* Set the Counter Register value */
 
+  TIMx->CNT = Counter;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Autoreload Register value
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  Autoreload: specifies the Autoreload register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  
+  /* Set the Autoreload Register value */
 
+  TIMx->ARR = Autoreload;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Counter value.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @retval Counter Register value
 
+  */
 
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+
 
+  /* Get the Counter Register value */
 
+  return TIMx->CNT;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Prescaler value.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @retval Prescaler Register value.
 
+  */
 
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+
 
+  /* Get the Prescaler Register value */
 
+  return TIMx->PSC;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or Disables the TIMx Update event.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  NewState: new state of the TIMx UDIS bit
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the Update Disable Bit */
 
+    TIMx->CR1 |= TIM_CR1_UDIS;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the Update Disable Bit */
 
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Update Request Interrupt source.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_UpdateSource: specifies the Update source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_UpdateSource_Global: Source of update is the counter
 
+  *                 overflow/underflow or the setting of UG bit, or an update
 
+  *                 generation through the slave mode controller.
 
+  *            @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
 
+  * @retval None
 
+  */
 
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
 
+
 
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
 
+  {
 
+    /* Set the URS Bit */
 
+    TIMx->CR1 |= TIM_CR1_URS;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the URS Bit */
 
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  NewState: new state of the TIMx peripheral Preload register
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the ARR Preload Bit */
 
+    TIMx->CR1 |= TIM_CR1_ARPE;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the ARR Preload Bit */
 
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Selects the TIMx's One Pulse Mode.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OPMode_Single
 
+  *            @arg TIM_OPMode_Repetitive
 
+  * @retval None
 
+  */
 
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
 
+
 
+  /* Reset the OPM Bit */
 
+  TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
 
+
 
+  /* Configure the OPM Mode */
 
+  TIMx->CR1 |= TIM_OPMode;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Clock Division value.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_CKD: specifies the clock division value.
 
+  *          This parameter can be one of the following value:
 
+  *            @arg TIM_CKD_DIV1: TDTS = Tck_tim
 
+  *            @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
 
+  *            @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
 
+  * @retval None
 
+  */
 
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
 
+
 
+  /* Reset the CKD Bits */
 
+  TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
 
+
 
+  /* Set the CKD value */
 
+  TIMx->CR1 |= TIM_CKD;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified TIM peripheral.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIMx peripheral.
 
+  * @param  NewState: new state of the TIMx peripheral.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the TIM Counter */
 
+    TIMx->CR1 |= TIM_CR1_CEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the TIM Counter */
 
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group2 Output Compare management functions
 
+ *  @brief    Output Compare management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                        Output Compare management functions
 
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM Driver: how to use it in Output Compare Mode
 
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
 
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
 
+       
+       2. Configure the TIM pins by configuring the corresponding GPIO pins
 
+       
+       2. Configure the Time base unit as described in the first part of this driver, 
+          if needed, else the Timer will run with the default configuration:
 
+          - Autoreload value = 0xFFFF
 
+          - Prescaler value = 0x0000
 
+          - Counter mode = Up counting
 
+          - Clock Division = TIM_CKD_DIV1
 
+          
+       3. Fill the TIM_OCInitStruct with the desired parameters including:
 
+          - The TIM Output Compare mode: TIM_OCMode
 
+          - TIM Output State: TIM_OutputState
 
+          - TIM Pulse value: TIM_Pulse
 
+          - TIM Output Compare Polarity : TIM_OCPolarity
 
+       
+       4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the 
+          corresponding configuration
 
+       
+       5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
 
+       
+       Note1: All other functions can be used separately to modify, if needed,
 
+              a specific feature of the Timer. 
+          
+       Note2: In case of PWM mode, this function is mandatory:
 
+              TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 
+              
+       Note3: If the corresponding interrupt or DMA request are needed, the user should:
 
+                1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 
+                2. Enable the corresponding interrupt (or DMA request) using the function 
+                   TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))   
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Initializes the TIMx Channel1 according to the specified parameters in
 
+  *         the TIM_OCInitStruct.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
 
+{
 
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
 
+   
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
 
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
 
+  /* Disable the Channel 1: Reset the CC1E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
 
+  
+  /* Get the TIMx CCER register value */
 
+  tmpccer = TIMx->CCER;
 
+  /* Get the TIMx CR2 register value */
 
+  tmpcr2 =  TIMx->CR2;
 
+  
+  /* Get the TIMx CCMR1 register value */
 
+  tmpccmrx = TIMx->CCMR1;
 
+    
+  /* Reset the Output Compare Mode Bits */
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
 
+  /* Select the Output Compare Mode */
 
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
 
+  
+  /* Reset the Output Polarity level */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC1P;
 
+  /* Set the Output Compare Polarity */
 
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
 
+  
+  /* Set the Output State */
 
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
 
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
 
+  {
 
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
 
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
 
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
 
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
 
+    
+    /* Reset the Output N Polarity level */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
 
+    /* Set the Output N Polarity */
 
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
 
+    /* Reset the Output N State */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
 
+    
+    /* Set the Output N State */
 
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
 
+    /* Reset the Output Compare and Output Compare N IDLE State */
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
 
+    /* Set the Output Idle state */
 
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
 
+    /* Set the Output N Idle state */
 
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
 
+  }
 
+  /* Write to TIMx CR2 */
 
+  TIMx->CR2 = tmpcr2;
 
+  
+  /* Write to TIMx CCMR1 */
 
+  TIMx->CCMR1 = tmpccmrx;
 
+  
+  /* Set the Capture Compare Register value */
 
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
 
+  
+  /* Write to TIMx CCER */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the TIMx Channel2 according to the specified parameters 
+  *         in the TIM_OCInitStruct.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
 
+{
 
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
 
+   
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
 
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
 
+  /* Disable the Channel 2: Reset the CC2E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
 
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
 
+  /* Get the TIMx CR2 register value */
 
+  tmpcr2 =  TIMx->CR2;
 
+  
+  /* Get the TIMx CCMR1 register value */
 
+  tmpccmrx = TIMx->CCMR1;
 
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
 
+  
+  /* Select the Output Compare Mode */
 
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
 
+  
+  /* Reset the Output Polarity level */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC2P;
 
+  /* Set the Output Compare Polarity */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
 
+  
+  /* Set the Output State */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
 
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
 
+  {
 
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
 
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
 
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
 
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
 
+    
+    /* Reset the Output N Polarity level */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
 
+    /* Set the Output N Polarity */
 
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
 
+    /* Reset the Output N State */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
 
+    
+    /* Set the Output N State */
 
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
 
+    /* Reset the Output Compare and Output Compare N IDLE State */
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
 
+    /* Set the Output Idle state */
 
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
 
+    /* Set the Output N Idle state */
 
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
 
+  }
 
+  /* Write to TIMx CR2 */
 
+  TIMx->CR2 = tmpcr2;
 
+  
+  /* Write to TIMx CCMR1 */
 
+  TIMx->CCMR1 = tmpccmrx;
 
+  
+  /* Set the Capture Compare Register value */
 
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
 
+  
+  /* Write to TIMx CCER */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the TIMx Channel3 according to the specified parameters
 
+  *         in the TIM_OCInitStruct.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
 
+{
 
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
 
+   
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
 
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
 
+  /* Disable the Channel 3: Reset the CC2E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
 
+  
+  /* Get the TIMx CCER register value */
 
+  tmpccer = TIMx->CCER;
 
+  /* Get the TIMx CR2 register value */
 
+  tmpcr2 =  TIMx->CR2;
 
+  
+  /* Get the TIMx CCMR2 register value */
 
+  tmpccmrx = TIMx->CCMR2;
 
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;  
+  /* Select the Output Compare Mode */
 
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
 
+  
+  /* Reset the Output Polarity level */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
 
+  /* Set the Output Compare Polarity */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
 
+  
+  /* Set the Output State */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
 
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
 
+  {
 
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
 
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
 
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
 
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
 
+    
+    /* Reset the Output N Polarity level */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
 
+    /* Set the Output N Polarity */
 
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
 
+    /* Reset the Output N State */
 
+    tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
 
+    
+    /* Set the Output N State */
 
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
 
+    /* Reset the Output Compare and Output Compare N IDLE State */
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
 
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
 
+    /* Set the Output Idle state */
 
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
 
+    /* Set the Output N Idle state */
 
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
 
+  }
 
+  /* Write to TIMx CR2 */
 
+  TIMx->CR2 = tmpcr2;
 
+  
+  /* Write to TIMx CCMR2 */
 
+  TIMx->CCMR2 = tmpccmrx;
 
+  
+  /* Set the Capture Compare Register value */
 
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
 
+  
+  /* Write to TIMx CCER */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the TIMx Channel4 according to the specified parameters
 
+  *         in the TIM_OCInitStruct.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
 
+{
 
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
 
+   
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
 
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
 
+  /* Disable the Channel 4: Reset the CC4E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
 
+  
+  /* Get the TIMx CCER register value */
 
+  tmpccer = TIMx->CCER;
 
+  /* Get the TIMx CR2 register value */
 
+  tmpcr2 =  TIMx->CR2;
 
+  
+  /* Get the TIMx CCMR2 register value */
 
+  tmpccmrx = TIMx->CCMR2;
 
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
 
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
 
+  
+  /* Select the Output Compare Mode */
 
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
 
+  
+  /* Reset the Output Polarity level */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
 
+  /* Set the Output Compare Polarity */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
 
+  
+  /* Set the Output State */
 
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
 
+  
+  if((TIMx == TIM1) || (TIMx == TIM8))
 
+  {
 
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
 
+    /* Reset the Output Compare IDLE State */
 
+    tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
 
+    /* Set the Output Idle state */
 
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
 
+  }
 
+  /* Write to TIMx CR2 */
 
+  TIMx->CR2 = tmpcr2;
 
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
 
+    
+  /* Set the Capture Compare Register value */
 
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
 
+  
+  /* Write to TIMx CCER */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
 
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
 
+{
 
+  /* Set the default configuration */
 
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
 
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
 
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
 
+  TIM_OCInitStruct->TIM_Pulse = 0x00000000;
 
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
 
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
 
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
 
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the TIM Output Compare Mode.
 
+  * @note   This function disables the selected channel before changing the Output
 
+  *         Compare Mode. If needed, user has to enable this channel using
 
+  *         TIM_CCxCmd() and TIM_CCxNCmd() functions.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_Channel: specifies the TIM Channel
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_Channel_1: TIM Channel 1
 
+  *            @arg TIM_Channel_2: TIM Channel 2
 
+  *            @arg TIM_Channel_3: TIM Channel 3
 
+  *            @arg TIM_Channel_4: TIM Channel 4
 
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
 
+  *           This parameter can be one of the following values:
 
+  *            @arg TIM_OCMode_Timing
 
+  *            @arg TIM_OCMode_Active
 
+  *            @arg TIM_OCMode_Toggle
 
+  *            @arg TIM_OCMode_PWM1
 
+  *            @arg TIM_OCMode_PWM2
 
+  *            @arg TIM_ForcedAction_Active
 
+  *            @arg TIM_ForcedAction_InActive
 
+  * @retval None
 
+  */
 
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
 
+{
 
+  uint32_t tmp = 0;
 
+  uint16_t tmp1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
 
+  assert_param(IS_TIM_OCM(TIM_OCMode));
 
+
 
+  tmp = (uint32_t) TIMx;
 
+  tmp += CCMR_OFFSET;
 
+
 
+  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
 
+
 
+  /* Disable the Channel: Reset the CCxE Bit */
 
+  TIMx->CCER &= (uint16_t) ~tmp1;
 
+
 
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
 
+  {
 
+    tmp += (TIM_Channel>>1);
 
+
 
+    /* Reset the OCxM bits in the CCMRx register */
 
+    *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
 
+   
+    /* Configure the OCxM bits in the CCMRx register */
 
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
 
+  }
 
+  else
 
+  {
 
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
 
+
 
+    /* Reset the OCxM bits in the CCMRx register */
 
+    *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
 
+    
+    /* Configure the OCxM bits in the CCMRx register */
 
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Capture Compare1 Register value
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  Compare1: specifies the Capture Compare1 register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+
 
+  /* Set the Capture Compare1 Register value */
 
+  TIMx->CCR1 = Compare1;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Capture Compare2 Register value
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  Compare2: specifies the Capture Compare2 register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+
 
+  /* Set the Capture Compare2 Register value */
 
+  TIMx->CCR2 = Compare2;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Capture Compare3 Register value
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  Compare3: specifies the Capture Compare3 register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+
 
+  /* Set the Capture Compare3 Register value */
 
+  TIMx->CCR3 = Compare3;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Capture Compare4 Register value
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  Compare4: specifies the Capture Compare4 register new value.
 
+  * @retval None
 
+  */
 
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+
 
+  /* Set the Capture Compare4 Register value */
 
+  TIMx->CCR4 = Compare4;
 
+}
 
+
 
+/**
 
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ForcedAction_Active: Force active level on OC1REF
 
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
 
+  * @retval None
 
+  */
 
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC1M Bits */
 
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
 
+
 
+  /* Configure The Forced output Mode */
 
+  tmpccmr1 |= TIM_ForcedAction;
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ForcedAction_Active: Force active level on OC2REF
 
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
 
+  * @retval None
 
+  */
 
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC2M Bits */
 
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
 
+
 
+  /* Configure The Forced output Mode */
 
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ForcedAction_Active: Force active level on OC3REF
 
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
 
+  * @retval None
 
+  */
 
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
 
+
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC1M Bits */
 
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
 
+
 
+  /* Configure The Forced output Mode */
 
+  tmpccmr2 |= TIM_ForcedAction;
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ForcedAction_Active: Force active level on OC4REF
 
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
 
+  * @retval None
 
+  */
 
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC2M Bits */
 
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
 
+
 
+  /* Configure The Forced output Mode */
 
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPreload_Enable
 
+  *            @arg TIM_OCPreload_Disable
 
+  * @retval None
 
+  */
 
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
 
+
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC1PE Bit */
 
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
 
+
 
+  /* Enable or Disable the Output Compare Preload feature */
 
+  tmpccmr1 |= TIM_OCPreload;
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPreload_Enable
 
+  *            @arg TIM_OCPreload_Disable
 
+  * @retval None
 
+  */
 
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
 
+
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC2PE Bit */
 
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
 
+
 
+  /* Enable or Disable the Output Compare Preload feature */
 
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPreload_Enable
 
+  *            @arg TIM_OCPreload_Disable
 
+  * @retval None
 
+  */
 
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
 
+
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC3PE Bit */
 
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
 
+
 
+  /* Enable or Disable the Output Compare Preload feature */
 
+  tmpccmr2 |= TIM_OCPreload;
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPreload_Enable
 
+  *            @arg TIM_OCPreload_Disable
 
+  * @retval None
 
+  */
 
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
 
+
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC4PE Bit */
 
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
 
+
 
+  /* Enable or Disable the Output Compare Preload feature */
 
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
 
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
 
+  * @retval None
 
+  */
 
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
 
+
 
+  /* Get the TIMx CCMR1 register value */
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC1FE Bit */
 
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
 
+
 
+  /* Enable or Disable the Output Compare Fast Bit */
 
+  tmpccmr1 |= TIM_OCFast;
 
+
 
+  /* Write to TIMx CCMR1 */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
 
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
 
+  * @retval None
 
+  */
 
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
 
+
 
+  /* Get the TIMx CCMR1 register value */
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC2FE Bit */
 
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
 
+
 
+  /* Enable or Disable the Output Compare Fast Bit */
 
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
 
+
 
+  /* Write to TIMx CCMR1 */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
 
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
 
+  * @retval None
 
+  */
 
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+  
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
 
+
 
+  /* Get the TIMx CCMR2 register value */
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC3FE Bit */
 
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
 
+
 
+  /* Enable or Disable the Output Compare Fast Bit */
 
+  tmpccmr2 |= TIM_OCFast;
 
+
 
+  /* Write to TIMx CCMR2 */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
 
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
 
+  * @retval None
 
+  */
 
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
 
+
 
+  /* Get the TIMx CCMR2 register value */
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC4FE Bit */
 
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
 
+
 
+  /* Enable or Disable the Output Compare Fast Bit */
 
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
 
+
 
+  /* Write to TIMx CCMR2 */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
 
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
 
+  * @retval None
 
+  */
 
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
 
+
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC1CE Bit */
 
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
 
+
 
+  /* Enable or Disable the Output Compare Clear Bit */
 
+  tmpccmr1 |= TIM_OCClear;
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
 
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
 
+  * @retval None
 
+  */
 
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
 
+{
 
+  uint16_t tmpccmr1 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
 
+
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Reset the OC2CE Bit */
 
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
 
+
 
+  /* Enable or Disable the Output Compare Clear Bit */
 
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
 
+
 
+  /* Write to TIMx CCMR1 register */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+}
 
+
 
+/**
 
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
 
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
 
+  * @retval None
 
+  */
 
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
 
+
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC3CE Bit */
 
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
 
+
 
+  /* Enable or Disable the Output Compare Clear Bit */
 
+  tmpccmr2 |= TIM_OCClear;
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
 
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
 
+  * @retval None
 
+  */
 
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
 
+{
 
+  uint16_t tmpccmr2 = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
 
+
 
+  tmpccmr2 = TIMx->CCMR2;
 
+
 
+  /* Reset the OC4CE Bit */
 
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
 
+
 
+  /* Enable or Disable the Output Compare Clear Bit */
 
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
 
+
 
+  /* Write to TIMx CCMR2 register */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx channel 1 polarity.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
 
+
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC1P Bit */
 
+  tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
 
+  tmpccer |= TIM_OCPolarity;
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Channel 1N polarity.
 
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
 
+   
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC1NP Bit */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
 
+  tmpccer |= TIM_OCNPolarity;
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx channel 2 polarity.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
 
+
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC2P Bit */
 
+  tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
 
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Channel 2N polarity.
 
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
 
+  
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC2NP Bit */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
 
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx channel 3 polarity.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
 
+
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC3P Bit */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
 
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Channel 3N polarity.
 
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+ 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
 
+    
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC3NP Bit */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
 
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx channel 4 polarity.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_OCPolarity_High: Output Compare active high
 
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
 
+  * @retval None
 
+  */
 
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
 
+{
 
+  uint16_t tmpccer = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
 
+
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set or Reset the CC4P Bit */
 
+  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
 
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
 
+
 
+  /* Write to TIMx CCER register */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_Channel: specifies the TIM Channel
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_Channel_1: TIM Channel 1
 
+  *            @arg TIM_Channel_2: TIM Channel 2
 
+  *            @arg TIM_Channel_3: TIM Channel 3
 
+  *            @arg TIM_Channel_4: TIM Channel 4
 
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
 
+  *          This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
 
+  */
 
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
 
+{
 
+  uint16_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
 
+  assert_param(IS_TIM_CCX(TIM_CCx));
 
+
 
+  tmp = CCER_CCE_SET << TIM_Channel;
 
+
 
+  /* Reset the CCxE Bit */
 
+  TIMx->CCER &= (uint16_t)~ tmp;
 
+
 
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
 
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
 
+  * @param  TIM_Channel: specifies the TIM Channel
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_Channel_1: TIM Channel 1
 
+  *            @arg TIM_Channel_2: TIM Channel 2
 
+  *            @arg TIM_Channel_3: TIM Channel 3
 
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
 
+  *          This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
 
+  */
 
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
 
+{
 
+  uint16_t tmp = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
 
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
 
+
 
+  tmp = CCER_CCNE_SET << TIM_Channel;
 
+
 
+  /* Reset the CCxNE Bit */
 
+  TIMx->CCER &= (uint16_t) ~tmp;
 
+
 
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group3 Input Capture management functions
 
+ *  @brief    Input Capture management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                      Input Capture management functions
 
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM Driver: how to use it in Input Capture Mode
 
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
 
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
 
+       
+       2. Configure the TIM pins by configuring the corresponding GPIO pins
 
+       
+       2. Configure the Time base unit as described in the first part of this driver,
 
+          if needed, else the Timer will run with the default configuration:
 
+          - Autoreload value = 0xFFFF
 
+          - Prescaler value = 0x0000
 
+          - Counter mode = Up counting
 
+          - Clock Division = TIM_CKD_DIV1
 
+          
+       3. Fill the TIM_ICInitStruct with the desired parameters including:
 
+          - TIM Channel: TIM_Channel
 
+          - TIM Input Capture polarity: TIM_ICPolarity
 
+          - TIM Input Capture selection: TIM_ICSelection
 
+          - TIM Input Capture Prescaler: TIM_ICPrescaler
 
+          - TIM Input CApture filter value: TIM_ICFilter
 
+       
+       4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the 
+          corresponding configuration and to measure only frequency or duty cycle of the input signal,
 
+          or,
 
+          Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty cycle of the input signal
 
+          
+       5. Enable the NVIC or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
 
+          using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 
+       
+       7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
 
+       
+       8. Use TIM_GetCapturex(TIMx); to read the captured value.
 
+       
+       Note1: All other functions can be used separately to modify, if needed,
 
+              a specific feature of the Timer. 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Initializes the TIM peripheral according to the specified parameters
 
+  *         in the TIM_ICInitStruct.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
 
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
 
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
 
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
 
+  
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
 
+  {
 
+    /* TI1 Configuration */
 
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
 
+               TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
 
+  {
 
+    /* TI2 Configuration */
 
+    assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
 
+               TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
 
+  {
 
+    /* TI3 Configuration */
 
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
 
+               TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+  else
 
+  {
 
+    /* TI4 Configuration */
 
+    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
 
+               TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
 
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
 
+{
 
+  /* Set the default configuration */
 
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
 
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
 
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
 
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
 
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIM peripheral according to the specified parameters
 
+  *         in the TIM_ICInitStruct to measure an external PWM signal.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5,8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
 
+  *         the configuration information for the specified TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
 
+{
 
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
 
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+
 
+  /* Select the Opposite Input Polarity */
 
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
 
+  {
 
+    icoppositepolarity = TIM_ICPolarity_Falling;
 
+  }
 
+  else
 
+  {
 
+    icoppositepolarity = TIM_ICPolarity_Rising;
 
+  }
 
+  /* Select the Opposite Input */
 
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
 
+  {
 
+    icoppositeselection = TIM_ICSelection_IndirectTI;
 
+  }
 
+  else
 
+  {
 
+    icoppositeselection = TIM_ICSelection_DirectTI;
 
+  }
 
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
 
+  {
 
+    /* TI1 Configuration */
 
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+    /* TI2 Configuration */
 
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+  else
 
+  { 
+    /* TI2 Configuration */
 
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
 
+               TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+    /* TI1 Configuration */
 
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
 
+    /* Set the Input Capture Prescaler value */
 
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Input Capture 1 value.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @retval Capture Compare 1 Register value.
 
+  */
 
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+
 
+  /* Get the Capture 1 Register value */
 
+  return TIMx->CCR1;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Input Capture 2 value.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @retval Capture Compare 2 Register value.
 
+  */
 
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+
 
+  /* Get the Capture 2 Register value */
 
+  return TIMx->CCR2;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Input Capture 3 value.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @retval Capture Compare 3 Register value.
 
+  */
 
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+
 
+  /* Get the Capture 3 Register value */
 
+  return TIMx->CCR3;
 
+}
 
+
 
+/**
 
+  * @brief  Gets the TIMx Input Capture 4 value.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @retval Capture Compare 4 Register value.
 
+  */
 
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+
 
+  /* Get the Capture 4 Register value */
 
+  return TIMx->CCR4;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
 
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
 
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPSC_DIV1: no prescaler
 
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 
+  * @retval None
 
+  */
 
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
 
+
 
+  /* Reset the IC1PSC Bits */
 
+  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
 
+
 
+  /* Set the IC1PSC value */
 
+  TIMx->CCMR1 |= TIM_ICPSC;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPSC_DIV1: no prescaler
 
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 
+  * @retval None
 
+  */
 
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
 
+
 
+  /* Reset the IC2PSC Bits */
 
+  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
 
+
 
+  /* Set the IC2PSC value */
 
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPSC_DIV1: no prescaler
 
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 
+  * @retval None
 
+  */
 
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
 
+
 
+  /* Reset the IC3PSC Bits */
 
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
 
+
 
+  /* Set the IC3PSC value */
 
+  TIMx->CCMR2 |= TIM_ICPSC;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPSC_DIV1: no prescaler
 
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
 
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
 
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
 
+  * @retval None
 
+  */
 
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
 
+{  
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
 
+
 
+  /* Reset the IC4PSC Bits */
 
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
 
+
 
+  /* Set the IC4PSC value */
 
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
 
+ *  @brief   Advanced-control timers (TIM1 and TIM8) specific features
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+          Advanced-control timers (TIM1 and TIM8) specific features
 
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM Driver: how to use the Break feature
 
+       =================================================================== 
+       After configuring the Timer channel(s) in the appropriate Output Compare mode: 
+                         
+       1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
 
+          Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
+          AOE(automatic output enable).
 
+               
+       2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
 
+          
+       3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
+          
+       4. Once the break even occurs, the Timer's output signals are put in reset
 
+          state or in a known state (according to the configuration made in
 
+          TIM_BDTRConfig() function).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
 
+  *         and the AOE(automatic output enable).
 
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
 
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
 
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
 
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
 
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
 
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
 
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
 
+
 
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
 
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
 
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
 
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
 
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
 
+  *         will be initialized.
 
+  * @retval None
 
+  */
 
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
 
+{
 
+  /* Set the default configuration */
 
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
 
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
 
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
 
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
 
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
 
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
 
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
 
+  * @param  TIMx: where x can be 1 or 8 to select the TIMx peripheral.
 
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the TIM Main Output */
 
+    TIMx->BDTR |= TIM_BDTR_MOE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the TIM Main Output */
 
+    TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
 
+  }  
+}
 
+
 
+/**
 
+  * @brief  Selects the TIM peripheral Commutation event.
 
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
 
+  * @param  NewState: new state of the Commutation event.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the COM Bit */
 
+    TIMx->CR2 |= TIM_CR2_CCUS;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the COM Bit */
 
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
 
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
 
+  * @param  NewState: new state of the Capture Compare Preload Control bit
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the CCPC Bit */
 
+    TIMx->CR2 |= TIM_CR2_CCPC;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the CCPC Bit */
 
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
 
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                 Interrupts, DMA and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified TIM interrupts.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIMx peripheral.
 
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg TIM_IT_Update: TIM update Interrupt source
 
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
 
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
 
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
 
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
 
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
 
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
 
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
 
+  *  
+  * @note   For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
 
+  * @note   For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
 
+  *          TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
 
+  *          be used: TIM_IT_Update or TIM_IT_CC1   
+  * @note   TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 
+  *        
+  * @param  NewState: new state of the TIM interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
 
+{  
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IT(TIM_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Interrupt sources */
 
+    TIMx->DIER |= TIM_IT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Interrupt sources */
 
+    TIMx->DIER &= (uint16_t)~TIM_IT;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx event to be generate by software.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_EventSource: specifies the event source.
 
+  *          This parameter can be one or more of the following values:	   
+  *            @arg TIM_EventSource_Update: Timer update Event source
 
+  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
 
+  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
 
+  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
 
+  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
 
+  *            @arg TIM_EventSource_COM: Timer COM event source  
+  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
 
+  *            @arg TIM_EventSource_Break: Timer Break event source
 
+  * 
+  * @note   TIM6 and TIM7 can only generate an update event. 
+  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
 
+  *        
+  * @retval None
 
+  */
 
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
 
+ 
+  /* Set the event sources */
 
+  TIMx->EGR = TIM_EventSource;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified TIM flag is set or not.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_FLAG_Update: TIM update Flag
 
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
 
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
 
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
 
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
 
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
 
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
 
+  *            @arg TIM_FLAG_Break: TIM Break Flag
 
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
 
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
 
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
 
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
 
+  *
 
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.    
+  *
 
+  * @retval The new state of TIM_FLAG (SET or RESET).
 
+  */
 
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
 
+{ 
+  ITStatus bitstatus = RESET;  
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
 
+
 
+  
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the TIMx's pending flags.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_FLAG: specifies the flag bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg TIM_FLAG_Update: TIM update Flag
 
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
 
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
 
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
 
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
 
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
 
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
 
+  *            @arg TIM_FLAG_Break: TIM Break Flag
 
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
 
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
 
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
 
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
 
+  *
 
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
 
+  *    
+  * @retval None
 
+  */
 
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
 
+{  
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+   
+  /* Clear the flags */
 
+  TIMx->SR = (uint16_t)~TIM_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the TIM interrupt has occurred or not.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_IT_Update: TIM update Interrupt source
 
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
 
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
 
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
 
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
 
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
 
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
 
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
 
+  *
 
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
 
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
 
+  *     
+  * @retval The new state of the TIM_IT(SET or RESET).
 
+  */
 
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
 
+{
 
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+  assert_param(IS_TIM_GET_IT(TIM_IT));
 
+   
+  itstatus = TIMx->SR & TIM_IT;
 
+  
+  itenable = TIMx->DIER & TIM_IT;
 
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the TIMx's interrupt pending bits.
 
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
 
+  * @param  TIM_IT: specifies the pending bit to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg TIM_IT_Update: TIM1 update Interrupt source
 
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
 
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
 
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
 
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
 
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
 
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
 
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
 
+  *
 
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
 
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
 
+  *      
+  * @retval None
 
+  */
 
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
 
+
 
+  /* Clear the IT pending Bit */
 
+  TIMx->SR = (uint16_t)~TIM_IT;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx's DMA interface.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_DMABase: DMA Base address.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_DMABase_CR1  
+  *            @arg TIM_DMABase_CR2
 
+  *            @arg TIM_DMABase_SMCR
 
+  *            @arg TIM_DMABase_DIER
 
+  *            @arg TIM1_DMABase_SR
 
+  *            @arg TIM_DMABase_EGR
 
+  *            @arg TIM_DMABase_CCMR1
 
+  *            @arg TIM_DMABase_CCMR2
 
+  *            @arg TIM_DMABase_CCER
 
+  *            @arg TIM_DMABase_CNT   
+  *            @arg TIM_DMABase_PSC   
+  *            @arg TIM_DMABase_ARR
 
+  *            @arg TIM_DMABase_RCR
 
+  *            @arg TIM_DMABase_CCR1
 
+  *            @arg TIM_DMABase_CCR2
 
+  *            @arg TIM_DMABase_CCR3  
+  *            @arg TIM_DMABase_CCR4
 
+  *            @arg TIM_DMABase_BDTR
 
+  *            @arg TIM_DMABase_DCR
 
+  * @param  TIM_DMABurstLength: DMA Burst length. This parameter can be one value
 
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
 
+  * @retval None
 
+  */
 
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
 
+
 
+  /* Set the DMA Base and the DMA Burst Length */
 
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx's DMA Requests.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
 
+  * @param  TIM_DMASource: specifies the DMA Request sources.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg TIM_DMA_Update: TIM update Interrupt source
 
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
 
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
 
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
 
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
 
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
 
+  *            @arg TIM_DMA_Trigger: TIM Trigger DMA source
 
+  * @param  NewState: new state of the DMA Request sources.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA sources */
 
+    TIMx->DIER |= TIM_DMASource; 
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA sources */
 
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  NewState: new state of the Capture Compare DMA source
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the CCDS Bit */
 
+    TIMx->CR2 |= TIM_CR2_CCDS;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the CCDS Bit */
 
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group6 Clocks management functions
 
+ *  @brief    Clocks management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Clocks management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the TIMx internal Clock
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @retval None
 
+  */
 
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+
 
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
 
+  TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Internal Trigger as External Clock
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_InputTriggerSource: Trigger source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
 
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
 
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
 
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
 
+  * @retval None
 
+  */
 
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
 
+
 
+  /* Select the Internal Trigger */
 
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
 
+
 
+  /* Select the External clock mode1 */
 
+  TIMx->SMCR |= TIM_SlaveMode_External1;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx Trigger as External Clock
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14  
+  *         to select the TIM peripheral.
 
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
 
+  *            @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
 
+  *            @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
 
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Rising
 
+  *            @arg TIM_ICPolarity_Falling
 
+  * @param  ICFilter: specifies the filter value.
 
+  *          This parameter must be a value between 0x0 and 0xF.
 
+  * @retval None
 
+  */
 
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
 
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
 
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
 
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
 
+
 
+  /* Configure the Timer Input Clock Source */
 
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
 
+  {
 
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
 
+  }
 
+  else
 
+  {
 
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
 
+  }
 
+  /* Select the Trigger source */
 
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
 
+  /* Select the External clock mode1 */
 
+  TIMx->SMCR |= TIM_SlaveMode_External1;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the External clock Mode1
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
 
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
 
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
 
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
 
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
 
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
 
+  * @param  ExtTRGFilter: External Trigger Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F
 
+  * @retval None
 
+  */
 
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
 
+                            uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 
+{
 
+  uint16_t tmpsmcr = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
 
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
 
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
 
+  /* Configure the ETR Clock source */
 
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
 
+  
+  /* Get the TIMx SMCR register value */
 
+  tmpsmcr = TIMx->SMCR;
 
+
 
+  /* Reset the SMS Bits */
 
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
 
+
 
+  /* Select the External clock mode1 */
 
+  tmpsmcr |= TIM_SlaveMode_External1;
 
+
 
+  /* Select the Trigger selection : ETRF */
 
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
 
+  tmpsmcr |= TIM_TS_ETRF;
 
+
 
+  /* Write to TIMx SMCR */
 
+  TIMx->SMCR = tmpsmcr;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the External clock Mode2
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
 
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
 
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
 
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
 
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
 
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
 
+  * @param  ExtTRGFilter: External Trigger Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F
 
+  * @retval None
 
+  */
 
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
 
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
 
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
 
+
 
+  /* Configure the ETR Clock source */
 
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
 
+
 
+  /* Enable the External clock mode2 */
 
+  TIMx->SMCR |= TIM_SMCR_ECE;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group7 Synchronization management functions
 
+ *  @brief    Synchronization management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       Synchronization management functions
 
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM Driver: how to use it in synchronization Mode
 
+       =================================================================== 
+       Case of two/several Timers
 
+       **************************
 
+       1. Configure the Master Timers using the following functions:
 
+          - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 
+          - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);  
+       2. Configure the Slave Timers using the following functions: 
+          - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+          - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+          
+       Case of Timers and external trigger(ETR pin)
 
+       ********************************************       
+       1. Configure the External trigger using this function:
 
+          - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
 
+                               uint16_t ExtTRGFilter);
 
+       2. Configure the Slave Timers using the following functions: 
+          - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+          - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Selects the Input Trigger source
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14  
+  *         to select the TIM peripheral.
 
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
 
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
 
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
 
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
 
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
 
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
 
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
 
+  *            @arg TIM_TS_ETRF: External Trigger input
 
+  * @retval None
 
+  */
 
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
 
+{
 
+  uint16_t tmpsmcr = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
 
+
 
+  /* Get the TIMx SMCR register value */
 
+  tmpsmcr = TIMx->SMCR;
 
+
 
+  /* Reset the TS Bits */
 
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
 
+
 
+  /* Set the Input Trigger source */
 
+  tmpsmcr |= TIM_InputTriggerSource;
 
+
 
+  /* Write to TIMx SMCR */
 
+  TIMx->SMCR = tmpsmcr;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the TIMx Trigger Output Mode.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
 
+  *     
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
 
+  *   This parameter can be one of the following values:
 
+  *
 
+  *  - For all TIMx
 
+  *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
 
+  *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
 
+  *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
 
+  *
 
+  *  - For all TIMx except TIM6 and TIM7
 
+  *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
 
+  *                                     is to be set, as soon as a capture or compare match occurs(TRGO)
 
+  *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
 
+  *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
 
+  *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
 
+  *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
 
+  *
 
+  * @retval None
 
+  */
 
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
 
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
 
+
 
+  /* Reset the MMS Bits */
 
+  TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
 
+  /* Select the TRGO source */
 
+  TIMx->CR2 |=  TIM_TRGOSource;
 
+}
 
+
 
+/**
 
+  * @brief  Selects the TIMx Slave Mode.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
 
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize 
+  *                                      the counter and triggers an update of the registers
 
+  *            @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high
 
+  *            @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI
 
+  *            @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
 
+  * @retval None
 
+  */
 
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
 
+
 
+  /* Reset the SMS Bits */
 
+  TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
 
+
 
+  /* Select the Slave Mode */
 
+  TIMx->SMCR |= TIM_SlaveMode;
 
+}
 
+
 
+/**
 
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
 
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
 
+  *                                             and its slaves (through TRGO)
 
+  *            @arg TIM_MasterSlaveMode_Disable: No action
 
+  * @retval None
 
+  */
 
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
 
+
 
+  /* Reset the MSM Bit */
 
+  TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
 
+  
+  /* Set or Reset the MSM Bit */
 
+  TIMx->SMCR |= TIM_MasterSlaveMode;
 
+}
 
+
 
+/**
 
+  * @brief  Configures the TIMx External Trigger (ETR).
 
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
 
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
 
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
 
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
 
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
 
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
 
+  * @param  ExtTRGFilter: External Trigger Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F
 
+  * @retval None
 
+  */
 
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
 
+                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 
+{
 
+  uint16_t tmpsmcr = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
 
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
 
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
 
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
 
+
 
+  tmpsmcr = TIMx->SMCR;
 
+
 
+  /* Reset the ETR Bits */
 
+  tmpsmcr &= SMCR_ETR_MASK;
 
+
 
+  /* Set the Prescaler, the Filter value and the Polarity */
 
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
 
+
 
+  /* Write to TIMx SMCR */
 
+  TIMx->SMCR = tmpsmcr;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group8 Specific interface management functions
 
+ *  @brief    Specific interface management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Specific interface management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the TIMx Encoder Interface.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
 
+  *            @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
 
+  *            @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
 
+  *                                       on the level of the other input.
 
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
 
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
 
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
 
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
 
+  * @retval None
 
+  */
 
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
 
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
 
+{
 
+  uint16_t tmpsmcr = 0;
 
+  uint16_t tmpccmr1 = 0;
 
+  uint16_t tmpccer = 0;
 
+    
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
 
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
 
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
 
+
 
+  /* Get the TIMx SMCR register value */
 
+  tmpsmcr = TIMx->SMCR;
 
+
 
+  /* Get the TIMx CCMR1 register value */
 
+  tmpccmr1 = TIMx->CCMR1;
 
+
 
+  /* Get the TIMx CCER register value */
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Set the encoder Mode */
 
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
 
+  tmpsmcr |= TIM_EncoderMode;
 
+
 
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
 
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
 
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
 
+
 
+  /* Set the TI1 and the TI2 Polarities */
 
+  tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
 
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
 
+
 
+  /* Write to TIMx SMCR */
 
+  TIMx->SMCR = tmpsmcr;
 
+
 
+  /* Write to TIMx CCMR1 */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+
 
+  /* Write to TIMx CCER */
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  NewState: new state of the TIMx Hall sensor interface.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Set the TI1S Bit */
 
+    TIMx->CR2 |= TIM_CR2_TI1S;
 
+  }
 
+  else
 
+  {
 
+    /* Reset the TI1S Bit */
 
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
 
+  }
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup TIM_Group9 Specific remapping management function
 
+ *  @brief   Specific remapping management function
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                     Specific remapping management function
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
 
+  * @param  TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
 
+  * @param  TIM_Remap: specifies the TIM input remapping source.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
 
+  *            @arg TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trogger output.
 
+  *            @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. 
+  *            @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. 
+  *            @arg TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
 
+  *            @arg TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
 
+  *            @arg TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
 
+  *            @arg TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
 
+  *            @arg TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
+  *            @arg TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
 
+  *                                 (HSE divided by a programmable prescaler)  
+  * @retval None
 
+  */
 
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
 
+{
 
+ /* Check the parameters */
 
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
 
+  assert_param(IS_TIM_REMAP(TIM_Remap));
 
+
 
+  /* Set the Timer remapping configuration */
 
+  TIMx->OR =  TIM_Remap;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @brief  Configure the TI1 as Input.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 
+  *         to select the TIM peripheral.
 
+  * @param  TIM_ICPolarity : The Input Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Rising
 
+  *            @arg TIM_ICPolarity_Falling
 
+  *            @arg TIM_ICPolarity_BothEdge  
+  * @param  TIM_ICSelection: specifies the input to be used.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
 
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
 
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
 
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F.
 
+  * @retval None
 
+  */
 
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter)
 
+{
 
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
 
+
 
+  /* Disable the Channel 1: Reset the CC1E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
 
+  tmpccmr1 = TIMx->CCMR1;
 
+  tmpccer = TIMx->CCER;
 
+
 
+  /* Select the Input and set the filter */
 
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
 
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
 
+
 
+  /* Select the Polarity and set the CC1E Bit */
 
+  tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 
+  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
 
+
 
+  /* Write to TIMx CCMR1 and CCER registers */
 
+  TIMx->CCMR1 = tmpccmr1;
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configure the TI2 as Input.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
 
+  * @param  TIM_ICPolarity : The Input Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Rising
 
+  *            @arg TIM_ICPolarity_Falling
 
+  *            @arg TIM_ICPolarity_BothEdge   
+  * @param  TIM_ICSelection: specifies the input to be used.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
 
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
 
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
 
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F.
 
+  * @retval None
 
+  */
 
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter)
 
+{
 
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
 
+
 
+  /* Disable the Channel 2: Reset the CC2E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
 
+  tmpccmr1 = TIMx->CCMR1;
 
+  tmpccer = TIMx->CCER;
 
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
 
+
 
+  /* Select the Input and set the filter */
 
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
 
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
 
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
 
+
 
+  /* Select the Polarity and set the CC2E Bit */
 
+  tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 
+  tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
 
+
 
+  /* Write to TIMx CCMR1 and CCER registers */
 
+  TIMx->CCMR1 = tmpccmr1 ;
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configure the TI3 as Input.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ICPolarity : The Input Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Rising
 
+  *            @arg TIM_ICPolarity_Falling
 
+  *            @arg TIM_ICPolarity_BothEdge         
+  * @param  TIM_ICSelection: specifies the input to be used.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
 
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
 
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
 
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F.
 
+  * @retval None
 
+  */
 
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter)
 
+{
 
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
 
+
 
+  /* Disable the Channel 3: Reset the CC3E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
 
+  tmpccmr2 = TIMx->CCMR2;
 
+  tmpccer = TIMx->CCER;
 
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
 
+
 
+  /* Select the Input and set the filter */
 
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
 
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
 
+
 
+  /* Select the Polarity and set the CC3E Bit */
 
+  tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
 
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
 
+
 
+  /* Write to TIMx CCMR2 and CCER registers */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+  TIMx->CCER = tmpccer;
 
+}
 
+
 
+/**
 
+  * @brief  Configure the TI4 as Input.
 
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
 
+  * @param  TIM_ICPolarity : The Input Polarity.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICPolarity_Rising
 
+  *            @arg TIM_ICPolarity_Falling
 
+  *            @arg TIM_ICPolarity_BothEdge     
+  * @param  TIM_ICSelection: specifies the input to be used.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
 
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
 
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
 
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
 
+  *          This parameter must be a value between 0x00 and 0x0F.
 
+  * @retval None
 
+  */
 
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
 
+                       uint16_t TIM_ICFilter)
 
+{
 
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
 
+
 
+  /* Disable the Channel 4: Reset the CC4E Bit */
 
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
 
+  tmpccmr2 = TIMx->CCMR2;
 
+  tmpccer = TIMx->CCER;
 
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
 
+
 
+  /* Select the Input and set the filter */
 
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
 
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
 
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
 
+
 
+  /* Select the Polarity and set the CC4E Bit */
 
+  tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
 
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
 
+
 
+  /* Write to TIMx CCMR2 and CCER registers */
 
+  TIMx->CCMR2 = tmpccmr2;
 
+  TIMx->CCER = tmpccer ;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 1469 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_usart.c
Ver arquivo 

@@ -0,0 +1,1469 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_usart.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
 
+  *          transmitter (USART):           
+  *           - Initialization and Configuration
 
+  *           - Data transfers
 
+  *           - Multi-Processor Communication
 
+  *           - LIN mode
 
+  *           - Half-duplex mode
 
+  *           - Smartcard mode
 
+  *           - IrDA mode
 
+  *           - DMA transfers management
 
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
 
+  *      
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          ===================================================================
 
+  *          1. Enable peripheral clock using the follwoing functions
 
+  *             RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 
+  *             RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5.
 
+  *
 
+  *          2.  According to the USART mode, enable the GPIO clocks using 
+  *              RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
+  *              or/and SCLK). 
+  *
 
+  *          3. Peripheral's alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
 
+  *                 - Configure the desired pin in alternate function by:
 
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
 
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
 
+  *                 - Call GPIO_Init() function
 
+  *        
+  *          4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+  *             flow control and Mode(Receiver/Transmitter) using the USART_Init()
 
+  *             function.
 
+  *
 
+  *          5. For synchronous mode, enable the clock and program the polarity,
 
+  *             phase and last bit using the USART_ClockInit() function.
 
+  *
 
+  *          5. Enable the NVIC and the corresponding interrupt using the function 
+  *             USART_ITConfig() if you need to use interrupt mode. 
+  *
 
+  *          6. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
 
+  *                   - Active the needed channel Request using USART_DMACmd() function
 
+  * 
+  *          7. Enable the USART using the USART_Cmd() function.
 
+  * 
+  *          8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  *
 
+  *          Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
 
+  *          for more details
 
+  *          
+  *          In order to reach higher communication baudrates, it is possible to
 
+  *          enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
 
+  *          This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
 
+  *          and before calling the function USART_Init().
 
+  *          
+  *  @endverbatim
 
+  *        
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */ 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_usart.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup USART 
+  * @brief USART driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
 
+#define CR1_CLEAR_MASK            ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
 
+                                              USART_CR1_PS | USART_CR1_TE | \
 
+                                              USART_CR1_RE))
 
+
 
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
 
+#define CR2_CLOCK_CLEAR_MASK      ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
 
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
 
+
 
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
 
+#define CR3_CLEAR_MASK            ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
 
+
 
+/*!< USART Interrupts mask */
 
+#define IT_MASK                   ((uint16_t)0x001F)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup USART_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup USART_Group1 Initialization and Configuration functions
 
+ *  @brief   Initialization and Configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                  Initialization and Configuration functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to initialize the USART 
+  in asynchronous and in synchronous modes.
 
+   - For the asynchronous mode only these parameters can be configured: 
+        - Baud Rate
 
+        - Word Length 
+        - Stop Bit
 
+        - Parity: If the parity is enabled, then the MSB bit of the data written
 
+          in the data register is transmitted but is changed by the parity bit.
 
+          Depending on the frame length defined by the M bit (8-bits or 9-bits),
 
+          the possible USART frame formats are as listed in the following table:
 
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
 
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
 
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
 
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
 
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
 
+   +-------------------------------------------------------------+            
+        - Hardware flow control
 
+        - Receiver/transmitter modes
 
+
 
+  The USART_Init() function follows the USART  asynchronous configuration procedure
 
+  (details for the procedure are available in reference manual (RM0090)).
 
+
 
+  - For the synchronous mode in addition to the asynchronous mode parameters these 
+    parameters should be also configured:
 
+        - USART Clock Enabled
 
+        - USART polarity
 
+        - USART phase
 
+        - USART LastBit
 
+  
+  These parameters can be configured using the USART_ClockInit() function.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @retval None
 
+  */
 
+void USART_DeInit(USART_TypeDef* USARTx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+
 
+  if (USARTx == USART1)
 
+  {
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
 
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
 
+  }
 
+  else if (USARTx == USART2)
 
+  {
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
 
+  }
 
+  else if (USARTx == USART3)
 
+  {
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
 
+  }    
+  else if (USARTx == UART4)
 
+  {
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
 
+  }
 
+  else if (USARTx == UART5)
 
+  {
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
 
+  }     
+  else
 
+  {
 
+    if (USARTx == USART6)
 
+    { 
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
 
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
 
+    }
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Initializes the USARTx peripheral according to the specified
 
+  *         parameters in the USART_InitStruct .
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
 
+  *         the configuration information for the specified USART peripheral.
 
+  * @retval None
 
+  */
 
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
 
+{
 
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
 
+  uint32_t integerdivider = 0x00;
 
+  uint32_t fractionaldivider = 0x00;
 
+  RCC_ClocksTypeDef RCC_ClocksStatus;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
 
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
 
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
 
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
 
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
 
+
 
+  /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
 
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  }
 
+
 
+/*---------------------------- USART CR2 Configuration -----------------------*/
 
+  tmpreg = USARTx->CR2;
 
+
 
+  /* Clear STOP[13:12] bits */
 
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
 
+
 
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
 
+      Set STOP[13:12] bits according to USART_StopBits value */
 
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
 
+  
+  /* Write to USART CR2 */
 
+  USARTx->CR2 = (uint16_t)tmpreg;
 
+
 
+/*---------------------------- USART CR1 Configuration -----------------------*/
 
+  tmpreg = USARTx->CR1;
 
+
 
+  /* Clear M, PCE, PS, TE and RE bits */
 
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
 
+
 
+  /* Configure the USART Word Length, Parity and mode: 
+     Set the M bits according to USART_WordLength value 
+     Set PCE and PS bits according to USART_Parity value
 
+     Set TE and RE bits according to USART_Mode value */
 
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
 
+            USART_InitStruct->USART_Mode;
 
+
 
+  /* Write to USART CR1 */
 
+  USARTx->CR1 = (uint16_t)tmpreg;
 
+
 
+/*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
 
+
 
+  /* Clear CTSE and RTSE bits */
 
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
 
+
 
+  /* Configure the USART HFC : 
+      Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
 
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
 
+
 
+  /* Write to USART CR3 */
 
+  USARTx->CR3 = (uint16_t)tmpreg;
 
+
 
+/*---------------------------- USART BRR Configuration -----------------------*/
 
+  /* Configure the USART Baud Rate */
 
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
 
+
 
+  if ((USARTx == USART1) || (USARTx == USART6))
 
+  {
 
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
 
+  }
 
+  else
 
+  {
 
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
 
+  }
 
+  
+  /* Determine the integer part */
 
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
 
+  {
 
+    /* Integer part computing in case Oversampling mode is 8 Samples */
 
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
 
+  else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
 
+  {
 
+    /* Integer part computing in case Oversampling mode is 16 Samples */
 
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
 
+  tmpreg = (integerdivider / 100) << 4;
 
+
 
+  /* Determine the fractional part */
 
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
 
+
 
+  /* Implement the fractional part in the register */
 
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
 
+  {
 
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
 
+  }
 
+  else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
 
+  {
 
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
 
+  }
 
+  
+  /* Write to USART BRR register */
 
+  USARTx->BRR = (uint16_t)tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each USART_InitStruct member with its default value.
 
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure which will
 
+  *         be initialized.
 
+  * @retval None
 
+  */
 
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
 
+{
 
+  /* USART_InitStruct members default value */
 
+  USART_InitStruct->USART_BaudRate = 9600;
 
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
 
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
 
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
 
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
 
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
 
+
 
+/**
 
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *         specified parameters in the USART_ClockInitStruct .
 
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
 
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
 
+  *         contains the configuration information for the specified  USART peripheral.
 
+  * @note   The Smart Card and Synchronous modes are not available for UART4 and UART5.    
+  * @retval None
 
+  */
 
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
 
+{
 
+  uint32_t tmpreg = 0x00;
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
 
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
 
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
 
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
 
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
 
+  tmpreg = USARTx->CR2;
 
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
 
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
 
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
 
+  /* Set CLKEN bit according to USART_Clock value */
 
+  /* Set CPOL bit according to USART_CPOL value */
 
+  /* Set CPHA bit according to USART_CPHA value */
 
+  /* Set LBCL bit according to USART_LastBit value */
 
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
 
+  /* Write to USART CR2 */
 
+  USARTx->CR2 = (uint16_t)tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
 
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
 
+  *         which will be initialized.
 
+  * @retval None
 
+  */
 
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
 
+{
 
+  /* USART_ClockInitStruct members default value */
 
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
 
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
 
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
 
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the specified USART peripheral.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USARTx peripheral.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
 
+    USARTx->CR1 |= USART_CR1_UE;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
 
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Sets the system clock prescaler.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_Prescaler: specifies the prescaler clock. 
+  * @note   The function is used for IrDA mode with UART4 and UART5.   
+  * @retval None
 
+  */
 
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
 
+{ 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  
+  /* Clear the USART prescaler */
 
+  USARTx->GTPR &= USART_GTPR_GT;
 
+  /* Set the USART prescaler */
 
+  USARTx->GTPR |= USART_Prescaler;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the USART's 8x oversampling mode.
 
+  * @note   This function has to be called before calling USART_Init() function
 
+  *         in order to have correct baudrate Divider value.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USART 8x oversampling mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
 
+    USARTx->CR1 |= USART_CR1_OVER8;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
 
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
 
+  }
 
+}  
+
 
+/**
 
+  * @brief  Enables or disables the USART's one bit sampling method.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USART one bit sampling method.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
 
+    USARTx->CR3 |= USART_CR3_ONEBIT;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group2 Data transfers functions
 
+ *  @brief   Data transfers functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                            Data transfers functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART data 
+  transfers.
 
+  
+  During an USART reception, data shifts in least significant bit first through 
+  the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) 
+  between the internal bus and the received shift register.
 
+
 
+  When a transmission is taking place, a write instruction to the USART_DR register 
+  stores the data in the TDR register and which is copied in the shift register 
+  at the end of the current transmission.
 
+
 
+  The read access of the USART_DR register can be done using the USART_ReceiveData()
 
+  function and returns the RDR buffered value. Whereas a write access to the USART_DR 
+  can be done using USART_SendData() function and stores the written data into 
+  TDR buffer.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Transmits single data through the USARTx peripheral.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  Data: the data to transmit.
 
+  * @retval None
 
+  */
 
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
 
+  USARTx->DR = (Data & (uint16_t)0x01FF);
 
+}
 
+
 
+/**
 
+  * @brief  Returns the most recent received data by the USARTx peripheral.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @retval The received data.
 
+  */
 
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  
+  /* Receive Data */
 
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group3 MultiProcessor Communication functions
 
+ *  @brief   Multi-Processor Communication functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                    Multi-Processor Communication functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART 
+  multiprocessor communication.
 
+  
+  For instance one of the USARTs can be the master, its TX output is connected to 
+  the RX input of the other USART. The others are slaves, their respective TX outputs 
+  are logically ANDed together and connected to the RX input of the master.
 
+
 
+  USART multiprocessor communication is possible through the following procedure:
 
+     1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
 
+        function.
 
+     2. Configures the USART address using the USART_SetAddress() function.
 
+     3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
 
+        using USART_WakeUpConfig() function only for the slaves.
 
+     4. Enable the USART using the USART_Cmd() function.
 
+     5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
 
+
 
+  The USART Slave exit from mute mode when receive the wake up condition.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Sets the address of the USART node.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_Address: Indicates the address of the USART node.
 
+  * @retval None
 
+  */
 
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
 
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
 
+  /* Set the USART address node */
 
+  USARTx->CR2 |= USART_Address;
 
+}
 
+
 
+/**
 
+  * @brief  Determines if the USART is in mute mode or not.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USART mute mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
 
+    USARTx->CR1 |= USART_CR1_RWU;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
 
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
 
+  }
 
+}
 
+/**
 
+  * @brief  Selects the USART WakeUp method.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_WakeUp: specifies the USART wakeup method.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
 
+  *            @arg USART_WakeUp_AddressMark: WakeUp by an address mark
 
+  * @retval None
 
+  */
 
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
 
+  
+  USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
 
+  USARTx->CR1 |= USART_WakeUp;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group4 LIN mode functions
 
+ *  @brief   LIN mode functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                                LIN mode functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART LIN 
+  Mode communication.
 
+  
+  In LIN mode, 8-bit data format with 1 stop bit is required in accordance with 
+  the LIN standard.
 
+
 
+  Only this LIN Feature is supported by the USART IP:
 
+    - LIN Master Synchronous Break send capability and LIN slave break detection
 
+      capability :  13-bit break generation and 10/11 bit break detection
 
+
 
+
 
+  USART LIN Master transmitter communication is possible through the following procedure:
 
+     1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+        Mode transmitter or Mode receiver and hardware flow control values using 
+        the USART_Init() function.
 
+     2. Enable the USART using the USART_Cmd() function.
 
+     3. Enable the LIN mode using the USART_LINCmd() function.
 
+     4. Send the break character using USART_SendBreak() function.
 
+
 
+  USART LIN Master receiver communication is possible through the following procedure:
 
+     1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+        Mode transmitter or Mode receiver and hardware flow control values using 
+        the USART_Init() function.
 
+     2. Enable the USART using the USART_Cmd() function.
 
+     3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()
 
+        function.
 
+     4. Enable the LIN mode using the USART_LINCmd() function.
 
+
 
+
 
+@note In LIN mode, the following bits must be kept cleared:
 
+        - CLKEN in the USART_CR2 register,
 
+        - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Sets the USART LIN Break detection length.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_LINBreakDetectLength_10b: 10-bit break detection
 
+  *            @arg USART_LINBreakDetectLength_11b: 11-bit break detection
 
+  * @retval None
 
+  */
 
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
 
+  
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
 
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the USART's LIN mode.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USART LIN mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
 
+    USARTx->CR2 |= USART_CR2_LINEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
 
+    USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Transmits break characters.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @retval None
 
+  */
 
+void USART_SendBreak(USART_TypeDef* USARTx)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  
+  /* Send break characters */
 
+  USARTx->CR1 |= USART_CR1_SBK;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group5 Halfduplex mode function
 
+ *  @brief   Half-duplex mode function 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                         Half-duplex mode function
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART 
+  Half-duplex communication.
 
+  
+  The USART can be configured to follow a single-wire half-duplex protocol where 
+  the TX and RX lines are internally connected.
 
+
 
+  USART Half duplex communication is possible through the following procedure:
 
+     1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
 
+        function.
 
+     2. Configures the USART address using the USART_SetAddress() function.
 
+     3. Enable the USART using the USART_Cmd() function.
 
+     4. Enable the half duplex mode using USART_HalfDuplexCmd() function.
 
+
 
+
 
+@note The RX pin is no longer used
 
+@note In Half-duplex mode the following bits must be kept cleared:
 
+        - LINEN and CLKEN bits in the USART_CR2 register.
 
+        - SCEN and IREN bits in the USART_CR3 register.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the USART's Half Duplex communication.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the USART Communication.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
 
+    USARTx->CR3 |= USART_CR3_HDSEL;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+
 
+/** @defgroup USART_Group6 Smartcard mode functions
 
+ *  @brief   Smartcard mode functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                               Smartcard mode functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART 
+  Smartcard communication.
 
+  
+  The Smartcard interface is designed to support asynchronous protocol Smartcards as
 
+  defined in the ISO 7816-3 standard.
 
+
 
+  The USART can provide a clock to the smartcard through the SCLK output.
 
+  In smartcard mode, SCLK is not associated to the communication but is simply derived 
+  from the internal peripheral input clock through a 5-bit prescaler.
 
+
 
+  Smartcard communication is possible through the following procedure:
 
+     1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
 
+     2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
 
+     3. Program the USART clock using the USART_ClockInit() function as following:
 
+        - USART Clock enabled
 
+        - USART CPOL Low
 
+        - USART CPHA on first edge
 
+        - USART Last Bit Clock Enabled
 
+     4. Program the Smartcard interface using the USART_Init() function as following:
 
+        - Word Length = 9 Bits
 
+        - 1.5 Stop Bit
 
+        - Even parity
 
+        - BaudRate = 12096 baud
 
+        - Hardware flow control disabled (RTS and CTS signals)
 
+        - Tx and Rx enabled
 
+     5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
 
+        function
 
+     6. Enable the USART using the USART_Cmd() function.
 
+     7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
 
+     8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
 
+
 
+  Please refer to the ISO 7816-3 specification for more details.
 
+
 
+
 
+@note It is also possible to choose 0.5 stop bit for receiving but it is recommended 
+      to use 1.5 stop bits for both transmitting and receiving to avoid switching 
+      between the two configurations.
 
+@note In smartcard mode, the following bits must be kept cleared:
 
+        - LINEN bit in the USART_CR2 register.
 
+        - HDSEL and IREN bits in the USART_CR3 register.
 
+@note Smartcard mode is available on USART peripherals only (not available on UART4 
+      and UART5 peripherals).
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Sets the specified USART guard time.
 
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_GuardTime: specifies the guard time.   
+  * @retval None
 
+  */
 
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
 
+{    
+  /* Check the parameters */
 
+  assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  
+  /* Clear the USART Guard time */
 
+  USARTx->GTPR &= USART_GTPR_PSC;
 
+  /* Set the USART guard time */
 
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the USART's Smart Card mode.
 
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the Smart Card mode.
 
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
 
+  */
 
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
 
+    USARTx->CR3 |= USART_CR3_SCEN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables NACK transmission.
 
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the NACK transmission.
 
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
 
+  */
 
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_1236_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
 
+    USARTx->CR3 |= USART_CR3_NACK;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group7 IrDA mode functions
 
+ *  @brief   IrDA mode functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                                IrDA mode functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to manage the USART 
+  IrDA communication.
 
+  
+  IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
 
+  on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+  is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
 
+  While receiving data, transmission should be avoided as the data to be transmitted
 
+  could be corrupted.
 
+
 
+  IrDA communication is possible through the following procedure:
 
+     1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver 
+        modes and hardware flow control values using the USART_Init() function.
 
+     2. Enable the USART using the USART_Cmd() function.
 
+     3. Configures the IrDA pulse width by configuring the prescaler using  
+        the USART_SetPrescaler() function.
 
+     4. Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
 
+        using the USART_IrDAConfig() function.
 
+     5. Enable the IrDA using the USART_IrDACmd() function.
 
+
 
+@note A pulse of width less than two and greater than one PSC period(s) may or may
 
+      not be rejected.
 
+@note The receiver set up time should be managed by software. The IrDA physical layer
 
+      specification specifies a minimum of 10 ms delay between transmission and 
+      reception (IrDA is a half duplex protocol).
 
+@note In IrDA mode, the following bits must be kept cleared:
 
+        - LINEN, STOP and CLKEN bits in the USART_CR2 register.
 
+        - SCEN and HDSEL bits in the USART_CR3 register.
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Configures the USART's IrDA interface.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_IrDAMode: specifies the IrDA mode.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_IrDAMode_LowPower
 
+  *            @arg USART_IrDAMode_Normal
 
+  * @retval None
 
+  */
 
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
 
+    
+  USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
 
+  USARTx->CR3 |= USART_IrDAMode;
 
+}
 
+
 
+/**
 
+  * @brief  Enables or disables the USART's IrDA interface.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  NewState: new state of the IrDA mode.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+    
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
 
+    USARTx->CR3 |= USART_CR3_IREN;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup USART_Group8 DMA transfers management functions
 
+ *  @brief   DMA transfers management functions
 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                      DMA transfers management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+  
+/**
 
+  * @brief  Enables or disables the USART's DMA interface.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_DMAReq: specifies the DMA request.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg USART_DMAReq_Tx: USART DMA transmit request
 
+  *            @arg USART_DMAReq_Rx: USART DMA receive request
 
+  * @param  NewState: new state of the DMA Request sources.
 
+  *          This parameter can be: ENABLE or DISABLE.   
+  * @retval None
 
+  */
 
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
 
+  if (NewState != DISABLE)
 
+  {
 
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
 
+       DMAR bits in the USART CR3 register */
 
+    USARTx->CR3 |= USART_DMAReq;
 
+  }
 
+  else
 
+  {
 
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
 
+       DMAR bits in the USART CR3 register */
 
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
 
+  }
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+  
+/** @defgroup USART_Group9 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                   Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+  This subsection provides a set of functions allowing to configure the USART 
+  Interrupts sources, DMA channels requests and check or clear the flags or 
+  pending bits status.
 
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
 
+  =============
 
+  In Polling Mode, the SPI communication can be managed by 10 flags:
 
+     1. USART_FLAG_TXE : to indicate the status of the transmit buffer register
 
+     2. USART_FLAG_RXNE : to indicate the status of the receive buffer register
 
+     3. USART_FLAG_TC : to indicate the status of the transmit operation
 
+     4. USART_FLAG_IDLE : to indicate the status of the Idle Line             
+     5. USART_FLAG_CTS : to indicate the status of the nCTS input
 
+     6. USART_FLAG_LBD : to indicate the status of the LIN break detection
 
+     7. USART_FLAG_NE : to indicate if a noise error occur
 
+     8. USART_FLAG_FE : to indicate if a frame error occur
 
+     9. USART_FLAG_PE : to indicate if a parity error occur
 
+     10. USART_FLAG_ORE : to indicate if an Overrun error occur
 
+
 
+  In this Mode it is advised to use the following functions:
 
+      - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
 
+      - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
 
+
 
+  Interrupt Mode
 
+  ===============
 
+  In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
 
+  and 10 pending bits: 
+
 
+  Pending Bits:
 
+  ------------- 
+     1. USART_IT_TXE : to indicate the status of the transmit buffer register
 
+     2. USART_IT_RXNE : to indicate the status of the receive buffer register
 
+     3. USART_IT_TC : to indicate the status of the transmit operation
 
+     4. USART_IT_IDLE : to indicate the status of the Idle Line             
+     5. USART_IT_CTS : to indicate the status of the nCTS input
 
+     6. USART_IT_LBD : to indicate the status of the LIN break detection
 
+     7. USART_IT_NE : to indicate if a noise error occur
 
+     8. USART_IT_FE : to indicate if a frame error occur
 
+     9. USART_IT_PE : to indicate if a parity error occur
 
+     10. USART_IT_ORE : to indicate if an Overrun error occur
 
+
 
+  Interrupt Source:
 
+  -----------------
 
+     1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty 
+                       interrupt. 
+     2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+                        empty interrupt.
 
+     3. USART_IT_TC : specifies the interrupt source for the Transmit complete 
+                       interrupt. 
+     4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.             
+     5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. 
+     6. USART_IT_LBD : specifies the interrupt source for the LIN break detection
 
+                       interrupt. 
+     7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. 
+     8. USART_IT_ERR :  specifies the interrupt source for the errors interrupt.
 
+
 
+@note Some parameters are coded in order to use them as interrupt source or as pending bits.
 
+
 
+  In this Mode it is advised to use the following functions:
 
+     - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
 
+     - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
 
+     - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
 
+
 
+  DMA Mode
 
+  ========
 
+  In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
 
+     1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
 
+     2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
 
+
 
+  In this Mode it is advised to use the following function:
 
+     - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
 
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables or disables the specified USART interrupts.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_IT_CTS:  CTS change interrupt
 
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
 
+  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
 
+  *            @arg USART_IT_TC:   Transmission complete interrupt
 
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
 
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
 
+  *            @arg USART_IT_PE:   Parity Error interrupt
 
+  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
 
+  * @param  NewState: new state of the specified USARTx interrupts.
 
+  *          This parameter can be: ENABLE or DISABLE.
 
+  * @retval None
 
+  */
 
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
 
+{
 
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
 
+  uint32_t usartxbase = 0x00;
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
 
+
 
+  /* The CTS interrupt is not available for UART4 and UART5 */
 
+  if (USART_IT == USART_IT_CTS)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  } 
+    
+  usartxbase = (uint32_t)USARTx;
 
+
 
+  /* Get the USART register index */
 
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
 
+
 
+  /* Get the interrupt position */
 
+  itpos = USART_IT & IT_MASK;
 
+  itmask = (((uint32_t)0x01) << itpos);
 
+    
+  if (usartreg == 0x01) /* The IT is in CR1 register */
 
+  {
 
+    usartxbase += 0x0C;
 
+  }
 
+  else if (usartreg == 0x02) /* The IT is in CR2 register */
 
+  {
 
+    usartxbase += 0x10;
 
+  }
 
+  else /* The IT is in CR3 register */
 
+  {
 
+    usartxbase += 0x14; 
+  }
 
+  if (NewState != DISABLE)
 
+  {
 
+    *(__IO uint32_t*)usartxbase  |= itmask;
 
+  }
 
+  else
 
+  {
 
+    *(__IO uint32_t*)usartxbase &= ~itmask;
 
+  }
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified USART flag is set or not.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_FLAG: specifies the flag to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
 
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag
 
+  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
 
+  *            @arg USART_FLAG_TC:   Transmission Complete flag
 
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
 
+  *            @arg USART_FLAG_IDLE: Idle Line detection flag
 
+  *            @arg USART_FLAG_ORE:  OverRun Error flag
 
+  *            @arg USART_FLAG_NE:   Noise Error flag
 
+  *            @arg USART_FLAG_FE:   Framing Error flag
 
+  *            @arg USART_FLAG_PE:   Parity Error flag
 
+  * @retval The new state of USART_FLAG (SET or RESET).
 
+  */
 
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_FLAG(USART_FLAG));
 
+
 
+  /* The CTS flag is not available for UART4 and UART5 */
 
+  if (USART_FLAG == USART_FLAG_CTS)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  } 
+    
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears the USARTx's pending flags.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_FLAG: specifies the flag to clear.
 
+  *          This parameter can be any combination of the following values:
 
+  *            @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
 
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag.
 
+  *            @arg USART_FLAG_TC:   Transmission Complete flag.
 
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
 
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *          sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
+  *          followed by a read operation to USART_DR register (USART_ReceiveData()).
 
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register 
+  *          (USART_ReceiveData()).
 
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register (USART_GetFlagStatus()) followed by a write operation
 
+  *          to USART_DR register (USART_SendData()).
 
+  * @note   TXE flag is cleared only by a write to the USART_DR register 
+  *          (USART_SendData()).
 
+  *   
+  * @retval None
 
+  */
 
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
 
+
 
+  /* The CTS flag is not available for UART4 and UART5 */
 
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  } 
+       
+  USARTx->SR = (uint16_t)~USART_FLAG;
 
+}
 
+
 
+/**
 
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_IT: specifies the USART interrupt source to check.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
 
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
 
+  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
 
+  *            @arg USART_IT_TC:   Transmission complete interrupt
 
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
 
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
 
+  *            @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
 
+  *            @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set  
+  *            @arg USART_IT_NE:   Noise Error interrupt
 
+  *            @arg USART_IT_FE:   Framing Error interrupt
 
+  *            @arg USART_IT_PE:   Parity Error interrupt
 
+  * @retval The new state of USART_IT (SET or RESET).
 
+  */
 
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
 
+{
 
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
 
+  ITStatus bitstatus = RESET;
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+
 
+  /* The CTS interrupt is not available for UART4 and UART5 */ 
+  if (USART_IT == USART_IT_CTS)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  } 
+    
+  /* Get the USART register index */
 
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
 
+  /* Get the interrupt position */
 
+  itmask = USART_IT & IT_MASK;
 
+  itmask = (uint32_t)0x01 << itmask;
 
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
 
+  {
 
+    itmask &= USARTx->CR1;
 
+  }
 
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
 
+  {
 
+    itmask &= USARTx->CR2;
 
+  }
 
+  else /* The IT  is in CR3 register */
 
+  {
 
+    itmask &= USARTx->CR3;
 
+  }
 
+  
+  bitpos = USART_IT >> 0x08;
 
+  bitpos = (uint32_t)0x01 << bitpos;
 
+  bitpos &= USARTx->SR;
 
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  
+  return bitstatus;  
+}
 
+
 
+/**
 
+  * @brief  Clears the USARTx's interrupt pending bits.
 
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
 
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
 
+  *          This parameter can be one of the following values:
 
+  *            @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
 
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
 
+  *            @arg USART_IT_TC:   Transmission complete interrupt. 
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt.
 
+  *
 
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) pending bits are cleared by 
+  *          software sequence: a read operation to USART_SR register 
+  *          (USART_GetITStatus()) followed by a read operation to USART_DR register 
+  *          (USART_ReceiveData()).
 
+  * @note   RXNE pending bit can be also cleared by a read to the USART_DR register 
+  *          (USART_ReceiveData()).
 
+  * @note   TC pending bit can be also cleared by software sequence: a read 
+  *          operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *          operation to USART_DR register (USART_SendData()).
 
+  * @note   TXE pending bit is cleared only by a write to the USART_DR register 
+  *          (USART_SendData()).
 
+  *  
+  * @retval None
 
+  */
 
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
 
+{
 
+  uint16_t bitpos = 0x00, itmask = 0x00;
 
+  /* Check the parameters */
 
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
 
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+
 
+  /* The CTS interrupt is not available for UART4 and UART5 */
 
+  if (USART_IT == USART_IT_CTS)
 
+  {
 
+    assert_param(IS_USART_1236_PERIPH(USARTx));
 
+  } 
+    
+  bitpos = USART_IT >> 0x08;
 
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
 
+  USARTx->SR = (uint16_t)~itmask;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 309 - 0
stm32/stm32f4xx_spl/src/stm32f4xx_wwdg.c
Ver arquivo 

@@ -0,0 +1,309 @@
 
+/**
 
+  ******************************************************************************
 
+  * @file    stm32f4xx_wwdg.c
 
+  * @author  MCD Application Team
 
+  * @version V1.0.2
 
+  * @date    05-March-2012
 
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:           
+  *           - Prescaler, Refresh window and Counter configuration
 
+  *           - WWDG activation
 
+  *           - Interrupts and flags management
 
+  *             
+  *  @verbatim
 
+  *    
+  *          ===================================================================
 
+  *                                     WWDG features
 
+  *          ===================================================================
 
+  *                                        
+  *          Once enabled the WWDG generates a system reset on expiry of a programmed
 
+  *          time period, unless the program refreshes the counter (downcounter) 
+  *          before to reach 0x3F value (i.e. a reset is generated when the counter
 
+  *          value rolls over from 0x40 to 0x3F). 
+  *          An MCU reset is also generated if the counter value is refreshed
 
+  *          before the counter has reached the refresh window value. This 
+  *          implies that the counter must be refreshed in a limited window.
 
+  *            
+  *          Once enabled the WWDG cannot be disabled except by a system reset.                          
+  *          
+  *          WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
 
+  *          reset occurs.
 
+  *            
+  *          The WWDG counter input clock is derived from the APB clock divided 
+  *          by a programmable prescaler.
 
+  *              
+  *          WWDG counter clock = PCLK1 / Prescaler
 
+  *          WWDG timeout = (WWDG counter clock) * (counter value)
 
+  *                      
+  *          Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
 
+  *                            
+  *          ===================================================================
 
+  *                                 How to use this driver
 
+  *          =================================================================== 
+  *          1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
 
+  *            
+  *          2. Configure the WWDG prescaler using WWDG_SetPrescaler() function
 
+  *                           
+  *          3. Configure the WWDG refresh window using WWDG_SetWindowValue() function
 
+  *            
+  *          4. Set the WWDG counter value and start it using WWDG_Enable() function.
 
+  *             When the WWDG is enabled the counter value should be configured to 
+  *             a value greater than 0x40 to prevent generating an immediate reset.     
+  *            
+  *          5. Optionally you can enable the Early wakeup interrupt which is 
+  *             generated when the counter reach 0x40.
 
+  *             Once enabled this interrupt cannot be disabled except by a system reset.
 
+  *                 
+  *          6. Then the application program must refresh the WWDG counter at regular
 
+  *             intervals during normal operation to prevent an MCU reset, using
 
+  *             WWDG_SetCounter() function. This operation must occur only when
 
+  *             the counter value is lower than the refresh window value, 
+  *             programmed using WWDG_SetWindowValue().         
+  *
 
+  *  @endverbatim  
+  *                             
+  ******************************************************************************
 
+  * @attention
 
+  *
 
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
 
+  *
 
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 
+  * You may not use this file except in compliance with the License.
 
+  * You may obtain a copy of the License at:
 
+  *
 
+  *        http://www.st.com/software_license_agreement_liberty_v2
 
+  *
 
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
+  * See the License for the specific language governing permissions and
 
+  * limitations under the License.
 
+  *
 
+  ******************************************************************************
 
+  */
 
+
 
+/* Includes ------------------------------------------------------------------*/
 
+#include "stm32f4xx_wwdg.h"
 
+#include "stm32f4xx_rcc.h"
 
+
 
+/** @addtogroup STM32F4xx_StdPeriph_Driver
 
+  * @{
 
+  */
 
+
 
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
 
+  * @{
 
+  */
 
+
 
+/* Private typedef -----------------------------------------------------------*/
 
+/* Private define ------------------------------------------------------------*/
 
+
 
+/* ----------- WWDG registers bit address in the alias region ----------- */
 
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
 
+/* Alias word address of EWI bit */
 
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
 
+#define EWI_BitNumber     0x09
 
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
 
+
 
+/* --------------------- WWDG registers bit mask ------------------------ */
 
+/* CFR register bit mask */
 
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
 
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
 
+#define BIT_MASK          ((uint8_t)0x7F)
 
+
 
+/* Private macro -------------------------------------------------------------*/
 
+/* Private variables ---------------------------------------------------------*/
 
+/* Private function prototypes -----------------------------------------------*/
 
+/* Private functions ---------------------------------------------------------*/
 
+
 
+/** @defgroup WWDG_Private_Functions
 
+  * @{
 
+  */
 
+
 
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
 
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+          Prescaler, Refresh window and Counter configuration functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void WWDG_DeInit(void)
 
+{
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
 
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
 
+}
 
+
 
+/**
 
+  * @brief  Sets the WWDG Prescaler.
 
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
 
+  *   This parameter can be one of the following values:
 
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
 
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
 
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
 
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
 
+  * @retval None
 
+  */
 
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
 
+{
 
+  uint32_t tmpreg = 0;
 
+  /* Check the parameters */
 
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
 
+  /* Clear WDGTB[1:0] bits */
 
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
 
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
 
+  tmpreg |= WWDG_Prescaler;
 
+  /* Store the new value */
 
+  WWDG->CFR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the WWDG window value.
 
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
 
+  *   This parameter value must be lower than 0x80.
 
+  * @retval None
 
+  */
 
+void WWDG_SetWindowValue(uint8_t WindowValue)
 
+{
 
+  __IO uint32_t tmpreg = 0;
 
+
 
+  /* Check the parameters */
 
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
 
+  /* Clear W[6:0] bits */
 
+
 
+  tmpreg = WWDG->CFR & CFR_W_MASK;
 
+
 
+  /* Set W[6:0] bits according to WindowValue value */
 
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
 
+
 
+  /* Store the new value */
 
+  WWDG->CFR = tmpreg;
 
+}
 
+
 
+/**
 
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
 
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void WWDG_EnableIT(void)
 
+{
 
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
 
+}
 
+
 
+/**
 
+  * @brief  Sets the WWDG counter value.
 
+  * @param  Counter: specifies the watchdog counter value.
 
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
 
+  *   an immediate reset) 
+  * @retval None
 
+  */
 
+void WWDG_SetCounter(uint8_t Counter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_WWDG_COUNTER(Counter));
 
+  /* Write to T[6:0] bits to configure the counter value, no need to do
 
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
 
+  WWDG->CR = Counter & BIT_MASK;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup WWDG_Group2 WWDG activation functions
 
+ *  @brief   WWDG activation functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                       WWDG activation function
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
 
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
 
+  *   an immediate reset)
 
+  * @retval None
 
+  */
 
+void WWDG_Enable(uint8_t Counter)
 
+{
 
+  /* Check the parameters */
 
+  assert_param(IS_WWDG_COUNTER(Counter));
 
+  WWDG->CR = WWDG_CR_WDGA | Counter;
 
+}
 
+/**
 
+  * @}
 
+  */
 
+
 
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
 
+ *  @brief   Interrupts and flags management functions 
+ *
 
+@verbatim   
+ ===============================================================================
 
+                 Interrupts and flags management functions
 
+ ===============================================================================  
+
 
+@endverbatim
 
+  * @{
 
+  */
 
+
 
+/**
 
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
 
+  * @param  None
 
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
 
+  */
 
+FlagStatus WWDG_GetFlagStatus(void)
 
+{
 
+  FlagStatus bitstatus = RESET;
 
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
 
+  {
 
+    bitstatus = SET;
 
+  }
 
+  else
 
+  {
 
+    bitstatus = RESET;
 
+  }
 
+  return bitstatus;
 
+}
 
+
 
+/**
 
+  * @brief  Clears Early Wakeup interrupt flag.
 
+  * @param  None
 
+  * @retval None
 
+  */
 
+void WWDG_ClearFlag(void)
 
+{
 
+  WWDG->SR = (uint32_t)RESET;
 
+}
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/**
 
+  * @}
 
+  */
 
+
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 53 - 0
stm32/system/core_cm4.c
Ver arquivo 

@@ -0,0 +1,53 @@
 
+/**************************************************************************//**

+ * @file     core_cm4.c

+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File

+ * @version  V2.01

+ * @date     06. December 2010

+ *

+ * @note

+ * Copyright (C) 2010 ARM Limited. All rights reserved.

+ *

+ * @par

+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 

+ * processor based microcontrollers.  This file can be freely distributed 

+ * within development tools that are supporting such ARM based processors. 

+ *

+ * @par

+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

+ *

+ ******************************************************************************/

+

+

+/* ###################  Compiler specific Intrinsics  ########################### */

+

+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/

+/* ARM armcc specific functions */

+

+

+

+

+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+

+

+

+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+

+

+

+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all instrinsics,

+ * Including the CMSIS ones.

+ */

+

+#endif

+ 1803 - 0
stm32/system/core_cm4.h
Ver arquivo 

@@ -0,0 +1,1803 @@
 
+/**************************************************************************//**

+ * @file     core_cm4.h

+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File

+ * @version  V4.00

+ * @date     22. August 2014

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2014 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CM4_H_GENERIC

+#define __CORE_CM4_H_GENERIC

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions

+  CMSIS violates the following MISRA-C:2004 rules:

+

+   \li Required Rule 8.5, object/function definition in header file.<br>

+     Function definitions in header files are used to allow 'inlining'.

+

+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>

+     Unions are used for effective representation of core registers.

+

+   \li Advisory Rule 19.7, Function-like macro defined.<br>

+     Function-like macros are used to allow more efficient code.

+ */

+

+

+/*******************************************************************************

+ *                 CMSIS definitions

+ ******************************************************************************/

+/** \ingroup Cortex_M4

+  @{

+ */

+

+/*  CMSIS CM4 definitions */

+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */

+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */

+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \

+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */

+

+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */

+

+

+#if   defined ( __CC_ARM )

+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */

+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */

+  #define __STATIC_INLINE  static __inline

+

+#elif defined ( __GNUC__ )

+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __ICCARM__ )

+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */

+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TMS470__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __TASKING__ )

+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */

+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#elif defined ( __CSMC__ )

+  #define __packed

+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */

+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */

+  #define __STATIC_INLINE  static inline

+

+#endif

+

+/** __FPU_USED indicates whether an FPU is used or not.

+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+*/

+#if defined ( __CC_ARM )

+  #if defined __TARGET_FPU_VFP

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __GNUC__ )

+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __ICCARM__ )

+  #if defined __ARMVFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TMS470__ )

+  #if defined __TI_VFP_SUPPORT__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __TASKING__ )

+  #if defined __FPU_VFP__

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+

+#elif defined ( __CSMC__ )		/* Cosmic */

+  #if ( __CSMC__ & 0x400)		// FPU present for parser

+    #if (__FPU_PRESENT == 1)

+      #define __FPU_USED       1

+    #else

+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"

+      #define __FPU_USED       0

+    #endif

+  #else

+    #define __FPU_USED         0

+  #endif

+#endif

+

+#include <stdint.h>                      /* standard types definitions                      */

+#include <core_cmInstr.h>                /* Core Instruction Access                         */

+#include <core_cmFunc.h>                 /* Core Function Access                            */

+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM4_H_GENERIC */

+

+#ifndef __CMSIS_GENERIC

+

+#ifndef __CORE_CM4_H_DEPENDANT

+#define __CORE_CM4_H_DEPENDANT

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* check device defines and use defaults */

+#if defined __CHECK_DEVICE_DEFINES

+  #ifndef __CM4_REV

+    #define __CM4_REV               0x0000

+    #warning "__CM4_REV not defined in device header file; using default!"

+  #endif

+

+  #ifndef __FPU_PRESENT

+    #define __FPU_PRESENT             0

+    #warning "__FPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __MPU_PRESENT

+    #define __MPU_PRESENT             0

+    #warning "__MPU_PRESENT not defined in device header file; using default!"

+  #endif

+

+  #ifndef __NVIC_PRIO_BITS

+    #define __NVIC_PRIO_BITS          4

+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"

+  #endif

+

+  #ifndef __Vendor_SysTickConfig

+    #define __Vendor_SysTickConfig    0

+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"

+  #endif

+#endif

+

+/* IO definitions (access restrictions to peripheral registers) */

+/**

+    \defgroup CMSIS_glob_defs CMSIS Global Defines

+

+    <strong>IO Type Qualifiers</strong> are used

+    \li to specify the access to peripheral variables.

+    \li for automatic generation of peripheral register debug information.

+*/

+#ifdef __cplusplus

+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */

+#else

+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */

+#endif

+#define     __O     volatile             /*!< Defines 'write only' permissions                */

+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */

+

+/*@} end of group Cortex_M4 */

+

+

+

+/*******************************************************************************

+ *                 Register Abstraction

+  Core Register contain:

+  - Core Register

+  - Core NVIC Register

+  - Core SCB Register

+  - Core SysTick Register

+  - Core Debug Register

+  - Core MPU Register

+  - Core FPU Register

+ ******************************************************************************/

+/** \defgroup CMSIS_core_register Defines and Type Definitions

+    \brief Type definitions and defines for Cortex-M processor based devices.

+*/

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_CORE  Status and Control Registers

+    \brief  Core Register type definitions.

+  @{

+ */

+

+/** \brief  Union type to access the Application Program Status Register (APSR).

+ */

+typedef union

+{

+  struct

+  {

+#if (__CORTEX_M != 0x04)

+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */

+#else

+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */

+#endif

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} APSR_Type;

+

+

+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} IPSR_Type;

+

+

+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */

+#if (__CORTEX_M != 0x04)

+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */

+#else

+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */

+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */

+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */

+#endif

+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */

+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */

+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */

+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */

+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */

+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */

+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} xPSR_Type;

+

+

+/** \brief  Union type to access the Control Registers (CONTROL).

+ */

+typedef union

+{

+  struct

+  {

+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */

+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */

+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */

+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */

+  } b;                                   /*!< Structure used for bit  access                  */

+  uint32_t w;                            /*!< Type      used for word access                  */

+} CONTROL_Type;

+

+/*@} end of group CMSIS_CORE */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)

+    \brief      Type definitions for the NVIC Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+ */

+typedef struct

+{

+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */

+       uint32_t RESERVED0[24];

+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */

+       uint32_t RSERVED1[24];

+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */

+       uint32_t RESERVED2[24];

+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */

+       uint32_t RESERVED3[24];

+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */

+       uint32_t RESERVED4[56];

+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

+       uint32_t RESERVED5[644];

+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */

+}  NVIC_Type;

+

+/* Software Triggered Interrupt Register Definitions */

+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */

+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */

+

+/*@} end of group CMSIS_NVIC */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCB     System Control Block (SCB)

+    \brief      Type definitions for the System Control Block Registers

+  @{

+ */

+

+/** \brief  Structure type to access the System Control Block (SCB).

+ */

+typedef struct

+{

+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */

+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */

+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */

+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */

+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */

+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */

+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */

+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */

+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */

+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */

+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */

+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */

+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */

+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */

+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */

+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */

+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */

+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */

+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */

+       uint32_t RESERVED0[5];

+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */

+} SCB_Type;

+

+/* SCB CPUID Register Definitions */

+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */

+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */

+

+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */

+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */

+

+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */

+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */

+

+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */

+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */

+

+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */

+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */

+

+/* SCB Interrupt Control State Register Definitions */

+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */

+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */

+

+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */

+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */

+

+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */

+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */

+

+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */

+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */

+

+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */

+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */

+

+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */

+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */

+

+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */

+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */

+

+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */

+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */

+

+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */

+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */

+

+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */

+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */

+

+/* SCB Vector Table Offset Register Definitions */

+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */

+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */

+

+/* SCB Application Interrupt and Reset Control Register Definitions */

+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */

+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */

+

+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */

+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */

+

+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */

+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */

+

+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */

+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */

+

+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */

+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */

+

+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */

+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */

+

+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */

+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */

+

+/* SCB System Control Register Definitions */

+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */

+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */

+

+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */

+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */

+

+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */

+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */

+

+/* SCB Configuration Control Register Definitions */

+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */

+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */

+

+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */

+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */

+

+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */

+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */

+

+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */

+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */

+

+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */

+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */

+

+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */

+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */

+

+/* SCB System Handler Control and State Register Definitions */

+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */

+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */

+

+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */

+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */

+

+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */

+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */

+

+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */

+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */

+

+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */

+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */

+

+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */

+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */

+

+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */

+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */

+

+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */

+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */

+

+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */

+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */

+

+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */

+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */

+

+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */

+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */

+

+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */

+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */

+

+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */

+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */

+

+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */

+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */

+

+/* SCB Configurable Fault Status Registers Definitions */

+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */

+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */

+

+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */

+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */

+

+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */

+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */

+

+/* SCB Hard Fault Status Registers Definitions */

+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */

+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */

+

+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */

+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */

+

+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */

+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */

+

+/* SCB Debug Fault Status Register Definitions */

+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */

+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */

+

+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */

+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */

+

+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */

+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */

+

+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */

+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */

+

+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */

+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */

+

+/*@} end of group CMSIS_SCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)

+    \brief      Type definitions for the System Control and ID Register not in the SCB

+  @{

+ */

+

+/** \brief  Structure type to access the System Control and ID Register not in the SCB.

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */

+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */

+} SCnSCB_Type;

+

+/* Interrupt Controller Type Register Definitions */

+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */

+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */

+

+/* Auxiliary Control Register Definitions */

+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */

+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */

+

+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */

+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */

+

+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */

+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */

+

+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */

+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */

+

+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */

+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */

+

+/*@} end of group CMSIS_SCnotSCB */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)

+    \brief      Type definitions for the System Timer Registers.

+  @{

+ */

+

+/** \brief  Structure type to access the System Timer (SysTick).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */

+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */

+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */

+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */

+} SysTick_Type;

+

+/* SysTick Control / Status Register Definitions */

+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */

+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */

+

+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */

+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */

+

+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */

+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */

+

+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */

+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */

+

+/* SysTick Reload Register Definitions */

+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */

+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */

+

+/* SysTick Current Register Definitions */

+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */

+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */

+

+/* SysTick Calibration Register Definitions */

+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */

+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */

+

+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */

+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */

+

+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */

+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */

+

+/*@} end of group CMSIS_SysTick */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)

+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)

+  @{

+ */

+

+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).

+ */

+typedef struct

+{

+  __O  union

+  {

+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */

+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */

+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */

+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */

+       uint32_t RESERVED0[864];

+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */

+       uint32_t RESERVED1[15];

+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */

+       uint32_t RESERVED2[15];

+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */

+       uint32_t RESERVED3[29];

+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */

+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */

+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */

+       uint32_t RESERVED4[43];

+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */

+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */

+       uint32_t RESERVED5[6];

+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */

+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */

+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */

+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */

+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */

+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */

+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */

+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */

+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */

+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */

+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */

+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */

+} ITM_Type;

+

+/* ITM Trace Privilege Register Definitions */

+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */

+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */

+

+/* ITM Trace Control Register Definitions */

+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */

+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */

+

+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */

+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */

+

+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */

+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */

+

+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */

+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */

+

+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */

+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */

+

+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */

+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */

+

+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */

+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */

+

+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */

+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */

+

+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */

+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */

+

+/* ITM Integration Write Register Definitions */

+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */

+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */

+

+/* ITM Integration Read Register Definitions */

+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */

+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */

+

+/* ITM Integration Mode Control Register Definitions */

+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */

+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */

+

+/* ITM Lock Status Register Definitions */

+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */

+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */

+

+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */

+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */

+

+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */

+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */

+

+/*@}*/ /* end of group CMSIS_ITM */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)

+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)

+  @{

+ */

+

+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).

+ */

+typedef struct

+{

+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */

+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */

+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */

+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */

+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */

+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */

+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */

+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */

+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */

+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */

+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */

+       uint32_t RESERVED0[1];

+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */

+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */

+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */

+       uint32_t RESERVED1[1];

+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */

+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */

+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */

+       uint32_t RESERVED2[1];

+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */

+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */

+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */

+} DWT_Type;

+

+/* DWT Control Register Definitions */

+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */

+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */

+

+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */

+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */

+

+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */

+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */

+

+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */

+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */

+

+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */

+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */

+

+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */

+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */

+

+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */

+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */

+

+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */

+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */

+

+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */

+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */

+

+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */

+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */

+

+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */

+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */

+

+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */

+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */

+

+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */

+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */

+

+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */

+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */

+

+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */

+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */

+

+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */

+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */

+

+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */

+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */

+

+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */

+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */

+

+/* DWT CPI Count Register Definitions */

+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */

+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */

+

+/* DWT Exception Overhead Count Register Definitions */

+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */

+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */

+

+/* DWT Sleep Count Register Definitions */

+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */

+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */

+

+/* DWT LSU Count Register Definitions */

+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */

+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */

+

+/* DWT Folded-instruction Count Register Definitions */

+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */

+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */

+

+/* DWT Comparator Mask Register Definitions */

+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */

+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */

+

+/* DWT Comparator Function Register Definitions */

+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */

+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */

+

+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */

+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */

+

+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */

+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */

+

+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */

+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */

+

+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */

+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */

+

+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */

+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */

+

+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */

+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */

+

+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */

+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */

+

+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */

+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */

+

+/*@}*/ /* end of group CMSIS_DWT */

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)

+    \brief      Type definitions for the Trace Port Interface (TPI)

+  @{

+ */

+

+/** \brief  Structure type to access the Trace Port Interface Register (TPI).

+ */

+typedef struct

+{

+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */

+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */

+       uint32_t RESERVED0[2];

+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */

+       uint32_t RESERVED1[55];

+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */

+       uint32_t RESERVED2[131];

+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */

+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */

+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */

+       uint32_t RESERVED3[759];

+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */

+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */

+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */

+       uint32_t RESERVED4[1];

+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */

+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */

+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */

+       uint32_t RESERVED5[39];

+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */

+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */

+       uint32_t RESERVED7[8];

+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */

+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */

+} TPI_Type;

+

+/* TPI Asynchronous Clock Prescaler Register Definitions */

+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */

+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */

+

+/* TPI Selected Pin Protocol Register Definitions */

+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */

+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */

+

+/* TPI Formatter and Flush Status Register Definitions */

+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */

+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */

+

+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */

+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */

+

+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */

+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */

+

+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */

+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */

+

+/* TPI Formatter and Flush Control Register Definitions */

+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */

+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */

+

+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */

+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */

+

+/* TPI TRIGGER Register Definitions */

+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */

+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */

+

+/* TPI Integration ETM Data Register Definitions (FIFO0) */

+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */

+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */

+

+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */

+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */

+

+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */

+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */

+

+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */

+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */

+

+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */

+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */

+

+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */

+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */

+

+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */

+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */

+

+/* TPI ITATBCTR2 Register Definitions */

+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */

+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */

+

+/* TPI Integration ITM Data Register Definitions (FIFO1) */

+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */

+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */

+

+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */

+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */

+

+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */

+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */

+

+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */

+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */

+

+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */

+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */

+

+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */

+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */

+

+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */

+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */

+

+/* TPI ITATBCTR0 Register Definitions */

+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */

+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */

+

+/* TPI Integration Mode Control Register Definitions */

+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */

+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */

+

+/* TPI DEVID Register Definitions */

+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */

+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */

+

+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */

+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */

+

+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */

+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */

+

+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */

+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */

+

+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */

+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */

+

+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */

+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */

+

+/* TPI DEVTYPE Register Definitions */

+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */

+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */

+

+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */

+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */

+

+/*@}*/ /* end of group CMSIS_TPI */

+

+

+#if (__MPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)

+    \brief      Type definitions for the Memory Protection Unit (MPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Memory Protection Unit (MPU).

+ */

+typedef struct

+{

+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */

+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */

+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */

+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */

+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */

+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */

+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */

+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */

+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */

+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */

+} MPU_Type;

+

+/* MPU Type Register */

+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */

+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */

+

+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */

+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */

+

+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */

+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */

+

+/* MPU Control Register */

+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */

+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */

+

+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */

+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */

+

+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */

+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */

+

+/* MPU Region Number Register */

+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */

+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */

+

+/* MPU Region Base Address Register */

+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */

+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */

+

+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */

+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */

+

+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */

+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */

+

+/* MPU Region Attribute and Size Register */

+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */

+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */

+

+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */

+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */

+

+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */

+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */

+

+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */

+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */

+

+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */

+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */

+

+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */

+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */

+

+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */

+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */

+

+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */

+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */

+

+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */

+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */

+

+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */

+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */

+

+/*@} end of group CMSIS_MPU */

+#endif

+

+

+#if (__FPU_PRESENT == 1)

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)

+    \brief      Type definitions for the Floating Point Unit (FPU)

+  @{

+ */

+

+/** \brief  Structure type to access the Floating Point Unit (FPU).

+ */

+typedef struct

+{

+       uint32_t RESERVED0[1];

+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */

+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */

+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */

+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */

+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */

+} FPU_Type;

+

+/* Floating-Point Context Control Register */

+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */

+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */

+

+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */

+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */

+

+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */

+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */

+

+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */

+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */

+

+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */

+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */

+

+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */

+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */

+

+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */

+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */

+

+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */

+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */

+

+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */

+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */

+

+/* Floating-Point Context Address Register */

+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */

+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */

+

+/* Floating-Point Default Status Control Register */

+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */

+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */

+

+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */

+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */

+

+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */

+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */

+

+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */

+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */

+

+/* Media and FP Feature Register 0 */

+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */

+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */

+

+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */

+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */

+

+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */

+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */

+

+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */

+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */

+

+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */

+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */

+

+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */

+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */

+

+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */

+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */

+

+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */

+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */

+

+/* Media and FP Feature Register 1 */

+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */

+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */

+

+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */

+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */

+

+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */

+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */

+

+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */

+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */

+

+/*@} end of group CMSIS_FPU */

+#endif

+

+

+/** \ingroup  CMSIS_core_register

+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)

+    \brief      Type definitions for the Core Debug Registers

+  @{

+ */

+

+/** \brief  Structure type to access the Core Debug Register (CoreDebug).

+ */

+typedef struct

+{

+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */

+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */

+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */

+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */

+} CoreDebug_Type;

+

+/* Debug Halting Control and Status Register */

+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */

+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */

+

+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */

+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */

+

+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */

+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */

+

+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */

+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */

+

+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */

+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */

+

+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */

+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */

+

+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */

+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */

+

+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */

+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */

+

+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */

+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */

+

+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */

+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */

+

+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */

+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */

+

+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */

+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */

+

+/* Debug Core Register Selector Register */

+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */

+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */

+

+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */

+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */

+

+/* Debug Exception and Monitor Control Register */

+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */

+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */

+

+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */

+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */

+

+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */

+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */

+

+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */

+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */

+

+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */

+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */

+

+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */

+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */

+

+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */

+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */

+

+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */

+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */

+

+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */

+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */

+

+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */

+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */

+

+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */

+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */

+

+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */

+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */

+

+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */

+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */

+

+/*@} end of group CMSIS_CoreDebug */

+

+

+/** \ingroup    CMSIS_core_register

+    \defgroup   CMSIS_core_base     Core Definitions

+    \brief      Definitions for base addresses, unions, and structures.

+  @{

+ */

+

+/* Memory mapping of Cortex-M4 Hardware */

+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */

+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */

+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */

+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */

+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */

+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */

+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */

+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */

+

+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */

+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */

+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */

+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */

+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */

+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */

+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */

+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */

+

+#if (__MPU_PRESENT == 1)

+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */

+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */

+#endif

+

+#if (__FPU_PRESENT == 1)

+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */

+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */

+#endif

+

+/*@} */

+

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+  Core Function Interface contains:

+  - Core NVIC Functions

+  - Core SysTick Functions

+  - Core Debug Functions

+  - Core Register Access Functions

+ ******************************************************************************/

+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference

+*/

+

+

+

+/* ##########################   NVIC functions  #################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions

+    \brief      Functions that manage interrupts and exceptions via the NVIC.

+    @{

+ */

+

+/** \brief  Set Priority Grouping

+

+  The function sets the priority grouping field using the required unlock sequence.

+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.

+  Only values from 0..7 are used.

+  In case of a conflict between priority grouping and available

+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]      PriorityGroup  Priority grouping field.

+ */

+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)

+{

+  uint32_t reg_value;

+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

+

+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */

+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */

+  reg_value  =  (reg_value                                 |

+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |

+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */

+  SCB->AIRCR =  reg_value;

+}

+

+

+/** \brief  Get Priority Grouping

+

+  The function reads the priority grouping field from the NVIC Interrupt Controller.

+

+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)

+{

+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */

+}

+

+

+/** \brief  Enable External Interrupt

+

+    The function enables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)

+{

+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */

+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */

+}

+

+

+/** \brief  Disable External Interrupt

+

+    The function disables a device-specific interrupt in the NVIC interrupt controller.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */

+}

+

+

+/** \brief  Get Pending Interrupt

+

+    The function reads the pending register in the NVIC and returns the pending bit

+    for the specified interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not pending.

+    \return             1  Interrupt status is pending.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)

+{

+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */

+}

+

+

+/** \brief  Set Pending Interrupt

+

+    The function sets the pending bit of an external interrupt.

+

+    \param [in]      IRQn  Interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */

+}

+

+

+/** \brief  Clear Pending Interrupt

+

+    The function clears the pending bit of an external interrupt.

+

+    \param [in]      IRQn  External interrupt number. Value cannot be negative.

+ */

+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)

+{

+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */

+}

+

+

+/** \brief  Get Active Interrupt

+

+    The function reads the active register in NVIC and returns the active bit.

+

+    \param [in]      IRQn  Interrupt number.

+

+    \return             0  Interrupt status is not active.

+    \return             1  Interrupt status is active.

+ */

+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)

+{

+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */

+}

+

+

+/** \brief  Set Interrupt Priority

+

+    The function sets the priority of an interrupt.

+

+    \note The priority cannot be set for every core interrupt.

+

+    \param [in]      IRQn  Interrupt number.

+    \param [in]  priority  Priority to set.

+ */

+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

+{

+  if(IRQn < 0) {

+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */

+  else {

+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */

+}

+

+

+/** \brief  Get Interrupt Priority

+

+    The function reads the priority of an interrupt. The interrupt

+    number can be positive to specify an external (device specific)

+    interrupt, or negative to specify an internal (core) interrupt.

+

+

+    \param [in]   IRQn  Interrupt number.

+    \return             Interrupt Priority. Value is aligned automatically to the implemented

+                        priority bits of the microcontroller.

+ */

+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)

+{

+

+  if(IRQn < 0) {

+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */

+  else {

+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */

+}

+

+

+/** \brief  Encode Priority

+

+    The function encodes the priority for an interrupt with the given priority group,

+    preemptive priority value, and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+

+    \param [in]     PriorityGroup  Used priority group.

+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).

+    \param [in]       SubPriority  Subpriority value (starting from 0).

+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().

+ */

+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+

+  return (

+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |

+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))

+         );

+}

+

+

+/** \brief  Decode Priority

+

+    The function decodes an interrupt priority value with a given priority group to

+    preemptive priority value and subpriority value.

+    In case of a conflict between priority grouping and available

+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+

+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().

+    \param [in]     PriorityGroup  Used priority group.

+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).

+    \param [out]     pSubPriority  Subpriority value (starting from 0).

+ */

+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)

+{

+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */

+  uint32_t PreemptPriorityBits;

+  uint32_t SubPriorityBits;

+

+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;

+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

+

+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);

+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);

+}

+

+

+/** \brief  System Reset

+

+    The function initiates a system reset request to reset the MCU.

+ */

+__STATIC_INLINE void NVIC_SystemReset(void)

+//static inline void NVIC_SystemReset(void)

+{

+  __DSB();                                                     /* Ensure all outstanding memory accesses included

+                                                                  buffered write are completed before reset */

+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |

+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |

+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */

+  __DSB();                                                     /* Ensure completion of memory access */

+  while(1);                                                    /* wait until reset */

+}

+

+/*@} end of CMSIS_Core_NVICFunctions */

+

+

+

+/* ##################################    SysTick function  ############################################ */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions

+    \brief      Functions that configure the System.

+  @{

+ */

+

+#if (__Vendor_SysTickConfig == 0)

+

+/** \brief  System Tick Configuration

+

+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.

+    Counter is in free running mode to generate periodic interrupts.

+

+    \param [in]  ticks  Number of ticks between two interrupts.

+

+    \return          0  Function succeeded.

+    \return          1  Function failed.

+

+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the

+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>

+    must contain a vendor-specific implementation of this function.

+

+ */

+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)

+{

+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */

+

+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */

+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */

+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_TICKINT_Msk   |

+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */

+  return (0);                                                  /* Function successful */

+}

+

+#endif

+

+/*@} end of CMSIS_Core_SysTickFunctions */

+

+

+

+/* ##################################### Debug In/Output function ########################################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_core_DebugFunctions ITM Functions

+    \brief   Functions that access the ITM debug interface.

+  @{

+ */

+

+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */

+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */

+

+

+/** \brief  ITM Send Character

+

+    The function transmits a character via the ITM channel 0, and

+    \li Just returns when no debugger is connected that has booked the output.

+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

+

+    \param [in]     ch  Character to transmit.

+

+    \returns            Character to transmit.

+ */

+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)

+{

+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */

+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */

+  {

+    while (ITM->PORT[0].u32 == 0);

+    ITM->PORT[0].u8 = (uint8_t) ch;

+  }

+  return (ch);

+}

+

+

+/** \brief  ITM Receive Character

+

+    The function inputs a character via the external variable \ref ITM_RxBuffer.

+

+    \return             Received character.

+    \return         -1  No character pending.

+ */

+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {

+  int32_t ch = -1;                           /* no character available */

+

+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {

+    ch = ITM_RxBuffer;

+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */

+  }

+

+  return (ch);

+}

+

+

+/** \brief  ITM Check Character

+

+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.

+

+    \return          0  No character available.

+    \return          1  Character available.

+ */

+__STATIC_INLINE int32_t ITM_CheckChar (void) {

+

+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {

+    return (0);                                 /* no character available */

+  } else {

+    return (1);                                 /*    character available */

+  }

+}

+

+/*@} end of CMSIS_core_DebugFunctions */

+

+

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CM4_H_DEPENDANT */

+

+#endif /* __CMSIS_GENERIC */

+ 640 - 0
stm32/system/core_cmFunc.h
Ver arquivo 

@@ -0,0 +1,640 @@
 
+/**************************************************************************//**

+ * @file     core_cmFunc.h

+ * @brief    CMSIS Cortex-M Core Function Access Header File

+ * @version  V4.00

+ * @date     28. August 2014

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2014 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifndef __CORE_CMFUNC_H

+#define __CORE_CMFUNC_H

+

+

+/* ###########################  Core Function Access  ########################### */

+/** \ingroup  CMSIS_Core_FunctionInterface

+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions

+  @{

+ */

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+#if (__ARMCC_VERSION < 400677)

+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

+#endif

+

+/* intrinsic void __enable_irq();     */

+/* intrinsic void __disable_irq();    */

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+__STATIC_INLINE uint32_t __get_CONTROL(void)

+{

+  register uint32_t __regControl         __ASM("control");

+  return(__regControl);

+}

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+__STATIC_INLINE void __set_CONTROL(uint32_t control)

+{

+  register uint32_t __regControl         __ASM("control");

+  __regControl = control;

+}

+

+

+/** \brief  Get IPSR Register

+

+    This function returns the content of the IPSR Register.

+

+    \return               IPSR Register value

+ */

+__STATIC_INLINE uint32_t __get_IPSR(void)

+{

+  register uint32_t __regIPSR          __ASM("ipsr");

+  return(__regIPSR);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__STATIC_INLINE uint32_t __get_APSR(void)

+{

+  register uint32_t __regAPSR          __ASM("apsr");

+  return(__regAPSR);

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+__STATIC_INLINE uint32_t __get_xPSR(void)

+{

+  register uint32_t __regXPSR          __ASM("xpsr");

+  return(__regXPSR);

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+__STATIC_INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  return(__regProcessStackPointer);

+}

+

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  register uint32_t __regProcessStackPointer  __ASM("psp");

+  __regProcessStackPointer = topOfProcStack;

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+__STATIC_INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  return(__regMainStackPointer);

+}

+

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  register uint32_t __regMainStackPointer     __ASM("msp");

+  __regMainStackPointer = topOfMainStack;

+}

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+__STATIC_INLINE uint32_t __get_PRIMASK(void)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  return(__regPriMask);

+}

+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  register uint32_t __regPriMask         __ASM("primask");

+  __regPriMask = (priMask);

+}

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __enable_fault_irq                __enable_fiq

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+#define __disable_fault_irq               __disable_fiq

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+__STATIC_INLINE uint32_t  __get_BASEPRI(void)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  return(__regBasePri);

+}

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)

+{

+  register uint32_t __regBasePri         __ASM("basepri");

+  __regBasePri = (basePri & 0xff);

+}

+

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+__STATIC_INLINE uint32_t __get_FAULTMASK(void)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  return(__regFaultMask);

+}

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  register uint32_t __regFaultMask       __ASM("faultmask");

+  __regFaultMask = (faultMask & (uint32_t)1);

+}

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  return(__regfpscr);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  register uint32_t __regfpscr         __ASM("fpscr");

+  __regfpscr = (fpscr);

+#endif

+}

+

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/** \brief  Enable IRQ Interrupts

+

+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)

+{

+  __ASM volatile ("cpsie i" : : : "memory");

+}

+

+

+/** \brief  Disable IRQ Interrupts

+

+  This function disables IRQ interrupts by setting the I-bit in the CPSR.

+  Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)

+{

+  __ASM volatile ("cpsid i" : : : "memory");

+}

+

+

+/** \brief  Get Control Register

+

+    This function returns the content of the Control Register.

+

+    \return               Control Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, control" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Control Register

+

+    This function writes the given value to the Control Register.

+

+    \param [in]    control  Control Register value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)

+{

+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");

+}

+

+

+/** \brief  Get IPSR Register

+

+    This function returns the content of the IPSR Register.

+

+    \return               IPSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get APSR Register

+

+    This function returns the content of the APSR Register.

+

+    \return               APSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get xPSR Register

+

+    This function returns the content of the xPSR Register.

+

+    \return               xPSR Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Get Process Stack Pointer

+

+    This function returns the current value of the Process Stack Pointer (PSP).

+

+    \return               PSP Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Process Stack Pointer

+

+    This function assigns the given value to the Process Stack Pointer (PSP).

+

+    \param [in]    topOfProcStack  Process Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)

+{

+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");

+}

+

+

+/** \brief  Get Main Stack Pointer

+

+    This function returns the current value of the Main Stack Pointer (MSP).

+

+    \return               MSP Register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)

+{

+  register uint32_t result;

+

+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Main Stack Pointer

+

+    This function assigns the given value to the Main Stack Pointer (MSP).

+

+    \param [in]    topOfMainStack  Main Stack Pointer value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)

+{

+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");

+}

+

+

+/** \brief  Get Priority Mask

+

+    This function returns the current state of the priority mask bit from the Priority Mask Register.

+

+    \return               Priority Mask value

+ */

+/*__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, primask" : "=r" (result) );

+  return(result);

+}

+*/
 
+

+

+/** \brief  Set Priority Mask

+

+    This function assigns the given value to the Priority Mask Register.

+

+    \param [in]    priMask  Priority Mask

+ */

+/*
 
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)

+{

+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");

+}

+*/
 
+

+#if       (__CORTEX_M >= 0x03)

+

+/** \brief  Enable FIQ

+

+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)

+{

+  __ASM volatile ("cpsie f" : : : "memory");

+}

+

+

+/** \brief  Disable FIQ

+

+    This function disables FIQ interrupts by setting the F-bit in the CPSR.

+    Can only be executed in Privileged modes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)

+{

+  __ASM volatile ("cpsid f" : : : "memory");

+}

+

+

+/** \brief  Get Base Priority

+

+    This function returns the current value of the Base Priority register.

+

+    \return               Base Priority register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Base Priority

+

+    This function assigns the given value to the Base Priority register.

+

+    \param [in]    basePri  Base Priority value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)

+{

+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");

+}

+

+

+/** \brief  Get Fault Mask

+

+    This function returns the current value of the Fault Mask register.

+

+    \return               Fault Mask register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)

+{

+  uint32_t result;

+

+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );

+  return(result);

+}

+

+

+/** \brief  Set Fault Mask

+

+    This function assigns the given value to the Fault Mask register.

+

+    \param [in]    faultMask  Fault Mask value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)

+{

+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");

+}

+

+#endif /* (__CORTEX_M >= 0x03) */

+

+

+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)

+

+/** \brief  Get FPSCR

+

+    This function returns the current value of the Floating Point Status/Control register.

+

+    \return               Floating Point Status/Control register value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  uint32_t result;

+

+  /* Empty asm statement works as a scheduling barrier */

+  __ASM volatile ("");

+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );

+  __ASM volatile ("");

+  return(result);

+#else

+   return(0);

+#endif

+}

+

+

+/** \brief  Set FPSCR

+

+    This function assigns the given value to the Floating Point Status/Control register.

+

+    \param [in]    fpscr  Floating Point Status/Control value to set

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)

+{

+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+  /* Empty asm statement works as a scheduling barrier */

+  __ASM volatile ("");

+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");

+  __ASM volatile ("");

+#endif

+  (void)fpscr;

+}

+

+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all intrinsics,

+ * Including the CMSIS ones.

+ */

+

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

+#endif

+

+/*@} end of CMSIS_Core_RegAccFunctions */

+

+#endif /* __CORE_CMFUNC_H */

+ 886 - 0
stm32/system/core_cmInstr.h
Ver arquivo 

@@ -0,0 +1,886 @@
 
+/**************************************************************************//**

+ * @file     core_cmInstr.h

+ * @brief    CMSIS Cortex-M Core Instruction Access Header File

+ * @version  V4.00

+ * @date     28. August 2014

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2014 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#ifndef __CORE_CMINSTR_H

+#define __CORE_CMINSTR_H

+

+

+/* ##########################  Core Instruction Access  ######################### */

+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface

+  Access to dedicated instructions

+  @{

+*/

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+

+#if (__ARMCC_VERSION < 400677)

+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"

+#endif

+

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+#define __NOP                             __nop

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+#define __WFI                             __wfi

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+#define __WFE                             __wfe

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+#define __SEV                             __sev

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor,

+    so that all instructions following the ISB are fetched from cache or

+    memory, after the instruction has been completed.

+ */

+#define __ISB()                           __isb(0xF)

+

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier.

+    It completes when all explicit memory accesses before this instruction complete.

+ */

+#define __DSB()                           __dsb(0xF)

+

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before

+    and after the instruction, without ensuring their completion.

+ */

+#define __DMB()                           __dmb(0xF)

+

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#define __REV                             __rev

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)

+{

+  rev16 r0, r0

+  bx lr

+}

+#endif

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)

+{

+  revsh r0, r0

+  bx lr

+}

+#endif

+

+

+/** \brief  Rotate Right in unsigned value (32 bit)

+

+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+

+    \param [in]    value  Value to rotate

+    \param [in]    value  Number of Bits to rotate

+    \return               Rotated value

+ */

+#define __ROR                             __ror

+

+

+/** \brief  Breakpoint

+

+    This function causes the processor to enter Debug state.

+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+

+    \param [in]    value  is ignored by the processor.

+                   If required, a debugger can use it to store additional information about the breakpoint.

+ */

+#define __BKPT(value)                       __breakpoint(value)

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+#define __RBIT                            __rbit

+

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function executes a exclusive LDR instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function executes a exclusive LDR instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function executes a exclusive LDR instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function executes a exclusive STR instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXB(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function executes a exclusive STR instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXH(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function executes a exclusive STR instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+#define __STREXW(value, ptr)              __strex(value, ptr)

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+#define __CLREX                           __clrex

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT                            __ssat

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT                            __usat

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+#define __CLZ                             __clz

+

+

+/** \brief  Rotate Right with Extend (32 bit)

+

+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

+

+    \param [in]    value  Value to rotate

+    \return               Rotated value

+ */

+#ifndef __NO_EMBEDDED_ASM

+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)

+{

+  rrx r0, r0

+  bx lr

+}

+#endif

+

+

+/** \brief  LDRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))

+

+

+/** \brief  LDRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))

+

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRBT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRHT(value, ptr)               __strt(value, ptr)

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+#define __STRT(value, ptr)                __strt(value, ptr)

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+

+/* Define macros for porting to both thumb1 and thumb2.

+ * For thumb1, use low register (r0-r7), specified by constrant "l"

+ * Otherwise, use general registers, specified by constrant "r" */

+#if defined (__thumb__) && !defined (__thumb2__)

+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)

+#define __CMSIS_GCC_USE_REG(r) "l" (r)

+#else

+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)

+#define __CMSIS_GCC_USE_REG(r) "r" (r)

+#endif

+

+/** \brief  No Operation

+

+    No Operation does nothing. This instruction can be used for code alignment purposes.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)

+{

+  __ASM volatile ("nop");

+}

+

+

+/** \brief  Wait For Interrupt

+

+    Wait For Interrupt is a hint instruction that suspends execution

+    until one of a number of events occurs.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)

+{

+  __ASM volatile ("wfi");

+}

+

+

+/** \brief  Wait For Event

+

+    Wait For Event is a hint instruction that permits the processor to enter

+    a low-power state until one of a number of events occurs.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)

+{

+  __ASM volatile ("wfe");

+}

+

+

+/** \brief  Send Event

+

+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)

+{

+  __ASM volatile ("sev");

+}

+

+

+/** \brief  Instruction Synchronization Barrier

+

+    Instruction Synchronization Barrier flushes the pipeline in the processor,

+    so that all instructions following the ISB are fetched from cache or

+    memory, after the instruction has been completed.

+ */

+
 
+/*__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)

+{

+  __ASM volatile ("isb");

+}
 
+*/

+

+

+/** \brief  Data Synchronization Barrier

+

+    This function acts as a special kind of Data Memory Barrier.

+    It completes when all explicit memory accesses before this instruction complete.

+ */
 
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)

+{

+  __ASM volatile ("dsb");

+}

+
 
+

+

+/** \brief  Data Memory Barrier

+

+    This function ensures the apparent order of the explicit memory operations before

+    and after the instruction, without ensuring their completion.

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)

+{

+  __ASM volatile ("dmb");

+}

+

+

+/** \brief  Reverse byte order (32 bit)

+

+    This function reverses the byte order in integer value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)

+  return __builtin_bswap32(value);

+#else

+  uint32_t result;

+

+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+#endif

+}

+

+

+/** \brief  Reverse byte order (16 bit)

+

+    This function reverses the byte order in two unsigned short values.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+}

+

+

+/** \brief  Reverse byte order in signed short value

+

+    This function reverses the byte order in a signed short value with sign extension to integer.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)

+{

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+  return (short)__builtin_bswap16(value);

+#else

+  uint32_t result;

+

+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+#endif

+}

+

+

+/** \brief  Rotate Right in unsigned value (32 bit)

+

+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+

+    \param [in]    value  Value to rotate

+    \param [in]    value  Number of Bits to rotate

+    \return               Rotated value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

+{

+  return (op1 >> op2) | (op1 << (32 - op2)); 

+}

+

+

+/** \brief  Breakpoint

+

+    This function causes the processor to enter Debug state.

+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+

+    \param [in]    value  is ignored by the processor.

+                   If required, a debugger can use it to store additional information about the breakpoint.

+ */

+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)

+

+

+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)

+

+/** \brief  Reverse bit order of value

+

+    This function reverses the bit order of the given value.

+

+    \param [in]    value  Value to reverse

+    \return               Reversed value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)

+{

+  uint32_t result;

+

+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );

+   return(result);

+}

+

+

+/** \brief  LDR Exclusive (8 bit)

+

+    This function executes a exclusive LDR instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDR Exclusive (16 bit)

+

+    This function executes a exclusive LDR instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDR Exclusive (32 bit)

+

+    This function executes a exclusive LDR instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (8 bit)

+

+    This function executes a exclusive STR instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (16 bit)

+

+    This function executes a exclusive STR instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );

+   return(result);

+}

+

+

+/** \brief  STR Exclusive (32 bit)

+

+    This function executes a exclusive STR instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+    \return          0  Function succeeded

+    \return          1  Function failed

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)

+{

+   uint32_t result;

+

+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );

+   return(result);

+}

+

+

+/** \brief  Remove the exclusive lock

+

+    This function removes the exclusive lock which is created by LDREX.

+

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)

+{

+  __ASM volatile ("clrex" ::: "memory");

+}

+

+

+/** \brief  Signed Saturate

+

+    This function saturates a signed value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (1..32)

+    \return             Saturated value

+ */

+#define __SSAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Unsigned Saturate

+

+    This function saturates an unsigned value.

+

+    \param [in]  value  Value to be saturated

+    \param [in]    sat  Bit position to saturate to (0..31)

+    \return             Saturated value

+ */

+#define __USAT(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+

+/** \brief  Count leading zeros

+

+    This function counts the number of leading zeros of a data value.

+

+    \param [in]  value  Value to count the leading zeros

+    \return             number of leading zeros in value

+ */

+/*
 
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );

+   return ((uint8_t) result);    //Add explicit type cast here

+}

+
 
+*/
 
+

+

+/** \brief  Rotate Right with Extend (32 bit)

+

+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

+

+    \param [in]    value  Value to rotate

+    \return               Rotated value

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)

+{

+  uint32_t result;

+

+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );

+  return(result);

+}

+

+

+/** \brief  LDRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged LDRT instruction for 8 bit value.

+

+    \param [in]    ptr  Pointer to data

+    \return             value of type uint8_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint8_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged LDRT instruction for 16 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint16_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)

+{

+    uint32_t result;

+

+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)

+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );

+#else

+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not

+       accepted by assembler. So has to use following less efficient pattern.

+    */

+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );

+#endif

+   return ((uint16_t) result);    /* Add explicit type cast here */

+}

+

+

+/** \brief  LDRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged LDRT instruction for 32 bit values.

+

+    \param [in]    ptr  Pointer to data

+    \return        value of type uint32_t at (*ptr)

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)

+{

+    uint32_t result;

+

+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );

+   return(result);

+}

+

+

+/** \brief  STRT Unprivileged (8 bit)

+

+    This function executes a Unprivileged STRT instruction for 8 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)

+{

+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (16 bit)

+

+    This function executes a Unprivileged STRT instruction for 16 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)

+{

+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );

+}

+

+

+/** \brief  STRT Unprivileged (32 bit)

+

+    This function executes a Unprivileged STRT instruction for 32 bit values.

+

+    \param [in]  value  Value to store

+    \param [in]    ptr  Pointer to location

+ */

+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)

+{

+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );

+}

+

+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+/*

+ * The CMSIS functions have been implemented as intrinsics in the compiler.

+ * Please use "carm -?i" to get an up to date list of all intrinsics,

+ * Including the CMSIS ones.

+ */

+

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

+#endif

+

+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */

+

+#endif /* __CORE_CMINSTR_H */

+ 697 - 0
stm32/system/core_cmSimd.h
Ver arquivo 

@@ -0,0 +1,697 @@
 
+/**************************************************************************//**

+ * @file     core_cmSimd.h

+ * @brief    CMSIS Cortex-M SIMD Header File

+ * @version  V4.00

+ * @date     22. August 2014

+ *

+ * @note

+ *

+ ******************************************************************************/

+/* Copyright (c) 2009 - 2014 ARM LIMITED

+

+   All rights reserved.

+   Redistribution and use in source and binary forms, with or without

+   modification, are permitted provided that the following conditions are met:

+   - Redistributions of source code must retain the above copyright

+     notice, this list of conditions and the following disclaimer.

+   - Redistributions in binary form must reproduce the above copyright

+     notice, this list of conditions and the following disclaimer in the

+     documentation and/or other materials provided with the distribution.

+   - Neither the name of ARM nor the names of its contributors may be used

+     to endorse or promote products derived from this software without

+     specific prior written permission.

+   *

+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE

+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+   POSSIBILITY OF SUCH DAMAGE.

+   ---------------------------------------------------------------------------*/

+

+

+#if defined ( __ICCARM__ )

+ #pragma system_include  /* treat file as system include file for MISRA check */

+#endif

+

+#ifndef __CORE_CMSIMD_H

+#define __CORE_CMSIMD_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+

+/*******************************************************************************

+ *                Hardware Abstraction Layer

+ ******************************************************************************/

+

+

+/* ###################  Compiler specific Intrinsics  ########################### */

+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

+  Access to dedicated SIMD instructions

+  @{

+*/

+

+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

+/* ARM armcc specific functions */

+#define __SADD8                           __sadd8

+#define __QADD8                           __qadd8

+#define __SHADD8                          __shadd8

+#define __UADD8                           __uadd8

+#define __UQADD8                          __uqadd8

+#define __UHADD8                          __uhadd8

+#define __SSUB8                           __ssub8

+#define __QSUB8                           __qsub8

+#define __SHSUB8                          __shsub8

+#define __USUB8                           __usub8

+#define __UQSUB8                          __uqsub8

+#define __UHSUB8                          __uhsub8

+#define __SADD16                          __sadd16

+#define __QADD16                          __qadd16

+#define __SHADD16                         __shadd16

+#define __UADD16                          __uadd16

+#define __UQADD16                         __uqadd16

+#define __UHADD16                         __uhadd16

+#define __SSUB16                          __ssub16

+#define __QSUB16                          __qsub16

+#define __SHSUB16                         __shsub16

+#define __USUB16                          __usub16

+#define __UQSUB16                         __uqsub16

+#define __UHSUB16                         __uhsub16

+#define __SASX                            __sasx

+#define __QASX                            __qasx

+#define __SHASX                           __shasx

+#define __UASX                            __uasx

+#define __UQASX                           __uqasx

+#define __UHASX                           __uhasx

+#define __SSAX                            __ssax

+#define __QSAX                            __qsax

+#define __SHSAX                           __shsax

+#define __USAX                            __usax

+#define __UQSAX                           __uqsax

+#define __UHSAX                           __uhsax

+#define __USAD8                           __usad8

+#define __USADA8                          __usada8

+#define __SSAT16                          __ssat16

+#define __USAT16                          __usat16

+#define __UXTB16                          __uxtb16

+#define __UXTAB16                         __uxtab16

+#define __SXTB16                          __sxtb16

+#define __SXTAB16                         __sxtab16

+#define __SMUAD                           __smuad

+#define __SMUADX                          __smuadx

+#define __SMLAD                           __smlad

+#define __SMLADX                          __smladx

+#define __SMLALD                          __smlald

+#define __SMLALDX                         __smlaldx

+#define __SMUSD                           __smusd

+#define __SMUSDX                          __smusdx

+#define __SMLSD                           __smlsd

+#define __SMLSDX                          __smlsdx

+#define __SMLSLD                          __smlsld

+#define __SMLSLDX                         __smlsldx

+#define __SEL                             __sel

+#define __QADD                            __qadd

+#define __QSUB                            __qsub

+

+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

+

+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

+

+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \

+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))

+

+

+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

+/* GNU gcc specific functions */

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+#define __SSAT16(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+#define __USAT16(ARG1,ARG2) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1); \

+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

+  __RES; \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

+{

+  uint32_t result;

+

+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)

+{

+  union llreg_u{

+    uint32_t w32[2];

+    uint64_t w64;

+  } llr;

+  llr.w64 = acc;

+

+#ifndef __ARMEB__   // Little endian

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );

+#else               // Big endian

+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );

+#endif

+

+  return(llr.w64);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)

+{

+  uint32_t result;

+

+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

+  return(result);

+}

+

+#define __PKHBT(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+

+#define __PKHTB(ARG1,ARG2,ARG3) \

+({                          \

+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

+  if (ARG3 == 0) \

+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

+  else \

+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

+  __RES; \

+ })

+

+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)

+{

+ int32_t result;

+

+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );

+ return(result);

+}

+

+

+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

+/* IAR iccarm specific functions */

+#include <cmsis_iar.h>

+

+

+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

+/* TI CCS specific functions */

+#include <cmsis_ccs.h>

+

+

+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

+/* TASKING carm specific functions */

+/* not yet supported */

+

+

+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/

+/* Cosmic specific functions */

+#include <cmsis_csm.h>

+

+#endif

+

+/*@} end of group CMSIS_SIMD_intrinsics */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __CORE_CMSIMD_H */

+ 134 - 0
stm32/system/stm32f4xx_conf.h
Ver arquivo 

@@ -0,0 +1,134 @@
 
+/**

+  ******************************************************************************

+  * @file    Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h  

+  * @author  MCD Application Team

+  * @version V1.5.0

+  * @date    06-March-2015

+  * @brief   Library configuration file.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>

+  *

+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");

+  * You may not use this file except in compliance with the License.

+  * You may obtain a copy of the License at:

+  *

+  *        http://www.st.com/software_license_agreement_liberty_v2

+  *

+  * Unless required by applicable law or agreed to in writing, software 

+  * distributed under the License is distributed on an "AS IS" BASIS, 

+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+  * See the License for the specific language governing permissions and

+  * limitations under the License.

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32F4xx_CONF_H

+#define __STM32F4xx_CONF_H

+

+/* Includes ------------------------------------------------------------------*/

+/* Uncomment the line below to enable peripheral header file inclusion */

+#include "stm32f4xx_adc.h"

+#include "stm32f4xx_crc.h"

+#include "stm32f4xx_dbgmcu.h"

+#include "stm32f4xx_dma.h"

+#include "stm32f4xx_exti.h"

+#include "stm32f4xx_flash.h"

+#include "stm32f4xx_gpio.h"

+#include "stm32f4xx_i2c.h"

+#include "stm32f4xx_iwdg.h"

+#include "stm32f4xx_pwr.h"

+#include "stm32f4xx_rcc.h"

+#include "stm32f4xx_rtc.h"

+#include "stm32f4xx_sdio.h"

+#include "stm32f4xx_spi.h"

+#include "stm32f4xx_syscfg.h"

+#include "stm32f4xx_tim.h"

+#include "stm32f4xx_usart.h"

+#include "stm32f4xx_wwdg.h"

+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */

+

+#if defined (STM32F429_439xx) || defined(STM32F446xx)

+#include "stm32f4xx_cryp.h"

+#include "stm32f4xx_hash.h"

+#include "stm32f4xx_rng.h"

+#include "stm32f4xx_can.h"

+#include "stm32f4xx_dac.h"

+#include "stm32f4xx_dcmi.h"

+#include "stm32f4xx_dma2d.h"

+#include "stm32f4xx_fmc.h"

+#include "stm32f4xx_ltdc.h"

+#include "stm32f4xx_sai.h"

+#endif /* STM32F429_439xx || STM32F446xx */

+

+#if defined (STM32F427_437xx)

+#include "stm32f4xx_cryp.h"

+#include "stm32f4xx_hash.h"

+#include "stm32f4xx_rng.h"

+#include "stm32f4xx_can.h"

+#include "stm32f4xx_dac.h"

+#include "stm32f4xx_dcmi.h"

+#include "stm32f4xx_dma2d.h"

+#include "stm32f4xx_fmc.h"

+#include "stm32f4xx_sai.h"

+#endif /* STM32F427_437xx */

+

+#if defined (STM32F40_41xxx)

+#include "stm32f4xx_cryp.h"

+#include "stm32f4xx_hash.h"

+#include "stm32f4xx_rng.h"

+#include "stm32f4xx_can.h"

+#include "stm32f4xx_dac.h"

+#include "stm32f4xx_dcmi.h"

+#include "stm32f4xx_fsmc.h"

+#endif /* STM32F40_41xxx */

+

+#if defined (STM32F411xE)

+#include "stm32f4xx_flash_ramfunc.h"

+#endif /* STM32F411xE */

+

+#if defined (STM32F446xx)

+#include "stm32f4xx_qspi.h"

+#include "stm32f4xx_fmpi2c.h"

+#include "stm32f4xx_spdifrx.h"

+#include "stm32f4xx_cec.h"

+#endif /* STM32F446xx */

+

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/* If an external clock source is used, then the value of the following define 

+   should be set to the value of the external clock source, else, if no external 

+   clock is used, keep this define commented */

+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */

+

+

+/* Uncomment the line below to expanse the "assert_param" macro in the 

+   Standard Peripheral Library drivers code */

+/* #define USE_FULL_ASSERT    1 */

+

+/* Exported macro ------------------------------------------------------------*/

+#ifdef  USE_FULL_ASSERT

+

+/**

+  * @brief  The assert_param macro is used for function's parameters check.

+  * @param  expr: If expr is false, it calls assert_failed function

+  *   which reports the name of the source file and the source

+  *   line number of the call that failed. 

+  *   If expr is true, it returns no value.

+  * @retval None

+  */

+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))

+/* Exported functions ------------------------------------------------------- */

+  void assert_failed(uint8_t* file, uint32_t line);

+#else

+  #define assert_param(expr) ((void)0)

+#endif /* USE_FULL_ASSERT */

+

+#endif /* __STM32F4xx_CONF_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 301 - 0
stm32/system/syscalls/syscalls.c
Ver arquivo 

@@ -0,0 +1,301 @@
 
+/*
 
+ * newlib_stubs.c
 
+ *
 
+ *  Created on: 2 Nov 2010
 
+ *      Author: nanoage.co.uk
 
+ */
 
+#include <errno.h>
 
+#include <sys/stat.h>
 
+#include <sys/times.h>
 
+#include <sys/unistd.h>
 
+#include "stm32f4xx_usart.h"
 
+#include "stm32f4xx.h"
 
+
 
+#ifdef SWOTRACE
 
+/* Set STDIO_USART to 255 as flag that trace output on SWO pin used instead */
 
+#define STDIO_USART 255
 
+#else
 
+/* Set USART number */
 
+#define STDIO_USART 0 /* Disable UART stdio */
 
+#endif /* SWOTRACE */
 
+
 
+
 
+#ifndef STDOUT_USART
 
+#define STDOUT_USART STDIO_USART
 
+#endif
 
+
 
+#ifndef STDERR_USART
 
+#define STDERR_USART STDIO_USART
 
+#endif
 
+
 
+#ifndef STDIN_USART
 
+#define STDIN_USART STDIO_USART
 
+#endif
 
+
 
+
 
+#undef errno
 
+extern int errno;
 
+
 
+/* Variable to receive characters on SWO */
 
+volatile int32_t ITM_RxBuffer;
 
+
 
+/*
 
+ environ
 
+ A pointer to a list of environment variables and their values.
 
+ For a minimal environment, this empty list is adequate:
 
+ */
 
+char *__env[1] = { 0 };
 
+char **environ = __env;
 
+
 
+int _write(int file, char *ptr, int len);
 
+
 
+void _exit(int status) {
 
+    _write(1, "exit", 4);
 
+    while (1) {
 
+        ;
 
+    }
 
+}
 
+
 
+int _close(int file) {
 
+    return -1;
 
+}
 
+/*
 
+ execve
 
+ Transfer control to a new process. Minimal implementation (for a system without processes):
 
+ */
 
+int _execve(char *name, char **argv, char **env) {
 
+    errno = ENOMEM;
 
+    return -1;
 
+}
 
+/*
 
+ fork
 
+ Create a new process. Minimal implementation (for a system without processes):
 
+ */
 
+
 
+int _fork() {
 
+    errno = EAGAIN;
 
+    return -1;
 
+}
 
+/*
 
+ fstat
 
+ Status of an open file. For consistency with other minimal implementations in these examples,
 
+ all files are regarded as character special devices.
 
+ The `sys/stat.h' header file required is distributed in the `include' subdirectory for this C library.
 
+ */
 
+int _fstat(int file, struct stat *st) {
 
+    st->st_mode = S_IFCHR;
 
+    return 0;
 
+}
 
+
 
+/*
 
+ getpid
 
+ Process-ID; this is sometimes used to generate strings unlikely to conflict with other processes. Minimal implementation, for a system without processes:
 
+ */
 
+
 
+int _getpid() {
 
+    return 1;
 
+}
 
+
 
+/*
 
+ isatty
 
+ Query whether output stream is a terminal. For consistency with the other minimal implementations,
 
+ */
 
+int _isatty(int file) {
 
+    switch (file){
 
+    case STDOUT_FILENO:
 
+    case STDERR_FILENO:
 
+    case STDIN_FILENO:
 
+        return 1;
 
+    default:
 
+        //errno = ENOTTY;
 
+        errno = EBADF;
 
+        return 0;
 
+    }
 
+}
 
+
 
+
 
+/*
 
+ kill
 
+ Send a signal. Minimal implementation:
 
+ */
 
+int _kill(int pid, int sig) {
 
+    errno = EINVAL;
 
+    return (-1);
 
+}
 
+
 
+/*
 
+ link
 
+ Establish a new name for an existing file. Minimal implementation:
 
+ */
 
+
 
+int _link(char *old, char *new) {
 
+    errno = EMLINK;
 
+    return -1;
 
+}
 
+
 
+/*
 
+ lseek
 
+ Set position in a file. Minimal implementation:
 
+ */
 
+int _lseek(int file, int ptr, int dir) {
 
+    return 0;
 
+}
 
+
 
+/*
 
+ sbrk
 
+ Increase program data space.
 
+ Malloc and related functions depend on this
 
+ */
 
+caddr_t _sbrk(int incr) {
 
+
 
+    extern char _ebss; // Defined by the linker
 
+    extern char __bss_end__;
 
+    static char *heap_end;
 
+    char *prev_heap_end;
 
+
 
+    if (heap_end == 0) {
 
+    	//heap_end = &_ebss;
 
+    	heap_end = &__bss_end__;
 
+    }
 
+    prev_heap_end = heap_end;
 
+
 
+char * stack = (char*) __get_MSP();
 
+     if (heap_end + incr >  stack)
 
+     {
 
+         _write (STDERR_FILENO, "Heap and stack collision\n", 25);
 
+         errno = ENOMEM;
 
+         return  (caddr_t) -1;
 
+         //abort ();
 
+     }
 
+
 
+    heap_end += incr;
 
+    return (caddr_t) prev_heap_end;
 
+
 
+}
 
+
 
+/*
 
+ read
 
+ Read a character to a file. `libc' subroutines will use this system routine for input from all files, including stdin
 
+ Returns -1 on error or blocks until the number of characters have been read.
 
+ */
 
+
 
+
 
+int _read(int file, char *ptr, int len) {
 
+    int n;
 
+    int num = 0;
 
+    switch (file) {
 
+    case STDIN_FILENO:
 
+        for (n = 0; n < len; n++) {
 
+#if   STDIN_USART == 1
 
+            while ((USART1->SR & USART_FLAG_RXNE) == (uint16_t)RESET) {}
 
+            char c = (char)(USART1->DR & (uint16_t)0x01FF);
 
+#elif STDIN_USART == 2
 
+            while ((USART2->SR & USART_FLAG_RXNE) == (uint16_t) RESET) {}
 
+            char c = (char) (USART2->DR & (uint16_t) 0x01FF);
 
+#elif STDIN_USART == 3
 
+            while ((USART3->SR & USART_FLAG_RXNE) == (uint16_t)RESET) {}
 
+            char c = (char)(USART3->DR & (uint16_t)0x01FF);
 
+#elif STDIN_USART == 255
 
+            /* TODO Test this feature */
 
+            char c = (char)ITM_ReceiveChar();
 
+#elif STDIN_USART == 0
 
+            /* Return NULL */
 
+            char c = '\0';
 
+#endif
 
+            *ptr++ = c;
 
+            num++;
 
+        }
 
+        break;
 
+    default:
 
+        errno = EBADF;
 
+        return -1;
 
+    }
 
+    return num;
 
+}
 
+
 
+/*
 
+ stat
 
+ Status of a file (by name). Minimal implementation:
 
+ int    _EXFUN(stat,( const char *__path, struct stat *__sbuf ));
 
+ */
 
+
 
+int _stat(const char *filepath, struct stat *st) {
 
+    st->st_mode = S_IFCHR;
 
+    return 0;
 
+}
 
+
 
+/*
 
+ times
 
+ Timing information for current process. Minimal implementation:
 
+ */
 
+
 
+clock_t _times(struct tms *buf) {
 
+    return -1;
 
+}
 
+
 
+/*
 
+ unlink
 
+ Remove a file's directory entry. Minimal implementation:
 
+ */
 
+int _unlink(char *name) {
 
+    errno = ENOENT;
 
+    return -1;
 
+}
 
+
 
+/*
 
+ wait
 
+ Wait for a child process. Minimal implementation:
 
+ */
 
+int _wait(int *status) {
 
+    errno = ECHILD;
 
+    return -1;
 
+}
 
+
 
+/*
 
+ write
 
+ Write a character to a file. `libc' subroutines will use this system routine for output to all files, including stdout
 
+ Returns -1 on error or number of bytes sent
 
+ */
 
+int _write(int file, char *ptr, int len) {
 
+    int n;
 
+    switch (file) {
 
+    case STDOUT_FILENO: /*stdout*/
 
+        for (n = 0; n < len; n++) {
 
+#if STDOUT_USART == 1
 
+            while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET) {}
 
+            USART1->DR = (*ptr++ & (uint16_t)0x01FF);
 
+#elif  STDOUT_USART == 2
 
+            while ((USART2->SR & USART_FLAG_TC) == (uint16_t) RESET) {
 
+            }
 
+            USART2->DR = (*ptr++ & (uint16_t) 0x01FF);
 
+#elif  STDOUT_USART == 3
 
+            while ((USART3->SR & USART_FLAG_TC) == (uint16_t)RESET) {}
 
+            USART3->DR = (*ptr++ & (uint16_t)0x01FF);
 
+#elif STDOUT_USART == 255
 
+            ITM_SendChar(*ptr++ & (uint16_t)0x00FF);
 
+#endif
 
+        }
 
+        break;
 
+    case STDERR_FILENO: /* stderr */
 
+        for (n = 0; n < len; n++) {
 
+#if STDERR_USART == 1
 
+            while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET) {}
 
+            USART1->DR = (*ptr++ & (uint16_t)0x01FF);
 
+#elif  STDERR_USART == 2
 
+            while ((USART2->SR & USART_FLAG_TC) == (uint16_t) RESET) {
 
+            }
 
+            USART2->DR = (*ptr++ & (uint16_t) 0x01FF);
 
+#elif  STDERR_USART == 3
 
+            while ((USART3->SR & USART_FLAG_TC) == (uint16_t)RESET) {}
 
+            USART3->DR = (*ptr++ & (uint16_t)0x01FF);
 
+#elif STDERR_USART == 255
 
+            ITM_SendChar(*ptr++ & (uint16_t)0x00FF);
 
+#endif
 
+        }
 
+        break;
 
+    default:
 
+        errno = EBADF;
 
+        return -1;
 
+    }
 
+    return len;
 
+}

Alguns arquivos não foram mostrados porque muitos arquivos mudaram nesse diff