stm32f4xx_adc.c 65 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_adc.c
  4. * @author MCD Application Team
  5. * @version V1.0.2
  6. * @date 05-March-2012
  7. * @brief This file provides firmware functions to manage the following
  8. * functionalities of the Analog to Digital Convertor (ADC) peripheral:
  9. * - Initialization and Configuration (in addition to ADC multi mode
  10. * selection)
  11. * - Analog Watchdog configuration
  12. * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
  13. * management
  14. * - Regular Channels Configuration
  15. * - Regular Channels DMA Configuration
  16. * - Injected channels Configuration
  17. * - Interrupts and flags management
  18. *
  19. * @verbatim
  20. *
  21. * ===================================================================
  22. * How to use this driver
  23. * ===================================================================
  24. * 1. Enable the ADC interface clock using
  25. * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
  26. *
  27. * 2. ADC pins configuration
  28. * - Enable the clock for the ADC GPIOs using the following function:
  29. * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
  30. * - Configure these ADC pins in analog mode using GPIO_Init();
  31. *
  32. * 3. Configure the ADC Prescaler, conversion resolution and data
  33. * alignment using the ADC_Init() function.
  34. * 4. Activate the ADC peripheral using ADC_Cmd() function.
  35. *
  36. * Regular channels group configuration
  37. * ====================================
  38. * - To configure the ADC regular channels group features, use
  39. * ADC_Init() and ADC_RegularChannelConfig() functions.
  40. * - To activate the continuous mode, use the ADC_continuousModeCmd()
  41. * function.
  42. * - To configurate and activate the Discontinuous mode, use the
  43. * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
  44. * - To read the ADC converted values, use the ADC_GetConversionValue()
  45. * function.
  46. *
  47. * Multi mode ADCs Regular channels configuration
  48. * ===============================================
  49. * - Refer to "Regular channels group configuration" description to
  50. * configure the ADC1, ADC2 and ADC3 regular channels.
  51. * - Select the Multi mode ADC regular channels features (dual or
  52. * triple mode) using ADC_CommonInit() function and configure
  53. * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
  54. * functions.
  55. * - Read the ADCs converted values using the
  56. * ADC_GetMultiModeConversionValue() function.
  57. *
  58. * DMA for Regular channels group features configuration
  59. * ======================================================
  60. * - To enable the DMA mode for regular channels group, use the
  61. * ADC_DMACmd() function.
  62. * - To enable the generation of DMA requests continuously at the end
  63. * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
  64. * function.
  65. *
  66. * Injected channels group configuration
  67. * =====================================
  68. * - To configure the ADC Injected channels group features, use
  69. * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
  70. * functions.
  71. * - To activate the continuous mode, use the ADC_continuousModeCmd()
  72. * function.
  73. * - To activate the Injected Discontinuous mode, use the
  74. * ADC_InjectedDiscModeCmd() function.
  75. * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
  76. * function.
  77. * - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
  78. * function.
  79. *
  80. * @endverbatim
  81. *
  82. ******************************************************************************
  83. * @attention
  84. *
  85. * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  86. *
  87. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  88. * You may not use this file except in compliance with the License.
  89. * You may obtain a copy of the License at:
  90. *
  91. * http://www.st.com/software_license_agreement_liberty_v2
  92. *
  93. * Unless required by applicable law or agreed to in writing, software
  94. * distributed under the License is distributed on an "AS IS" BASIS,
  95. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  96. * See the License for the specific language governing permissions and
  97. * limitations under the License.
  98. *
  99. ******************************************************************************
  100. */
  101. /* Includes ------------------------------------------------------------------*/
  102. #include "stm32f4xx_adc.h"
  103. #include "stm32f4xx_rcc.h"
  104. /** @addtogroup STM32F4xx_StdPeriph_Driver
  105. * @{
  106. */
  107. /** @defgroup ADC
  108. * @brief ADC driver modules
  109. * @{
  110. */
  111. /* Private typedef -----------------------------------------------------------*/
  112. /* Private define ------------------------------------------------------------*/
  113. /* ADC DISCNUM mask */
  114. #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
  115. /* ADC AWDCH mask */
  116. #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
  117. /* ADC Analog watchdog enable mode mask */
  118. #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF)
  119. /* CR1 register Mask */
  120. #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
  121. /* ADC EXTEN mask */
  122. #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF)
  123. /* ADC JEXTEN mask */
  124. #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
  125. /* ADC JEXTSEL mask */
  126. #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
  127. /* CR2 register Mask */
  128. #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
  129. /* ADC SQx mask */
  130. #define SQR3_SQ_SET ((uint32_t)0x0000001F)
  131. #define SQR2_SQ_SET ((uint32_t)0x0000001F)
  132. #define SQR1_SQ_SET ((uint32_t)0x0000001F)
  133. /* ADC L Mask */
  134. #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF)
  135. /* ADC JSQx mask */
  136. #define JSQR_JSQ_SET ((uint32_t)0x0000001F)
  137. /* ADC JL mask */
  138. #define JSQR_JL_SET ((uint32_t)0x00300000)
  139. #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
  140. /* ADC SMPx mask */
  141. #define SMPR1_SMP_SET ((uint32_t)0x00000007)
  142. #define SMPR2_SMP_SET ((uint32_t)0x00000007)
  143. /* ADC JDRx registers offset */
  144. #define JDR_OFFSET ((uint8_t)0x28)
  145. /* ADC CDR register base address */
  146. #define CDR_ADDRESS ((uint32_t)0x40012308)
  147. /* ADC CCR register Mask */
  148. #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0)
  149. /* Private macro -------------------------------------------------------------*/
  150. /* Private variables ---------------------------------------------------------*/
  151. /* Private function prototypes -----------------------------------------------*/
  152. /* Private functions ---------------------------------------------------------*/
  153. /** @defgroup ADC_Private_Functions
  154. * @{
  155. */
  156. /** @defgroup ADC_Group1 Initialization and Configuration functions
  157. * @brief Initialization and Configuration functions
  158. *
  159. @verbatim
  160. ===============================================================================
  161. Initialization and Configuration functions
  162. ===============================================================================
  163. This section provides functions allowing to:
  164. - Initialize and configure the ADC Prescaler
  165. - ADC Conversion Resolution (12bit..6bit)
  166. - Scan Conversion Mode (multichannels or one channel) for regular group
  167. - ADC Continuous Conversion Mode (Continuous or Single conversion) for
  168. regular group
  169. - External trigger Edge and source of regular group,
  170. - Converted data alignment (left or right)
  171. - The number of ADC conversions that will be done using the sequencer for
  172. regular channel group
  173. - Multi ADC mode selection
  174. - Direct memory access mode selection for multi ADC mode
  175. - Delay between 2 sampling phases (used in dual or triple interleaved modes)
  176. - Enable or disable the ADC peripheral
  177. @endverbatim
  178. * @{
  179. */
  180. /**
  181. * @brief Deinitializes all ADCs peripherals registers to their default reset
  182. * values.
  183. * @param None
  184. * @retval None
  185. */
  186. void ADC_DeInit(void)
  187. {
  188. /* Enable all ADCs reset state */
  189. RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
  190. /* Release all ADCs from reset state */
  191. RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
  192. }
  193. /**
  194. * @brief Initializes the ADCx peripheral according to the specified parameters
  195. * in the ADC_InitStruct.
  196. * @note This function is used to configure the global features of the ADC (
  197. * Resolution and Data Alignment), however, the rest of the configuration
  198. * parameters are specific to the regular channels group (scan mode
  199. * activation, continuous mode activation, External trigger source and
  200. * edge, number of conversion in the regular channels group sequencer).
  201. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  202. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
  203. * the configuration information for the specified ADC peripheral.
  204. * @retval None
  205. */
  206. void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
  207. {
  208. uint32_t tmpreg1 = 0;
  209. uint8_t tmpreg2 = 0;
  210. /* Check the parameters */
  211. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  212. assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
  213. assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
  214. assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
  215. assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
  216. assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
  217. assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
  218. assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
  219. /*---------------------------- ADCx CR1 Configuration -----------------*/
  220. /* Get the ADCx CR1 value */
  221. tmpreg1 = ADCx->CR1;
  222. /* Clear RES and SCAN bits */
  223. tmpreg1 &= CR1_CLEAR_MASK;
  224. /* Configure ADCx: scan conversion mode and resolution */
  225. /* Set SCAN bit according to ADC_ScanConvMode value */
  226. /* Set RES bit according to ADC_Resolution value */
  227. tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
  228. ADC_InitStruct->ADC_Resolution);
  229. /* Write to ADCx CR1 */
  230. ADCx->CR1 = tmpreg1;
  231. /*---------------------------- ADCx CR2 Configuration -----------------*/
  232. /* Get the ADCx CR2 value */
  233. tmpreg1 = ADCx->CR2;
  234. /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
  235. tmpreg1 &= CR2_CLEAR_MASK;
  236. /* Configure ADCx: external trigger event and edge, data alignment and
  237. continuous conversion mode */
  238. /* Set ALIGN bit according to ADC_DataAlign value */
  239. /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
  240. /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
  241. /* Set CONT bit according to ADC_ContinuousConvMode value */
  242. tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
  243. ADC_InitStruct->ADC_ExternalTrigConv |
  244. ADC_InitStruct->ADC_ExternalTrigConvEdge | \
  245. ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
  246. /* Write to ADCx CR2 */
  247. ADCx->CR2 = tmpreg1;
  248. /*---------------------------- ADCx SQR1 Configuration -----------------*/
  249. /* Get the ADCx SQR1 value */
  250. tmpreg1 = ADCx->SQR1;
  251. /* Clear L bits */
  252. tmpreg1 &= SQR1_L_RESET;
  253. /* Configure ADCx: regular channel sequence length */
  254. /* Set L bits according to ADC_NbrOfConversion value */
  255. tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
  256. tmpreg1 |= ((uint32_t)tmpreg2 << 20);
  257. /* Write to ADCx SQR1 */
  258. ADCx->SQR1 = tmpreg1;
  259. }
  260. /**
  261. * @brief Fills each ADC_InitStruct member with its default value.
  262. * @note This function is used to initialize the global features of the ADC (
  263. * Resolution and Data Alignment), however, the rest of the configuration
  264. * parameters are specific to the regular channels group (scan mode
  265. * activation, continuous mode activation, External trigger source and
  266. * edge, number of conversion in the regular channels group sequencer).
  267. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
  268. * be initialized.
  269. * @retval None
  270. */
  271. void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
  272. {
  273. /* Initialize the ADC_Mode member */
  274. ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
  275. /* initialize the ADC_ScanConvMode member */
  276. ADC_InitStruct->ADC_ScanConvMode = DISABLE;
  277. /* Initialize the ADC_ContinuousConvMode member */
  278. ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
  279. /* Initialize the ADC_ExternalTrigConvEdge member */
  280. ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
  281. /* Initialize the ADC_ExternalTrigConv member */
  282. ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
  283. /* Initialize the ADC_DataAlign member */
  284. ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
  285. /* Initialize the ADC_NbrOfConversion member */
  286. ADC_InitStruct->ADC_NbrOfConversion = 1;
  287. }
  288. /**
  289. * @brief Initializes the ADCs peripherals according to the specified parameters
  290. * in the ADC_CommonInitStruct.
  291. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
  292. * that contains the configuration information for All ADCs peripherals.
  293. * @retval None
  294. */
  295. void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
  296. {
  297. uint32_t tmpreg1 = 0;
  298. /* Check the parameters */
  299. assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
  300. assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
  301. assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
  302. assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
  303. /*---------------------------- ADC CCR Configuration -----------------*/
  304. /* Get the ADC CCR value */
  305. tmpreg1 = ADC->CCR;
  306. /* Clear MULTI, DELAY, DMA and ADCPRE bits */
  307. tmpreg1 &= CR_CLEAR_MASK;
  308. /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
  309. and DMA access mode for multimode */
  310. /* Set MULTI bits according to ADC_Mode value */
  311. /* Set ADCPRE bits according to ADC_Prescaler value */
  312. /* Set DMA bits according to ADC_DMAAccessMode value */
  313. /* Set DELAY bits according to ADC_TwoSamplingDelay value */
  314. tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode |
  315. ADC_CommonInitStruct->ADC_Prescaler |
  316. ADC_CommonInitStruct->ADC_DMAAccessMode |
  317. ADC_CommonInitStruct->ADC_TwoSamplingDelay);
  318. /* Write to ADC CCR */
  319. ADC->CCR = tmpreg1;
  320. }
  321. /**
  322. * @brief Fills each ADC_CommonInitStruct member with its default value.
  323. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
  324. * which will be initialized.
  325. * @retval None
  326. */
  327. void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
  328. {
  329. /* Initialize the ADC_Mode member */
  330. ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
  331. /* initialize the ADC_Prescaler member */
  332. ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
  333. /* Initialize the ADC_DMAAccessMode member */
  334. ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
  335. /* Initialize the ADC_TwoSamplingDelay member */
  336. ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
  337. }
  338. /**
  339. * @brief Enables or disables the specified ADC peripheral.
  340. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  341. * @param NewState: new state of the ADCx peripheral.
  342. * This parameter can be: ENABLE or DISABLE.
  343. * @retval None
  344. */
  345. void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  346. {
  347. /* Check the parameters */
  348. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  349. assert_param(IS_FUNCTIONAL_STATE(NewState));
  350. if (NewState != DISABLE)
  351. {
  352. /* Set the ADON bit to wake up the ADC from power down mode */
  353. ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
  354. }
  355. else
  356. {
  357. /* Disable the selected ADC peripheral */
  358. ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
  359. }
  360. }
  361. /**
  362. * @}
  363. */
  364. /** @defgroup ADC_Group2 Analog Watchdog configuration functions
  365. * @brief Analog Watchdog configuration functions
  366. *
  367. @verbatim
  368. ===============================================================================
  369. Analog Watchdog configuration functions
  370. ===============================================================================
  371. This section provides functions allowing to configure the Analog Watchdog
  372. (AWD) feature in the ADC.
  373. A typical configuration Analog Watchdog is done following these steps :
  374. 1. the ADC guarded channel(s) is (are) selected using the
  375. ADC_AnalogWatchdogSingleChannelConfig() function.
  376. 2. The Analog watchdog lower and higher threshold are configured using the
  377. ADC_AnalogWatchdogThresholdsConfig() function.
  378. 3. The Analog watchdog is enabled and configured to enable the check, on one
  379. or more channels, using the ADC_AnalogWatchdogCmd() function.
  380. @endverbatim
  381. * @{
  382. */
  383. /**
  384. * @brief Enables or disables the analog watchdog on single/all regular or
  385. * injected channels
  386. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  387. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
  388. * This parameter can be one of the following values:
  389. * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
  390. * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
  391. * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
  392. * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
  393. * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
  394. * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
  395. * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
  396. * @retval None
  397. */
  398. void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
  399. {
  400. uint32_t tmpreg = 0;
  401. /* Check the parameters */
  402. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  403. assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
  404. /* Get the old register value */
  405. tmpreg = ADCx->CR1;
  406. /* Clear AWDEN, JAWDEN and AWDSGL bits */
  407. tmpreg &= CR1_AWDMode_RESET;
  408. /* Set the analog watchdog enable mode */
  409. tmpreg |= ADC_AnalogWatchdog;
  410. /* Store the new register value */
  411. ADCx->CR1 = tmpreg;
  412. }
  413. /**
  414. * @brief Configures the high and low thresholds of the analog watchdog.
  415. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  416. * @param HighThreshold: the ADC analog watchdog High threshold value.
  417. * This parameter must be a 12-bit value.
  418. * @param LowThreshold: the ADC analog watchdog Low threshold value.
  419. * This parameter must be a 12-bit value.
  420. * @retval None
  421. */
  422. void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
  423. uint16_t LowThreshold)
  424. {
  425. /* Check the parameters */
  426. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  427. assert_param(IS_ADC_THRESHOLD(HighThreshold));
  428. assert_param(IS_ADC_THRESHOLD(LowThreshold));
  429. /* Set the ADCx high threshold */
  430. ADCx->HTR = HighThreshold;
  431. /* Set the ADCx low threshold */
  432. ADCx->LTR = LowThreshold;
  433. }
  434. /**
  435. * @brief Configures the analog watchdog guarded single channel
  436. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  437. * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
  438. * This parameter can be one of the following values:
  439. * @arg ADC_Channel_0: ADC Channel0 selected
  440. * @arg ADC_Channel_1: ADC Channel1 selected
  441. * @arg ADC_Channel_2: ADC Channel2 selected
  442. * @arg ADC_Channel_3: ADC Channel3 selected
  443. * @arg ADC_Channel_4: ADC Channel4 selected
  444. * @arg ADC_Channel_5: ADC Channel5 selected
  445. * @arg ADC_Channel_6: ADC Channel6 selected
  446. * @arg ADC_Channel_7: ADC Channel7 selected
  447. * @arg ADC_Channel_8: ADC Channel8 selected
  448. * @arg ADC_Channel_9: ADC Channel9 selected
  449. * @arg ADC_Channel_10: ADC Channel10 selected
  450. * @arg ADC_Channel_11: ADC Channel11 selected
  451. * @arg ADC_Channel_12: ADC Channel12 selected
  452. * @arg ADC_Channel_13: ADC Channel13 selected
  453. * @arg ADC_Channel_14: ADC Channel14 selected
  454. * @arg ADC_Channel_15: ADC Channel15 selected
  455. * @arg ADC_Channel_16: ADC Channel16 selected
  456. * @arg ADC_Channel_17: ADC Channel17 selected
  457. * @arg ADC_Channel_18: ADC Channel18 selected
  458. * @retval None
  459. */
  460. void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
  461. {
  462. uint32_t tmpreg = 0;
  463. /* Check the parameters */
  464. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  465. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  466. /* Get the old register value */
  467. tmpreg = ADCx->CR1;
  468. /* Clear the Analog watchdog channel select bits */
  469. tmpreg &= CR1_AWDCH_RESET;
  470. /* Set the Analog watchdog channel */
  471. tmpreg |= ADC_Channel;
  472. /* Store the new register value */
  473. ADCx->CR1 = tmpreg;
  474. }
  475. /**
  476. * @}
  477. */
  478. /** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal)
  479. * and VBAT (Voltage BATtery) management functions
  480. * @brief Temperature Sensor, Vrefint and VBAT management functions
  481. *
  482. @verbatim
  483. ===============================================================================
  484. Temperature Sensor, Vrefint and VBAT management functions
  485. ===============================================================================
  486. This section provides functions allowing to enable/ disable the internal
  487. connections between the ADC and the Temperature Sensor, the Vrefint and the
  488. Vbat sources.
  489. A typical configuration to get the Temperature sensor and Vrefint channels
  490. voltages is done following these steps :
  491. 1. Enable the internal connection of Temperature sensor and Vrefint sources
  492. with the ADC channels using ADC_TempSensorVrefintCmd() function.
  493. 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
  494. ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
  495. 3. Get the voltage values, using ADC_GetConversionValue() or
  496. ADC_GetInjectedConversionValue().
  497. A typical configuration to get the VBAT channel voltage is done following
  498. these steps :
  499. 1. Enable the internal connection of VBAT source with the ADC channel using
  500. ADC_VBATCmd() function.
  501. 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
  502. ADC_InjectedChannelConfig() functions
  503. 3. Get the voltage value, using ADC_GetConversionValue() or
  504. ADC_GetInjectedConversionValue().
  505. @endverbatim
  506. * @{
  507. */
  508. /**
  509. * @brief Enables or disables the temperature sensor and Vrefint channels.
  510. * @param NewState: new state of the temperature sensor and Vrefint channels.
  511. * This parameter can be: ENABLE or DISABLE.
  512. * @retval None
  513. */
  514. void ADC_TempSensorVrefintCmd(FunctionalState NewState)
  515. {
  516. /* Check the parameters */
  517. assert_param(IS_FUNCTIONAL_STATE(NewState));
  518. if (NewState != DISABLE)
  519. {
  520. /* Enable the temperature sensor and Vrefint channel*/
  521. ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
  522. }
  523. else
  524. {
  525. /* Disable the temperature sensor and Vrefint channel*/
  526. ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
  527. }
  528. }
  529. /**
  530. * @brief Enables or disables the VBAT (Voltage Battery) channel.
  531. * @param NewState: new state of the VBAT channel.
  532. * This parameter can be: ENABLE or DISABLE.
  533. * @retval None
  534. */
  535. void ADC_VBATCmd(FunctionalState NewState)
  536. {
  537. /* Check the parameters */
  538. assert_param(IS_FUNCTIONAL_STATE(NewState));
  539. if (NewState != DISABLE)
  540. {
  541. /* Enable the VBAT channel*/
  542. ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
  543. }
  544. else
  545. {
  546. /* Disable the VBAT channel*/
  547. ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
  548. }
  549. }
  550. /**
  551. * @}
  552. */
  553. /** @defgroup ADC_Group4 Regular Channels Configuration functions
  554. * @brief Regular Channels Configuration functions
  555. *
  556. @verbatim
  557. ===============================================================================
  558. Regular Channels Configuration functions
  559. ===============================================================================
  560. This section provides functions allowing to manage the ADC's regular channels,
  561. it is composed of 2 sub sections :
  562. 1. Configuration and management functions for regular channels: This subsection
  563. provides functions allowing to configure the ADC regular channels :
  564. - Configure the rank in the regular group sequencer for each channel
  565. - Configure the sampling time for each channel
  566. - select the conversion Trigger for regular channels
  567. - select the desired EOC event behavior configuration
  568. - Activate the continuous Mode (*)
  569. - Activate the Discontinuous Mode
  570. Please Note that the following features for regular channels are configurated
  571. using the ADC_Init() function :
  572. - scan mode activation
  573. - continuous mode activation (**)
  574. - External trigger source
  575. - External trigger edge
  576. - number of conversion in the regular channels group sequencer.
  577. @note (*) and (**) are performing the same configuration
  578. 2. Get the conversion data: This subsection provides an important function in
  579. the ADC peripheral since it returns the converted data of the current
  580. regular channel. When the Conversion value is read, the EOC Flag is
  581. automatically cleared.
  582. @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
  583. results data (in the selected multi mode) can be returned in the same
  584. time using ADC_GetMultiModeConversionValue() function.
  585. @endverbatim
  586. * @{
  587. */
  588. /**
  589. * @brief Configures for the selected ADC regular channel its corresponding
  590. * rank in the sequencer and its sample time.
  591. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  592. * @param ADC_Channel: the ADC channel to configure.
  593. * This parameter can be one of the following values:
  594. * @arg ADC_Channel_0: ADC Channel0 selected
  595. * @arg ADC_Channel_1: ADC Channel1 selected
  596. * @arg ADC_Channel_2: ADC Channel2 selected
  597. * @arg ADC_Channel_3: ADC Channel3 selected
  598. * @arg ADC_Channel_4: ADC Channel4 selected
  599. * @arg ADC_Channel_5: ADC Channel5 selected
  600. * @arg ADC_Channel_6: ADC Channel6 selected
  601. * @arg ADC_Channel_7: ADC Channel7 selected
  602. * @arg ADC_Channel_8: ADC Channel8 selected
  603. * @arg ADC_Channel_9: ADC Channel9 selected
  604. * @arg ADC_Channel_10: ADC Channel10 selected
  605. * @arg ADC_Channel_11: ADC Channel11 selected
  606. * @arg ADC_Channel_12: ADC Channel12 selected
  607. * @arg ADC_Channel_13: ADC Channel13 selected
  608. * @arg ADC_Channel_14: ADC Channel14 selected
  609. * @arg ADC_Channel_15: ADC Channel15 selected
  610. * @arg ADC_Channel_16: ADC Channel16 selected
  611. * @arg ADC_Channel_17: ADC Channel17 selected
  612. * @arg ADC_Channel_18: ADC Channel18 selected
  613. * @param Rank: The rank in the regular group sequencer.
  614. * This parameter must be between 1 to 16.
  615. * @param ADC_SampleTime: The sample time value to be set for the selected channel.
  616. * This parameter can be one of the following values:
  617. * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
  618. * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
  619. * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
  620. * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
  621. * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
  622. * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
  623. * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
  624. * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
  625. * @retval None
  626. */
  627. void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
  628. {
  629. uint32_t tmpreg1 = 0, tmpreg2 = 0;
  630. /* Check the parameters */
  631. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  632. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  633. assert_param(IS_ADC_REGULAR_RANK(Rank));
  634. assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
  635. /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
  636. if (ADC_Channel > ADC_Channel_9)
  637. {
  638. /* Get the old register value */
  639. tmpreg1 = ADCx->SMPR1;
  640. /* Calculate the mask to clear */
  641. tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
  642. /* Clear the old sample time */
  643. tmpreg1 &= ~tmpreg2;
  644. /* Calculate the mask to set */
  645. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
  646. /* Set the new sample time */
  647. tmpreg1 |= tmpreg2;
  648. /* Store the new register value */
  649. ADCx->SMPR1 = tmpreg1;
  650. }
  651. else /* ADC_Channel include in ADC_Channel_[0..9] */
  652. {
  653. /* Get the old register value */
  654. tmpreg1 = ADCx->SMPR2;
  655. /* Calculate the mask to clear */
  656. tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
  657. /* Clear the old sample time */
  658. tmpreg1 &= ~tmpreg2;
  659. /* Calculate the mask to set */
  660. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
  661. /* Set the new sample time */
  662. tmpreg1 |= tmpreg2;
  663. /* Store the new register value */
  664. ADCx->SMPR2 = tmpreg1;
  665. }
  666. /* For Rank 1 to 6 */
  667. if (Rank < 7)
  668. {
  669. /* Get the old register value */
  670. tmpreg1 = ADCx->SQR3;
  671. /* Calculate the mask to clear */
  672. tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
  673. /* Clear the old SQx bits for the selected rank */
  674. tmpreg1 &= ~tmpreg2;
  675. /* Calculate the mask to set */
  676. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
  677. /* Set the SQx bits for the selected rank */
  678. tmpreg1 |= tmpreg2;
  679. /* Store the new register value */
  680. ADCx->SQR3 = tmpreg1;
  681. }
  682. /* For Rank 7 to 12 */
  683. else if (Rank < 13)
  684. {
  685. /* Get the old register value */
  686. tmpreg1 = ADCx->SQR2;
  687. /* Calculate the mask to clear */
  688. tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
  689. /* Clear the old SQx bits for the selected rank */
  690. tmpreg1 &= ~tmpreg2;
  691. /* Calculate the mask to set */
  692. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
  693. /* Set the SQx bits for the selected rank */
  694. tmpreg1 |= tmpreg2;
  695. /* Store the new register value */
  696. ADCx->SQR2 = tmpreg1;
  697. }
  698. /* For Rank 13 to 16 */
  699. else
  700. {
  701. /* Get the old register value */
  702. tmpreg1 = ADCx->SQR1;
  703. /* Calculate the mask to clear */
  704. tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
  705. /* Clear the old SQx bits for the selected rank */
  706. tmpreg1 &= ~tmpreg2;
  707. /* Calculate the mask to set */
  708. tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
  709. /* Set the SQx bits for the selected rank */
  710. tmpreg1 |= tmpreg2;
  711. /* Store the new register value */
  712. ADCx->SQR1 = tmpreg1;
  713. }
  714. }
  715. /**
  716. * @brief Enables the selected ADC software start conversion of the regular channels.
  717. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  718. * @retval None
  719. */
  720. void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
  721. {
  722. /* Check the parameters */
  723. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  724. /* Enable the selected ADC conversion for regular group */
  725. ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
  726. }
  727. /**
  728. * @brief Gets the selected ADC Software start regular conversion Status.
  729. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  730. * @retval The new state of ADC software start conversion (SET or RESET).
  731. */
  732. FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
  733. {
  734. FlagStatus bitstatus = RESET;
  735. /* Check the parameters */
  736. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  737. /* Check the status of SWSTART bit */
  738. if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
  739. {
  740. /* SWSTART bit is set */
  741. bitstatus = SET;
  742. }
  743. else
  744. {
  745. /* SWSTART bit is reset */
  746. bitstatus = RESET;
  747. }
  748. /* Return the SWSTART bit status */
  749. return bitstatus;
  750. }
  751. /**
  752. * @brief Enables or disables the EOC on each regular channel conversion
  753. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  754. * @param NewState: new state of the selected ADC EOC flag rising
  755. * This parameter can be: ENABLE or DISABLE.
  756. * @retval None
  757. */
  758. void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  759. {
  760. /* Check the parameters */
  761. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  762. assert_param(IS_FUNCTIONAL_STATE(NewState));
  763. if (NewState != DISABLE)
  764. {
  765. /* Enable the selected ADC EOC rising on each regular channel conversion */
  766. ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
  767. }
  768. else
  769. {
  770. /* Disable the selected ADC EOC rising on each regular channel conversion */
  771. ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
  772. }
  773. }
  774. /**
  775. * @brief Enables or disables the ADC continuous conversion mode
  776. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  777. * @param NewState: new state of the selected ADC continuous conversion mode
  778. * This parameter can be: ENABLE or DISABLE.
  779. * @retval None
  780. */
  781. void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  782. {
  783. /* Check the parameters */
  784. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  785. assert_param(IS_FUNCTIONAL_STATE(NewState));
  786. if (NewState != DISABLE)
  787. {
  788. /* Enable the selected ADC continuous conversion mode */
  789. ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
  790. }
  791. else
  792. {
  793. /* Disable the selected ADC continuous conversion mode */
  794. ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
  795. }
  796. }
  797. /**
  798. * @brief Configures the discontinuous mode for the selected ADC regular group
  799. * channel.
  800. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  801. * @param Number: specifies the discontinuous mode regular channel count value.
  802. * This number must be between 1 and 8.
  803. * @retval None
  804. */
  805. void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
  806. {
  807. uint32_t tmpreg1 = 0;
  808. uint32_t tmpreg2 = 0;
  809. /* Check the parameters */
  810. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  811. assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
  812. /* Get the old register value */
  813. tmpreg1 = ADCx->CR1;
  814. /* Clear the old discontinuous mode channel count */
  815. tmpreg1 &= CR1_DISCNUM_RESET;
  816. /* Set the discontinuous mode channel count */
  817. tmpreg2 = Number - 1;
  818. tmpreg1 |= tmpreg2 << 13;
  819. /* Store the new register value */
  820. ADCx->CR1 = tmpreg1;
  821. }
  822. /**
  823. * @brief Enables or disables the discontinuous mode on regular group channel
  824. * for the specified ADC
  825. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  826. * @param NewState: new state of the selected ADC discontinuous mode on
  827. * regular group channel.
  828. * This parameter can be: ENABLE or DISABLE.
  829. * @retval None
  830. */
  831. void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  832. {
  833. /* Check the parameters */
  834. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  835. assert_param(IS_FUNCTIONAL_STATE(NewState));
  836. if (NewState != DISABLE)
  837. {
  838. /* Enable the selected ADC regular discontinuous mode */
  839. ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
  840. }
  841. else
  842. {
  843. /* Disable the selected ADC regular discontinuous mode */
  844. ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
  845. }
  846. }
  847. /**
  848. * @brief Returns the last ADCx conversion result data for regular channel.
  849. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  850. * @retval The Data conversion value.
  851. */
  852. uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
  853. {
  854. /* Check the parameters */
  855. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  856. /* Return the selected ADC conversion value */
  857. return (uint16_t) ADCx->DR;
  858. }
  859. /**
  860. * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results
  861. * data in the selected multi mode.
  862. * @param None
  863. * @retval The Data conversion value.
  864. * @note In dual mode, the value returned by this function is as following
  865. * Data[15:0] : these bits contain the regular data of ADC1.
  866. * Data[31:16]: these bits contain the regular data of ADC2.
  867. * @note In triple mode, the value returned by this function is as following
  868. * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
  869. * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
  870. */
  871. uint32_t ADC_GetMultiModeConversionValue(void)
  872. {
  873. /* Return the multi mode conversion value */
  874. return (*(__IO uint32_t *) CDR_ADDRESS);
  875. }
  876. /**
  877. * @}
  878. */
  879. /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
  880. * @brief Regular Channels DMA Configuration functions
  881. *
  882. @verbatim
  883. ===============================================================================
  884. Regular Channels DMA Configuration functions
  885. ===============================================================================
  886. This section provides functions allowing to configure the DMA for ADC regular
  887. channels.
  888. Since converted regular channel values are stored into a unique data register,
  889. it is useful to use DMA for conversion of more than one regular channel. This
  890. avoids the loss of the data already stored in the ADC Data register.
  891. When the DMA mode is enabled (using the ADC_DMACmd() function), after each
  892. conversion of a regular channel, a DMA request is generated.
  893. Depending on the "DMA disable selection for Independent ADC mode"
  894. configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
  895. at the end of the last DMA transfer, two possibilities are allowed:
  896. - No new DMA request is issued to the DMA controller (feature DISABLED)
  897. - Requests can continue to be generated (feature ENABLED).
  898. Depending on the "DMA disable selection for multi ADC mode" configuration
  899. (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
  900. at the end of the last DMA transfer, two possibilities are allowed:
  901. - No new DMA request is issued to the DMA controller (feature DISABLED)
  902. - Requests can continue to be generated (feature ENABLED).
  903. @endverbatim
  904. * @{
  905. */
  906. /**
  907. * @brief Enables or disables the specified ADC DMA request.
  908. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  909. * @param NewState: new state of the selected ADC DMA transfer.
  910. * This parameter can be: ENABLE or DISABLE.
  911. * @retval None
  912. */
  913. void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  914. {
  915. /* Check the parameters */
  916. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  917. assert_param(IS_FUNCTIONAL_STATE(NewState));
  918. if (NewState != DISABLE)
  919. {
  920. /* Enable the selected ADC DMA request */
  921. ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
  922. }
  923. else
  924. {
  925. /* Disable the selected ADC DMA request */
  926. ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
  927. }
  928. }
  929. /**
  930. * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
  931. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  932. * @param NewState: new state of the selected ADC DMA request after last transfer.
  933. * This parameter can be: ENABLE or DISABLE.
  934. * @retval None
  935. */
  936. void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  937. {
  938. /* Check the parameters */
  939. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  940. assert_param(IS_FUNCTIONAL_STATE(NewState));
  941. if (NewState != DISABLE)
  942. {
  943. /* Enable the selected ADC DMA request after last transfer */
  944. ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
  945. }
  946. else
  947. {
  948. /* Disable the selected ADC DMA request after last transfer */
  949. ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
  950. }
  951. }
  952. /**
  953. * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode
  954. * @param NewState: new state of the selected ADC DMA request after last transfer.
  955. * This parameter can be: ENABLE or DISABLE.
  956. * @note if Enabled, DMA requests are issued as long as data are converted and
  957. * DMA mode for multi ADC mode (selected using ADC_CommonInit() function
  958. * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is
  959. * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
  960. * @retval None
  961. */
  962. void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
  963. {
  964. /* Check the parameters */
  965. assert_param(IS_FUNCTIONAL_STATE(NewState));
  966. if (NewState != DISABLE)
  967. {
  968. /* Enable the selected ADC DMA request after last transfer */
  969. ADC->CCR |= (uint32_t)ADC_CCR_DDS;
  970. }
  971. else
  972. {
  973. /* Disable the selected ADC DMA request after last transfer */
  974. ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
  975. }
  976. }
  977. /**
  978. * @}
  979. */
  980. /** @defgroup ADC_Group6 Injected channels Configuration functions
  981. * @brief Injected channels Configuration functions
  982. *
  983. @verbatim
  984. ===============================================================================
  985. Injected channels Configuration functions
  986. ===============================================================================
  987. This section provide functions allowing to configure the ADC Injected channels,
  988. it is composed of 2 sub sections :
  989. 1. Configuration functions for Injected channels: This subsection provides
  990. functions allowing to configure the ADC injected channels :
  991. - Configure the rank in the injected group sequencer for each channel
  992. - Configure the sampling time for each channel
  993. - Activate the Auto injected Mode
  994. - Activate the Discontinuous Mode
  995. - scan mode activation
  996. - External/software trigger source
  997. - External trigger edge
  998. - injected channels sequencer.
  999. 2. Get the Specified Injected channel conversion data: This subsection
  1000. provides an important function in the ADC peripheral since it returns the
  1001. converted data of the specific injected channel.
  1002. @endverbatim
  1003. * @{
  1004. */
  1005. /**
  1006. * @brief Configures for the selected ADC injected channel its corresponding
  1007. * rank in the sequencer and its sample time.
  1008. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1009. * @param ADC_Channel: the ADC channel to configure.
  1010. * This parameter can be one of the following values:
  1011. * @arg ADC_Channel_0: ADC Channel0 selected
  1012. * @arg ADC_Channel_1: ADC Channel1 selected
  1013. * @arg ADC_Channel_2: ADC Channel2 selected
  1014. * @arg ADC_Channel_3: ADC Channel3 selected
  1015. * @arg ADC_Channel_4: ADC Channel4 selected
  1016. * @arg ADC_Channel_5: ADC Channel5 selected
  1017. * @arg ADC_Channel_6: ADC Channel6 selected
  1018. * @arg ADC_Channel_7: ADC Channel7 selected
  1019. * @arg ADC_Channel_8: ADC Channel8 selected
  1020. * @arg ADC_Channel_9: ADC Channel9 selected
  1021. * @arg ADC_Channel_10: ADC Channel10 selected
  1022. * @arg ADC_Channel_11: ADC Channel11 selected
  1023. * @arg ADC_Channel_12: ADC Channel12 selected
  1024. * @arg ADC_Channel_13: ADC Channel13 selected
  1025. * @arg ADC_Channel_14: ADC Channel14 selected
  1026. * @arg ADC_Channel_15: ADC Channel15 selected
  1027. * @arg ADC_Channel_16: ADC Channel16 selected
  1028. * @arg ADC_Channel_17: ADC Channel17 selected
  1029. * @arg ADC_Channel_18: ADC Channel18 selected
  1030. * @param Rank: The rank in the injected group sequencer.
  1031. * This parameter must be between 1 to 4.
  1032. * @param ADC_SampleTime: The sample time value to be set for the selected channel.
  1033. * This parameter can be one of the following values:
  1034. * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
  1035. * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
  1036. * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
  1037. * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
  1038. * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
  1039. * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
  1040. * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
  1041. * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
  1042. * @retval None
  1043. */
  1044. void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
  1045. {
  1046. uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
  1047. /* Check the parameters */
  1048. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1049. assert_param(IS_ADC_CHANNEL(ADC_Channel));
  1050. assert_param(IS_ADC_INJECTED_RANK(Rank));
  1051. assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
  1052. /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
  1053. if (ADC_Channel > ADC_Channel_9)
  1054. {
  1055. /* Get the old register value */
  1056. tmpreg1 = ADCx->SMPR1;
  1057. /* Calculate the mask to clear */
  1058. tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
  1059. /* Clear the old sample time */
  1060. tmpreg1 &= ~tmpreg2;
  1061. /* Calculate the mask to set */
  1062. tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
  1063. /* Set the new sample time */
  1064. tmpreg1 |= tmpreg2;
  1065. /* Store the new register value */
  1066. ADCx->SMPR1 = tmpreg1;
  1067. }
  1068. else /* ADC_Channel include in ADC_Channel_[0..9] */
  1069. {
  1070. /* Get the old register value */
  1071. tmpreg1 = ADCx->SMPR2;
  1072. /* Calculate the mask to clear */
  1073. tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
  1074. /* Clear the old sample time */
  1075. tmpreg1 &= ~tmpreg2;
  1076. /* Calculate the mask to set */
  1077. tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
  1078. /* Set the new sample time */
  1079. tmpreg1 |= tmpreg2;
  1080. /* Store the new register value */
  1081. ADCx->SMPR2 = tmpreg1;
  1082. }
  1083. /* Rank configuration */
  1084. /* Get the old register value */
  1085. tmpreg1 = ADCx->JSQR;
  1086. /* Get JL value: Number = JL+1 */
  1087. tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
  1088. /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
  1089. tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
  1090. /* Clear the old JSQx bits for the selected rank */
  1091. tmpreg1 &= ~tmpreg2;
  1092. /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
  1093. tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
  1094. /* Set the JSQx bits for the selected rank */
  1095. tmpreg1 |= tmpreg2;
  1096. /* Store the new register value */
  1097. ADCx->JSQR = tmpreg1;
  1098. }
  1099. /**
  1100. * @brief Configures the sequencer length for injected channels
  1101. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1102. * @param Length: The sequencer length.
  1103. * This parameter must be a number between 1 to 4.
  1104. * @retval None
  1105. */
  1106. void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
  1107. {
  1108. uint32_t tmpreg1 = 0;
  1109. uint32_t tmpreg2 = 0;
  1110. /* Check the parameters */
  1111. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1112. assert_param(IS_ADC_INJECTED_LENGTH(Length));
  1113. /* Get the old register value */
  1114. tmpreg1 = ADCx->JSQR;
  1115. /* Clear the old injected sequence length JL bits */
  1116. tmpreg1 &= JSQR_JL_RESET;
  1117. /* Set the injected sequence length JL bits */
  1118. tmpreg2 = Length - 1;
  1119. tmpreg1 |= tmpreg2 << 20;
  1120. /* Store the new register value */
  1121. ADCx->JSQR = tmpreg1;
  1122. }
  1123. /**
  1124. * @brief Set the injected channels conversion value offset
  1125. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1126. * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
  1127. * This parameter can be one of the following values:
  1128. * @arg ADC_InjectedChannel_1: Injected Channel1 selected
  1129. * @arg ADC_InjectedChannel_2: Injected Channel2 selected
  1130. * @arg ADC_InjectedChannel_3: Injected Channel3 selected
  1131. * @arg ADC_InjectedChannel_4: Injected Channel4 selected
  1132. * @param Offset: the offset value for the selected ADC injected channel
  1133. * This parameter must be a 12bit value.
  1134. * @retval None
  1135. */
  1136. void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
  1137. {
  1138. __IO uint32_t tmp = 0;
  1139. /* Check the parameters */
  1140. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1141. assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
  1142. assert_param(IS_ADC_OFFSET(Offset));
  1143. tmp = (uint32_t)ADCx;
  1144. tmp += ADC_InjectedChannel;
  1145. /* Set the selected injected channel data offset */
  1146. *(__IO uint32_t *) tmp = (uint32_t)Offset;
  1147. }
  1148. /**
  1149. * @brief Configures the ADCx external trigger for injected channels conversion.
  1150. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1151. * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
  1152. * This parameter can be one of the following values:
  1153. * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
  1154. * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
  1155. * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
  1156. * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
  1157. * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
  1158. * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
  1159. * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
  1160. * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
  1161. * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
  1162. * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
  1163. * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
  1164. * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
  1165. * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
  1166. * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
  1167. * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
  1168. * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
  1169. * @retval None
  1170. */
  1171. void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
  1172. {
  1173. uint32_t tmpreg = 0;
  1174. /* Check the parameters */
  1175. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1176. assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
  1177. /* Get the old register value */
  1178. tmpreg = ADCx->CR2;
  1179. /* Clear the old external event selection for injected group */
  1180. tmpreg &= CR2_JEXTSEL_RESET;
  1181. /* Set the external event selection for injected group */
  1182. tmpreg |= ADC_ExternalTrigInjecConv;
  1183. /* Store the new register value */
  1184. ADCx->CR2 = tmpreg;
  1185. }
  1186. /**
  1187. * @brief Configures the ADCx external trigger edge for injected channels conversion.
  1188. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1189. * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
  1190. * to start injected conversion.
  1191. * This parameter can be one of the following values:
  1192. * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for
  1193. * injected conversion
  1194. * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
  1195. * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
  1196. * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising
  1197. * and falling edge
  1198. * @retval None
  1199. */
  1200. void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
  1201. {
  1202. uint32_t tmpreg = 0;
  1203. /* Check the parameters */
  1204. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1205. assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
  1206. /* Get the old register value */
  1207. tmpreg = ADCx->CR2;
  1208. /* Clear the old external trigger edge for injected group */
  1209. tmpreg &= CR2_JEXTEN_RESET;
  1210. /* Set the new external trigger edge for injected group */
  1211. tmpreg |= ADC_ExternalTrigInjecConvEdge;
  1212. /* Store the new register value */
  1213. ADCx->CR2 = tmpreg;
  1214. }
  1215. /**
  1216. * @brief Enables the selected ADC software start conversion of the injected channels.
  1217. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1218. * @retval None
  1219. */
  1220. void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
  1221. {
  1222. /* Check the parameters */
  1223. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1224. /* Enable the selected ADC conversion for injected group */
  1225. ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
  1226. }
  1227. /**
  1228. * @brief Gets the selected ADC Software start injected conversion Status.
  1229. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1230. * @retval The new state of ADC software start injected conversion (SET or RESET).
  1231. */
  1232. FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
  1233. {
  1234. FlagStatus bitstatus = RESET;
  1235. /* Check the parameters */
  1236. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1237. /* Check the status of JSWSTART bit */
  1238. if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
  1239. {
  1240. /* JSWSTART bit is set */
  1241. bitstatus = SET;
  1242. }
  1243. else
  1244. {
  1245. /* JSWSTART bit is reset */
  1246. bitstatus = RESET;
  1247. }
  1248. /* Return the JSWSTART bit status */
  1249. return bitstatus;
  1250. }
  1251. /**
  1252. * @brief Enables or disables the selected ADC automatic injected group
  1253. * conversion after regular one.
  1254. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1255. * @param NewState: new state of the selected ADC auto injected conversion
  1256. * This parameter can be: ENABLE or DISABLE.
  1257. * @retval None
  1258. */
  1259. void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  1260. {
  1261. /* Check the parameters */
  1262. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1263. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1264. if (NewState != DISABLE)
  1265. {
  1266. /* Enable the selected ADC automatic injected group conversion */
  1267. ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
  1268. }
  1269. else
  1270. {
  1271. /* Disable the selected ADC automatic injected group conversion */
  1272. ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
  1273. }
  1274. }
  1275. /**
  1276. * @brief Enables or disables the discontinuous mode for injected group
  1277. * channel for the specified ADC
  1278. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1279. * @param NewState: new state of the selected ADC discontinuous mode on injected
  1280. * group channel.
  1281. * This parameter can be: ENABLE or DISABLE.
  1282. * @retval None
  1283. */
  1284. void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
  1285. {
  1286. /* Check the parameters */
  1287. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1288. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1289. if (NewState != DISABLE)
  1290. {
  1291. /* Enable the selected ADC injected discontinuous mode */
  1292. ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
  1293. }
  1294. else
  1295. {
  1296. /* Disable the selected ADC injected discontinuous mode */
  1297. ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
  1298. }
  1299. }
  1300. /**
  1301. * @brief Returns the ADC injected channel conversion result
  1302. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1303. * @param ADC_InjectedChannel: the converted ADC injected channel.
  1304. * This parameter can be one of the following values:
  1305. * @arg ADC_InjectedChannel_1: Injected Channel1 selected
  1306. * @arg ADC_InjectedChannel_2: Injected Channel2 selected
  1307. * @arg ADC_InjectedChannel_3: Injected Channel3 selected
  1308. * @arg ADC_InjectedChannel_4: Injected Channel4 selected
  1309. * @retval The Data conversion value.
  1310. */
  1311. uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
  1312. {
  1313. __IO uint32_t tmp = 0;
  1314. /* Check the parameters */
  1315. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1316. assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
  1317. tmp = (uint32_t)ADCx;
  1318. tmp += ADC_InjectedChannel + JDR_OFFSET;
  1319. /* Returns the selected injected channel conversion data value */
  1320. return (uint16_t) (*(__IO uint32_t*) tmp);
  1321. }
  1322. /**
  1323. * @}
  1324. */
  1325. /** @defgroup ADC_Group7 Interrupts and flags management functions
  1326. * @brief Interrupts and flags management functions
  1327. *
  1328. @verbatim
  1329. ===============================================================================
  1330. Interrupts and flags management functions
  1331. ===============================================================================
  1332. This section provides functions allowing to configure the ADC Interrupts and
  1333. to get the status and clear flags and Interrupts pending bits.
  1334. Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into
  1335. 3 groups:
  1336. I. Flags and Interrupts for ADC regular channels
  1337. =================================================
  1338. Flags :
  1339. ----------
  1340. 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
  1341. 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending
  1342. on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:
  1343. ==> a regular CHANNEL conversion
  1344. ==> sequence of regular GROUP conversions .
  1345. 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL
  1346. conversion starts.
  1347. Interrupts :
  1348. ------------
  1349. 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event.
  1350. 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of
  1351. conversion event.
  1352. II. Flags and Interrupts for ADC Injected channels
  1353. =================================================
  1354. Flags :
  1355. ----------
  1356. 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at
  1357. the end of injected GROUP conversion
  1358. 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
  1359. injected GROUP conversion starts.
  1360. Interrupts :
  1361. ------------
  1362. 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of
  1363. conversion event.
  1364. III. General Flags and Interrupts for the ADC
  1365. =================================================
  1366. Flags :
  1367. ----------
  1368. 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
  1369. crosses the programmed thresholds values.
  1370. Interrupts :
  1371. ------------
  1372. 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
  1373. The user should identify which mode will be used in his application to manage
  1374. the ADC controller events: Polling mode or Interrupt mode.
  1375. In the Polling Mode it is advised to use the following functions:
  1376. - ADC_GetFlagStatus() : to check if flags events occur.
  1377. - ADC_ClearFlag() : to clear the flags events.
  1378. In the Interrupt Mode it is advised to use the following functions:
  1379. - ADC_ITConfig() : to enable or disable the interrupt source.
  1380. - ADC_GetITStatus() : to check if Interrupt occurs.
  1381. - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
  1382. (corresponding Flag).
  1383. @endverbatim
  1384. * @{
  1385. */
  1386. /**
  1387. * @brief Enables or disables the specified ADC interrupts.
  1388. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1389. * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
  1390. * This parameter can be one of the following values:
  1391. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1392. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1393. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1394. * @arg ADC_IT_OVR: Overrun interrupt enable
  1395. * @param NewState: new state of the specified ADC interrupts.
  1396. * This parameter can be: ENABLE or DISABLE.
  1397. * @retval None
  1398. */
  1399. void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
  1400. {
  1401. uint32_t itmask = 0;
  1402. /* Check the parameters */
  1403. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1404. assert_param(IS_FUNCTIONAL_STATE(NewState));
  1405. assert_param(IS_ADC_IT(ADC_IT));
  1406. /* Get the ADC IT index */
  1407. itmask = (uint8_t)ADC_IT;
  1408. itmask = (uint32_t)0x01 << itmask;
  1409. if (NewState != DISABLE)
  1410. {
  1411. /* Enable the selected ADC interrupts */
  1412. ADCx->CR1 |= itmask;
  1413. }
  1414. else
  1415. {
  1416. /* Disable the selected ADC interrupts */
  1417. ADCx->CR1 &= (~(uint32_t)itmask);
  1418. }
  1419. }
  1420. /**
  1421. * @brief Checks whether the specified ADC flag is set or not.
  1422. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1423. * @param ADC_FLAG: specifies the flag to check.
  1424. * This parameter can be one of the following values:
  1425. * @arg ADC_FLAG_AWD: Analog watchdog flag
  1426. * @arg ADC_FLAG_EOC: End of conversion flag
  1427. * @arg ADC_FLAG_JEOC: End of injected group conversion flag
  1428. * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
  1429. * @arg ADC_FLAG_STRT: Start of regular group conversion flag
  1430. * @arg ADC_FLAG_OVR: Overrun flag
  1431. * @retval The new state of ADC_FLAG (SET or RESET).
  1432. */
  1433. FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
  1434. {
  1435. FlagStatus bitstatus = RESET;
  1436. /* Check the parameters */
  1437. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1438. assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
  1439. /* Check the status of the specified ADC flag */
  1440. if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
  1441. {
  1442. /* ADC_FLAG is set */
  1443. bitstatus = SET;
  1444. }
  1445. else
  1446. {
  1447. /* ADC_FLAG is reset */
  1448. bitstatus = RESET;
  1449. }
  1450. /* Return the ADC_FLAG status */
  1451. return bitstatus;
  1452. }
  1453. /**
  1454. * @brief Clears the ADCx's pending flags.
  1455. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1456. * @param ADC_FLAG: specifies the flag to clear.
  1457. * This parameter can be any combination of the following values:
  1458. * @arg ADC_FLAG_AWD: Analog watchdog flag
  1459. * @arg ADC_FLAG_EOC: End of conversion flag
  1460. * @arg ADC_FLAG_JEOC: End of injected group conversion flag
  1461. * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
  1462. * @arg ADC_FLAG_STRT: Start of regular group conversion flag
  1463. * @arg ADC_FLAG_OVR: Overrun flag
  1464. * @retval None
  1465. */
  1466. void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
  1467. {
  1468. /* Check the parameters */
  1469. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1470. assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
  1471. /* Clear the selected ADC flags */
  1472. ADCx->SR = ~(uint32_t)ADC_FLAG;
  1473. }
  1474. /**
  1475. * @brief Checks whether the specified ADC interrupt has occurred or not.
  1476. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1477. * @param ADC_IT: specifies the ADC interrupt source to check.
  1478. * This parameter can be one of the following values:
  1479. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1480. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1481. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1482. * @arg ADC_IT_OVR: Overrun interrupt mask
  1483. * @retval The new state of ADC_IT (SET or RESET).
  1484. */
  1485. ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
  1486. {
  1487. ITStatus bitstatus = RESET;
  1488. uint32_t itmask = 0, enablestatus = 0;
  1489. /* Check the parameters */
  1490. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1491. assert_param(IS_ADC_IT(ADC_IT));
  1492. /* Get the ADC IT index */
  1493. itmask = ADC_IT >> 8;
  1494. /* Get the ADC_IT enable bit status */
  1495. enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
  1496. /* Check the status of the specified ADC interrupt */
  1497. if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
  1498. {
  1499. /* ADC_IT is set */
  1500. bitstatus = SET;
  1501. }
  1502. else
  1503. {
  1504. /* ADC_IT is reset */
  1505. bitstatus = RESET;
  1506. }
  1507. /* Return the ADC_IT status */
  1508. return bitstatus;
  1509. }
  1510. /**
  1511. * @brief Clears the ADCx's interrupt pending bits.
  1512. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
  1513. * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
  1514. * This parameter can be one of the following values:
  1515. * @arg ADC_IT_EOC: End of conversion interrupt mask
  1516. * @arg ADC_IT_AWD: Analog watchdog interrupt mask
  1517. * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
  1518. * @arg ADC_IT_OVR: Overrun interrupt mask
  1519. * @retval None
  1520. */
  1521. void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
  1522. {
  1523. uint8_t itmask = 0;
  1524. /* Check the parameters */
  1525. assert_param(IS_ADC_ALL_PERIPH(ADCx));
  1526. assert_param(IS_ADC_IT(ADC_IT));
  1527. /* Get the ADC IT index */
  1528. itmask = (uint8_t)(ADC_IT >> 8);
  1529. /* Clear the selected ADC interrupt pending bits */
  1530. ADCx->SR = ~(uint32_t)itmask;
  1531. }
  1532. /**
  1533. * @}
  1534. */
  1535. /**
  1536. * @}
  1537. */
  1538. /**
  1539. * @}
  1540. */
  1541. /**
  1542. * @}
  1543. */
  1544. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/