bt-67xx_universal_hw/projects/iar/stm32f407xG.icf

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08020000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__   = 0x2001FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_heap__   = 0x3000;
define symbol __ICFEDIT_size_anchor__  = 0xC;
define symbol __ICFEDIT_size_crc__  = 0x4;
/**** End of ICF editor section. ###ICF###*/

define symbol __region_RAM1_start__ = 0x10000000;
define symbol __region_RAM1_end__   = 0x1000FFFF;

define memory mem with size = 4G;
define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__ - __ICFEDIT_size_anchor__];
define region ANCHOR_region = mem:[from __ICFEDIT_region_ROM_end__ - __ICFEDIT_size_anchor__ - __ICFEDIT_size_crc__ size __ICFEDIT_size_anchor__];
define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
define region RAM1_region  = mem:[from __region_RAM1_start__   to __region_RAM1_end__];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

initialize by copy { readwrite, section .sram };
do not initialize  { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };

place in ROM_region   { readonly };
place in ANCHOR_region { section .anchorsection };
place in RAM_region   { readwrite,
                        block CSTACK, block HEAP };
place in RAM1_region  { section .sram };

place at address mem:__ICFEDIT_region_ROM_end__-3 { readonly section .checksum };