stm32f4xx_hash_sha1.c 9.3 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hash_sha1.c
  4. * @author MCD Application Team
  5. * @version V1.0.2
  6. * @date 05-March-2012
  7. * @brief This file provides high level functions to compute the HASH SHA1 and
  8. * HMAC SHA1 Digest of an input message.
  9. * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
  10. * peripheral.
  11. *
  12. * @verbatim
  13. *
  14. * ===================================================================
  15. * How to use this driver
  16. * ===================================================================
  17. * 1. Enable The HASH controller clock using
  18. * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
  19. *
  20. * 2. Calculate the HASH SHA1 Digest using HASH_SHA1() function.
  21. *
  22. * 3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
  23. *
  24. * @endverbatim
  25. *
  26. ******************************************************************************
  27. * @attention
  28. *
  29. * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  30. *
  31. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  32. * You may not use this file except in compliance with the License.
  33. * You may obtain a copy of the License at:
  34. *
  35. * http://www.st.com/software_license_agreement_liberty_v2
  36. *
  37. * Unless required by applicable law or agreed to in writing, software
  38. * distributed under the License is distributed on an "AS IS" BASIS,
  39. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  40. * See the License for the specific language governing permissions and
  41. * limitations under the License.
  42. *
  43. ******************************************************************************
  44. */
  45. /* Includes ------------------------------------------------------------------*/
  46. #include "stm32f4xx_hash.h"
  47. /** @addtogroup STM32F4xx_StdPeriph_Driver
  48. * @{
  49. */
  50. /** @defgroup HASH
  51. * @brief HASH driver modules
  52. * @{
  53. */
  54. /* Private typedef -----------------------------------------------------------*/
  55. /* Private define ------------------------------------------------------------*/
  56. #define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
  57. /* Private macro -------------------------------------------------------------*/
  58. /* Private variables ---------------------------------------------------------*/
  59. /* Private function prototypes -----------------------------------------------*/
  60. /* Private functions ---------------------------------------------------------*/
  61. /** @defgroup HASH_Private_Functions
  62. * @{
  63. */
  64. /** @defgroup HASH_Group6 High Level SHA1 functions
  65. * @brief High Level SHA1 Hash and HMAC functions
  66. *
  67. @verbatim
  68. ===============================================================================
  69. High Level SHA1 Hash and HMAC functions
  70. ===============================================================================
  71. @endverbatim
  72. * @{
  73. */
  74. /**
  75. * @brief Compute the HASH SHA1 digest.
  76. * @param Input: pointer to the Input buffer to be treated.
  77. * @param Ilen: length of the Input buffer.
  78. * @param Output: the returned digest
  79. * @retval An ErrorStatus enumeration value:
  80. * - SUCCESS: digest computation done
  81. * - ERROR: digest computation failed
  82. */
  83. ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
  84. {
  85. HASH_InitTypeDef SHA1_HASH_InitStructure;
  86. HASH_MsgDigest SHA1_MessageDigest;
  87. __IO uint16_t nbvalidbitsdata = 0;
  88. uint32_t i = 0;
  89. __IO uint32_t counter = 0;
  90. uint32_t busystatus = 0;
  91. ErrorStatus status = SUCCESS;
  92. uint32_t inputaddr = (uint32_t)Input;
  93. uint32_t outputaddr = (uint32_t)Output;
  94. /* Number of valid bits in last word of the Input data */
  95. nbvalidbitsdata = 8 * (Ilen % 4);
  96. /* HASH peripheral initialization */
  97. HASH_DeInit();
  98. /* HASH Configuration */
  99. SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
  100. SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
  101. SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
  102. HASH_Init(&SHA1_HASH_InitStructure);
  103. /* Configure the number of valid bits in last word of the data */
  104. HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
  105. /* Write the Input block in the IN FIFO */
  106. for(i=0; i<Ilen; i+=4)
  107. {
  108. HASH_DataIn(*(uint32_t*)inputaddr);
  109. inputaddr+=4;
  110. }
  111. /* Start the HASH processor */
  112. HASH_StartDigest();
  113. /* wait until the Busy flag is RESET */
  114. do
  115. {
  116. busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
  117. counter++;
  118. }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
  119. if (busystatus != RESET)
  120. {
  121. status = ERROR;
  122. }
  123. else
  124. {
  125. /* Read the message digest */
  126. HASH_GetDigest(&SHA1_MessageDigest);
  127. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
  128. outputaddr+=4;
  129. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
  130. outputaddr+=4;
  131. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
  132. outputaddr+=4;
  133. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
  134. outputaddr+=4;
  135. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
  136. }
  137. return status;
  138. }
  139. /**
  140. * @brief Compute the HMAC SHA1 digest.
  141. * @param Key: pointer to the Key used for HMAC.
  142. * @param Keylen: length of the Key used for HMAC.
  143. * @param Input: pointer to the Input buffer to be treated.
  144. * @param Ilen: length of the Input buffer.
  145. * @param Output: the returned digest
  146. * @retval An ErrorStatus enumeration value:
  147. * - SUCCESS: digest computation done
  148. * - ERROR: digest computation failed
  149. */
  150. ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
  151. uint32_t Ilen, uint8_t Output[20])
  152. {
  153. HASH_InitTypeDef SHA1_HASH_InitStructure;
  154. HASH_MsgDigest SHA1_MessageDigest;
  155. __IO uint16_t nbvalidbitsdata = 0;
  156. __IO uint16_t nbvalidbitskey = 0;
  157. uint32_t i = 0;
  158. __IO uint32_t counter = 0;
  159. uint32_t busystatus = 0;
  160. ErrorStatus status = SUCCESS;
  161. uint32_t keyaddr = (uint32_t)Key;
  162. uint32_t inputaddr = (uint32_t)Input;
  163. uint32_t outputaddr = (uint32_t)Output;
  164. /* Number of valid bits in last word of the Input data */
  165. nbvalidbitsdata = 8 * (Ilen % 4);
  166. /* Number of valid bits in last word of the Key */
  167. nbvalidbitskey = 8 * (Keylen % 4);
  168. /* HASH peripheral initialization */
  169. HASH_DeInit();
  170. /* HASH Configuration */
  171. SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
  172. SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
  173. SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
  174. if(Keylen > 64)
  175. {
  176. /* HMAC long Key */
  177. SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
  178. }
  179. else
  180. {
  181. /* HMAC short Key */
  182. SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
  183. }
  184. HASH_Init(&SHA1_HASH_InitStructure);
  185. /* Configure the number of valid bits in last word of the Key */
  186. HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
  187. /* Write the Key */
  188. for(i=0; i<Keylen; i+=4)
  189. {
  190. HASH_DataIn(*(uint32_t*)keyaddr);
  191. keyaddr+=4;
  192. }
  193. /* Start the HASH processor */
  194. HASH_StartDigest();
  195. /* wait until the Busy flag is RESET */
  196. do
  197. {
  198. busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
  199. counter++;
  200. }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
  201. if (busystatus != RESET)
  202. {
  203. status = ERROR;
  204. }
  205. else
  206. {
  207. /* Configure the number of valid bits in last word of the Input data */
  208. HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
  209. /* Write the Input block in the IN FIFO */
  210. for(i=0; i<Ilen; i+=4)
  211. {
  212. HASH_DataIn(*(uint32_t*)inputaddr);
  213. inputaddr+=4;
  214. }
  215. /* Start the HASH processor */
  216. HASH_StartDigest();
  217. /* wait until the Busy flag is RESET */
  218. counter =0;
  219. do
  220. {
  221. busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
  222. counter++;
  223. }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
  224. if (busystatus != RESET)
  225. {
  226. status = ERROR;
  227. }
  228. else
  229. {
  230. /* Configure the number of valid bits in last word of the Key */
  231. HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
  232. /* Write the Key */
  233. keyaddr = (uint32_t)Key;
  234. for(i=0; i<Keylen; i+=4)
  235. {
  236. HASH_DataIn(*(uint32_t*)keyaddr);
  237. keyaddr+=4;
  238. }
  239. /* Start the HASH processor */
  240. HASH_StartDigest();
  241. /* wait until the Busy flag is RESET */
  242. counter =0;
  243. do
  244. {
  245. busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
  246. counter++;
  247. }while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
  248. if (busystatus != RESET)
  249. {
  250. status = ERROR;
  251. }
  252. else
  253. {
  254. /* Read the message digest */
  255. HASH_GetDigest(&SHA1_MessageDigest);
  256. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
  257. outputaddr+=4;
  258. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
  259. outputaddr+=4;
  260. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
  261. outputaddr+=4;
  262. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
  263. outputaddr+=4;
  264. *(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
  265. }
  266. }
  267. }
  268. return status;
  269. }
  270. /**
  271. * @}
  272. */
  273. /**
  274. * @}
  275. */
  276. /**
  277. * @}
  278. */
  279. /**
  280. * @}
  281. */
  282. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/