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@@ -5,43 +5,43 @@ Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00008000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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- 1 .text 0000b688 08008000 08008000 00010000 2**3
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+ 1 .text 0000b5e8 08008000 08008000 00010000 2**3
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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- 2 .ARM 00000008 08013688 08013688 0001b688 2**2
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+ 2 .ARM 00000008 080135e8 080135e8 0001b5e8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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- 3 .init_array 00000004 08013690 08013690 0001b690 2**2
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+ 3 .init_array 00000004 080135f0 080135f0 0001b5f0 2**2
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CONTENTS, ALLOC, LOAD, DATA
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- 4 .fini_array 00000004 08013694 08013694 0001b694 2**2
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+ 4 .fini_array 00000004 080135f4 080135f4 0001b5f4 2**2
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CONTENTS, ALLOC, LOAD, DATA
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- 5 .data 00000118 20000000 08013698 00020000 2**2
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+ 5 .data 00000118 20000000 080135f8 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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- 6 .bss 0000c884 20000118 080137b0 00020118 2**2
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+ 6 .bss 0000c6c0 20000118 08013710 00020118 2**2
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ALLOC
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- 7 ._user_heap_stack 00000900 2000c99c 08020034 00020118 2**0
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+ 7 ._user_heap_stack 00000900 2000c7d8 0801fdd0 00020118 2**0
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ALLOC
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8 .settings 00004000 08004000 08004000 0000c000 2**0
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CONTENTS, ALLOC, LOAD, DATA
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9 .ARM.attributes 0000002f 00000000 00000000 00020118 2**0
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CONTENTS, READONLY
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- 10 .debug_info 00024c72 00000000 00000000 00020147 2**0
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+ 10 .debug_info 000248ba 00000000 00000000 00020147 2**0
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CONTENTS, READONLY, DEBUGGING
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- 11 .debug_abbrev 00007158 00000000 00000000 00044db9 2**0
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+ 11 .debug_abbrev 00007128 00000000 00000000 00044a01 2**0
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CONTENTS, READONLY, DEBUGGING
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- 12 .debug_loc 00011f69 00000000 00000000 0004bf11 2**0
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+ 12 .debug_loc 00011f49 00000000 00000000 0004bb29 2**0
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CONTENTS, READONLY, DEBUGGING
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- 13 .debug_aranges 000019c8 00000000 00000000 0005de80 2**3
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+ 13 .debug_aranges 000019b8 00000000 00000000 0005da78 2**3
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CONTENTS, READONLY, DEBUGGING
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- 14 .debug_ranges 00001d78 00000000 00000000 0005f848 2**3
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+ 14 .debug_ranges 00001d20 00000000 00000000 0005f430 2**3
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CONTENTS, READONLY, DEBUGGING
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- 15 .debug_macro 00017611 00000000 00000000 000615c0 2**0
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+ 15 .debug_macro 00017611 00000000 00000000 00061150 2**0
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CONTENTS, READONLY, DEBUGGING
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- 16 .debug_line 00013254 00000000 00000000 00078bd1 2**0
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+ 16 .debug_line 00013203 00000000 00000000 00078761 2**0
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CONTENTS, READONLY, DEBUGGING
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- 17 .debug_str 00071523 00000000 00000000 0008be25 2**0
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+ 17 .debug_str 0007145c 00000000 00000000 0008b964 2**0
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CONTENTS, READONLY, DEBUGGING
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- 18 .comment 00000030 00000000 00000000 000fd348 2**0
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+ 18 .comment 00000030 00000000 00000000 000fcdc0 2**0
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CONTENTS, READONLY
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- 19 .debug_frame 00003ec8 00000000 00000000 000fd378 2**2
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+ 19 .debug_frame 00003e9c 00000000 00000000 000fcdf0 2**2
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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@@ -92,7 +92,7 @@ Disassembly of section .text:
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800806a: f240 0300 movw r3, #0
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800806e: f2c0 0300 movt r3, #0
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8008072: b12b cbz r3, 8008080 <__do_global_dtors_aux+0x28>
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- 8008074: f243 6070 movw r0, #13936 ; 0x3670
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+ 8008074: f243 50d0 movw r0, #13776 ; 0x35d0
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8008078: f6c0 0001 movt r0, #2049 ; 0x801
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800807c: f3af 8000 nop.w
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8008080: 2301 movs r3, #1
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@@ -105,7 +105,7 @@ Disassembly of section .text:
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800808a: f240 0300 movw r3, #0
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800808e: f2c0 0300 movt r3, #0
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8008092: b14b cbz r3, 80080a8 <frame_dummy+0x20>
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- 8008094: f243 6070 movw r0, #13936 ; 0x3670
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+ 8008094: f243 50d0 movw r0, #13776 ; 0x35d0
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8008098: f240 111c movw r1, #284 ; 0x11c
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800809c: f6c0 0001 movt r0, #2049 ; 0x801
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80080a0: f2c2 0100 movt r1, #8192 ; 0x2000
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@@ -1764,8 +1764,8 @@ Disassembly of section .text:
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08009348 <__libc_init_array>:
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8009348: b570 push {r4, r5, r6, lr}
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- 800934a: f243 6690 movw r6, #13968 ; 0x3690
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- 800934e: f243 6590 movw r5, #13968 ; 0x3690
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+ 800934a: f243 56f0 movw r6, #13808 ; 0x35f0
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+ 800934e: f243 55f0 movw r5, #13808 ; 0x35f0
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8009352: f6c0 0601 movt r6, #2049 ; 0x801
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8009356: f6c0 0501 movt r5, #2049 ; 0x801
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800935a: 1b76 subs r6, r6, r5
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@@ -1778,12 +1778,12 @@ Disassembly of section .text:
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800936a: 4798 blx r3
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800936c: 42a6 cmp r6, r4
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800936e: d1f9 bne.n 8009364 <__libc_init_array+0x1c>
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- 8009370: f243 6694 movw r6, #13972 ; 0x3694
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- 8009374: f243 6590 movw r5, #13968 ; 0x3690
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+ 8009370: f243 56f4 movw r6, #13812 ; 0x35f4
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+ 8009374: f243 55f0 movw r5, #13808 ; 0x35f0
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8009378: f6c0 0601 movt r6, #2049 ; 0x801
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800937c: f6c0 0501 movt r5, #2049 ; 0x801
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8009380: 1b76 subs r6, r6, r5
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- 8009382: f00a f975 bl 8013670 <_init>
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+ 8009382: f00a f925 bl 80135d0 <_init>
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8009386: 10b6 asrs r6, r6, #2
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8009388: d008 beq.n 800939c <__libc_init_array+0x54>
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800938a: 3d04 subs r5, #4
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@@ -5310,7 +5310,7 @@ dhcp_discover(struct netif *netif)
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800a4d6: 4630 mov r0, r6
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800a4d8: bd7c pop {r2, r3, r4, r5, r6, pc}
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800a4da: bf00 nop
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- 800a4dc: 0801187c .word 0x0801187c
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+ 800a4dc: 080117f4 .word 0x080117f4
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0800a4e0 <dhcp_rebind>:
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*
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@@ -5417,7 +5417,7 @@ dhcp_rebind(struct netif *netif)
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}
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800a55c: 4630 mov r0, r6
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800a55e: bd7c pop {r2, r3, r4, r5, r6, pc}
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- 800a560: 0801187c .word 0x0801187c
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+ 800a560: 080117f4 .word 0x080117f4
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0800a564 <dhcp_reboot>:
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*
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@@ -5533,7 +5533,7 @@ dhcp_reboot(struct netif *netif)
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800a5fa: 4630 mov r0, r6
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800a5fc: bd7c pop {r2, r3, r4, r5, r6, pc}
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800a5fe: bf00 nop
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- 800a600: 0801187c .word 0x0801187c
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+ 800a600: 080117f4 .word 0x080117f4
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0800a604 <dhcp_select>:
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* @param netif the netif under DHCP control
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@@ -5690,7 +5690,7 @@ dhcp_select(struct netif *netif)
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800a6de: 4630 mov r0, r6
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800a6e0: bd7c pop {r2, r3, r4, r5, r6, pc}
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800a6e2: bf00 nop
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- 800a6e4: 0801187c .word 0x0801187c
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+ 800a6e4: 080117f4 .word 0x080117f4
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0800a6e8 <dhcp_check>:
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*
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@@ -7019,7 +7019,7 @@ free_pbuf_and_return:
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800ab88: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
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800ab8c: 20006dd0 .word 0x20006dd0
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800ab90: 20006ddc .word 0x20006ddc
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- 800ab94: 08011880 .word 0x08011880
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+ 800ab94: 080117f8 .word 0x080117f8
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0800ab98 <dhcp_arp_reply>:
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*
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@@ -7123,7 +7123,7 @@ void dhcp_arp_reply(struct netif *netif, ip_addr_t *addr)
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}
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800ac10: bd3e pop {r1, r2, r3, r4, r5, pc}
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800ac12: bf00 nop
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- 800ac14: 0801187c .word 0x0801187c
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+ 800ac14: 080117f4 .word 0x080117f4
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0800ac18 <dhcp_renew>:
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*
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@@ -7453,7 +7453,7 @@ dhcp_release(struct netif *netif)
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800ad96: 4630 mov r0, r6
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800ad98: bd7c pop {r2, r3, r4, r5, r6, pc}
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800ad9a: bf00 nop
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- 800ad9c: 08011880 .word 0x08011880
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+ 800ad9c: 080117f8 .word 0x080117f8
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0800ada0 <dhcp_fine_tmr>:
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* A DHCP server is expected to respond within a short period of time.
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@@ -7892,7 +7892,7 @@ dhcp_start(struct netif *netif)
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800af0a: b240 sxtb r0, r0
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800af0c: bd38 pop {r3, r4, r5, pc}
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800af0e: bf00 nop
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- 800af10: 08011880 .word 0x08011880
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+ 800af10: 080117f8 .word 0x080117f8
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800af14: 0800a7cd .word 0x0800a7cd
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0800af18 <lwip_init>:
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@@ -8851,10 +8851,10 @@ memp_init(void)
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800b268: bdf0 pop {r4, r5, r6, r7, pc}
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800b26a: bf00 nop
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800b26c: 20008220 .word 0x20008220
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- 800b270: 08011830 .word 0x08011830
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+ 800b270: 080117a8 .word 0x080117a8
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800b274: 20000143 .word 0x20000143
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800b278: 20006b4c .word 0x20006b4c
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- 800b27c: 08011844 .word 0x08011844
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+ 800b27c: 080117bc .word 0x080117bc
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0800b280 <memp_malloc>:
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#endif
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@@ -10964,7 +10964,7 @@ again:
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800b890: bd70 pop {r4, r5, r6, pc}
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800b892: bf00 nop
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800b894: 20000110 .word 0x20000110
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- 800b898: 08011858 .word 0x08011858
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+ 800b898: 080117d0 .word 0x080117d0
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0800b89c <tcp_init>:
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/**
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@@ -11138,7 +11138,7 @@ tcp_bind(struct tcp_pcb *pcb, ip_addr_t *ipaddr, u16_t port)
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800b902: b240 sxtb r0, r0
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800b904: bdf8 pop {r3, r4, r5, r6, r7, pc}
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800b906: bf00 nop
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- 800b908: 08011858 .word 0x08011858
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+ 800b908: 080117d0 .word 0x080117d0
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800b90c: 2000834c .word 0x2000834c
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0800b910 <tcp_listen_with_backlog>:
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@@ -12359,8 +12359,8 @@ tcp_slowtmr_start:
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800bd18: 20008340 .word 0x20008340
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800bd1c: 20006b7d .word 0x20006b7d
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800bd20: 2000833c .word 0x2000833c
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- 800bd24: 08011875 .word 0x08011875
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- 800bd28: 08011868 .word 0x08011868
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+ 800bd24: 080117ed .word 0x080117ed
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+ 800bd28: 080117e0 .word 0x080117e0
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800bd2c: 000124f8 .word 0x000124f8
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800bd30: 20008350 .word 0x20008350
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800bd34: 20008338 .word 0x20008338
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@@ -19773,7 +19773,7 @@ void sys_timeouts_init(void)
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#if NO_SYS
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/* Initialise timestamp for sys_check_timeouts */
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timeouts_last_time = sys_now();
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- 800dbaa: f003 fa09 bl 8010fc0 <sys_now>
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+ 800dbaa: f003 f9c5 bl 8010f38 <sys_now>
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800dbae: 4b05 ldr r3, [pc, #20] ; (800dbc4 <sys_timeouts_init+0x4c>)
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800dbb0: 6018 str r0, [r3, #0]
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800dbb2: bd08 pop {r3, pc}
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@@ -20003,7 +20003,7 @@ sys_check_timeouts(void)
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u32_t now;
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now = sys_now();
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- 800dcae: f003 f987 bl 8010fc0 <sys_now>
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+ 800dcae: f003 f943 bl 8010f38 <sys_now>
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/* this cares for wraparounds */
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diff = now - timeouts_last_time;
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800dcb2: 4b0f ldr r3, [pc, #60] ; (800dcf0 <sys_check_timeouts+0x4c>)
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@@ -25645,8 +25645,8 @@ etharp_request(struct netif *netif, ip_addr_t *ipaddr)
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800efd6: b260 sxtb r0, r4
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800efd8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
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800efdc: 20008220 .word 0x20008220
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- 800efe0: 0801188a .word 0x0801188a
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- 800efe4: 08011884 .word 0x08011884
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+ 800efe0: 08011802 .word 0x08011802
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+ 800efe4: 080117fc .word 0x080117fc
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0800efe8 <etharp_query>:
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* - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
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@@ -26319,7 +26319,7 @@ etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
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800f244: 20008220 .word 0x20008220
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800f248: 20006bc2 .word 0x20006bc2
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800f24c: 20006bc4 .word 0x20006bc4
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- 800f250: 08011884 .word 0x08011884
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+ 800f250: 080117fc .word 0x080117fc
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0800f254 <ethernet_input>:
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* @param p the recevied packet, p->payload pointing to the ethernet header
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@@ -26843,7 +26843,7 @@ free_and_return:
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800f468: b007 add sp, #28
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800f46a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
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800f46e: bf00 nop
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- 800f470: 08011884 .word 0x08011884
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+ 800f470: 080117fc .word 0x080117fc
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800f474: 20008220 .word 0x20008220
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800f478: 20006bc4 .word 0x20006bc4
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@@ -26917,13 +26917,13 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
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/* Prepare transmit descriptors to give to DMA*/
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ETH_Prepare_Transmit_Descriptors(framelength);
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800f49e: b2a8 uxth r0, r5
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- 800f4a0: f001 f988 bl 80107b4 <ETH_Prepare_Transmit_Descriptors>
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+ 800f4a0: f001 f944 bl 801072c <ETH_Prepare_Transmit_Descriptors>
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return ERR_OK;
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}
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800f4a4: 4620 mov r0, r4
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800f4a6: bd70 pop {r4, r5, r6, pc}
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- 800f4a8: 20008cc0 .word 0x20008cc0
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+ 800f4a8: 20008afc .word 0x20008afc
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0800f4ac <ethernetif_input>:
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* the appropriate input function is called.
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@@ -26941,7 +26941,7 @@ err_t ethernetif_input(struct netif *netif)
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/* get received frame */
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frame = ETH_Get_Received_Frame();
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800f4b2: a801 add r0, sp, #4
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- 800f4b4: f001 f964 bl 8010780 <ETH_Get_Received_Frame>
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+ 800f4b4: f001 f920 bl 80106f8 <ETH_Get_Received_Frame>
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = frame.length;
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buffer = (u8 *)frame.buffer;
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@@ -27129,7 +27129,7 @@ err_t ethernetif_input(struct netif *netif)
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800f538: b260 sxtb r0, r4
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800f53a: b004 add sp, #16
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800f53c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
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- 800f540: 2000ab2c .word 0x2000ab2c
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+ 800f540: 2000a968 .word 0x2000a968
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800f544: 40029000 .word 0x40029000
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0800f548 <ethernetif_init>:
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@@ -27206,7 +27206,7 @@ err_t ethernetif_init(struct netif *netif)
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SETTINGS_GetMac(mac);
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|
800f568: 4668 mov r0, sp
|
|
|
- 800f56a: f000 fa8d bl 800fa88 <SETTINGS_GetMac>
|
|
|
+ 800f56a: f000 fa4b bl 800fa04 <SETTINGS_GetMac>
|
|
|
|
|
|
netif->hwaddr[0] = mac[0];
|
|
|
800f56e: f89d 3000 ldrb.w r3, [sp]
|
|
|
@@ -27240,7 +27240,7 @@ err_t ethernetif_init(struct netif *netif)
|
|
|
/* initialize MAC address in ethernet MAC */
|
|
|
ETH_MACAddressConfig(ETH_MAC_Address0, netif->hwaddr);
|
|
|
800f5a2: 2000 movs r0, #0
|
|
|
- 800f5a4: f001 f8d4 bl 8010750 <ETH_MACAddressConfig>
|
|
|
+ 800f5a4: f001 f890 bl 80106c8 <ETH_MACAddressConfig>
|
|
|
|
|
|
/* maximum transfer unit */
|
|
|
netif->mtu = 1500;
|
|
|
@@ -27258,13 +27258,13 @@ err_t ethernetif_init(struct netif *netif)
|
|
|
800f5b4: 480c ldr r0, [pc, #48] ; (800f5e8 <ethernetif_init+0xa0>)
|
|
|
800f5b6: 490e ldr r1, [pc, #56] ; (800f5f0 <ethernetif_init+0xa8>)
|
|
|
800f5b8: 2205 movs r2, #5
|
|
|
- 800f5ba: f001 f9bf bl 801093c <ETH_DMATxDescChainInit>
|
|
|
+ 800f5ba: f001 f97b bl 80108b4 <ETH_DMATxDescChainInit>
|
|
|
/* Initialize Rx Descriptors list: Chain Mode */
|
|
|
ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
|
|
|
800f5be: 480d ldr r0, [pc, #52] ; (800f5f4 <ethernetif_init+0xac>)
|
|
|
800f5c0: 490d ldr r1, [pc, #52] ; (800f5f8 <ethernetif_init+0xb0>)
|
|
|
800f5c2: 2205 movs r2, #5
|
|
|
- 800f5c4: f001 f950 bl 8010868 <ETH_DMARxDescChainInit>
|
|
|
+ 800f5c4: f001 f90c bl 80107e0 <ETH_DMARxDescChainInit>
|
|
|
|
|
|
#ifdef CHECKSUM_BY_HARDWARE
|
|
|
/* Enable the TCP, UDP and ICMP checksum insertion for the Tx frames */
|
|
|
@@ -27283,7 +27283,7 @@ err_t ethernetif_init(struct netif *netif)
|
|
|
800f5d2: 3401 adds r4, #1
|
|
|
{
|
|
|
ETH_DMATxDescChecksumInsertionConfig(&DMATxDscrTab[i], ETH_DMATxDesc_ChecksumTCPUDPICMPFull);
|
|
|
- 800f5d4: f001 f9d4 bl 8010980 <ETH_DMATxDescChecksumInsertionConfig>
|
|
|
+ 800f5d4: f001 f990 bl 80108f8 <ETH_DMATxDescChecksumInsertionConfig>
|
|
|
/* Initialize Rx Descriptors list: Chain Mode */
|
|
|
ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
|
|
|
|
|
|
@@ -27298,7 +27298,7 @@ err_t ethernetif_init(struct netif *netif)
|
|
|
|
|
|
/* Enable MAC and DMA transmission and reception */
|
|
|
ETH_Start();
|
|
|
- 800f5dc: f001 fa10 bl 8010a00 <ETH_Start>
|
|
|
+ 800f5dc: f001 f9cc bl 8010978 <ETH_Start>
|
|
|
|
|
|
/* initialize the hardware */
|
|
|
low_level_init(netif);
|
|
|
@@ -27308,11 +27308,11 @@ err_t ethernetif_init(struct netif *netif)
|
|
|
800f5e0: 2000 movs r0, #0
|
|
|
800f5e2: bd3e pop {r1, r2, r3, r4, r5, pc}
|
|
|
800f5e4: 0800f151 .word 0x0800f151
|
|
|
- 800f5e8: 20008cc4 .word 0x20008cc4
|
|
|
+ 800f5e8: 20008b00 .word 0x20008b00
|
|
|
800f5ec: 0800f47d .word 0x0800f47d
|
|
|
- 800f5f0: 2000abd0 .word 0x2000abd0
|
|
|
- 800f5f4: 2000ab30 .word 0x2000ab30
|
|
|
- 800f5f8: 20008d64 .word 0x20008d64
|
|
|
+ 800f5f0: 2000aa0c .word 0x2000aa0c
|
|
|
+ 800f5f4: 2000a96c .word 0x2000a96c
|
|
|
+ 800f5f8: 20008ba0 .word 0x20008ba0
|
|
|
|
|
|
0800f5fc <CRC_Init>:
|
|
|
/**
|
|
|
@@ -27879,14 +27879,14 @@ void LED_Blinky_Green(void)
|
|
|
*/
|
|
|
void SETTINGS_SetBootParamsDef(void)
|
|
|
{
|
|
|
- sSettings.bootParams.loadMode = 1;
|
|
|
+ sSettings.bootParams.loadMode = 0;
|
|
|
800f7fc: 4b02 ldr r3, [pc, #8] ; (800f808 <SETTINGS_SetBootParamsDef+0xc>)
|
|
|
- 800f7fe: 2201 movs r2, #1
|
|
|
+ 800f7fe: 2200 movs r2, #0
|
|
|
800f800: 701a strb r2, [r3, #0]
|
|
|
sSettings.bootParams.bootTry = 0;
|
|
|
- 800f802: 2200 movs r2, #0
|
|
|
- 800f804: 705a strb r2, [r3, #1]
|
|
|
- 800f806: 4770 bx lr
|
|
|
+ 800f802: 705a strb r2, [r3, #1]
|
|
|
+ 800f804: 4770 bx lr
|
|
|
+ 800f806: bf00 nop
|
|
|
800f808: 2000838c .word 0x2000838c
|
|
|
|
|
|
0800f80c <SETTINGS_SetWebParamsDef>:
|
|
|
@@ -27904,20 +27904,20 @@ void SETTINGS_SetWebParamsDef(void)
|
|
|
800f814: f7fa f804 bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sWebParams.gate, "192.168.1.1");
|
|
|
800f818: 4908 ldr r1, [pc, #32] ; (800f83c <SETTINGS_SetWebParamsDef+0x30>)
|
|
|
- 800f81a: f104 000f add.w r0, r4, #15
|
|
|
+ 800f81a: f104 0010 add.w r0, r4, #16
|
|
|
800f81e: f7f9 ffff bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sWebParams.mask, "255.255.255.0");
|
|
|
- 800f822: f104 001e add.w r0, r4, #30
|
|
|
+ 800f822: f104 0020 add.w r0, r4, #32
|
|
|
800f826: 4906 ldr r1, [pc, #24] ; (800f840 <SETTINGS_SetWebParamsDef+0x34>)
|
|
|
800f828: f7f9 fffa bl 8009820 <strcpy>
|
|
|
sSettings.sWebParams.dhcpEnable = 1;
|
|
|
800f82c: 2201 movs r2, #1
|
|
|
- 800f82e: f884 202d strb.w r2, [r4, #45] ; 0x2d
|
|
|
+ 800f82e: f884 2030 strb.w r2, [r4, #48] ; 0x30
|
|
|
800f832: bd10 pop {r4, pc}
|
|
|
800f834: 2000838e .word 0x2000838e
|
|
|
- 800f838: 08011890 .word 0x08011890
|
|
|
- 800f83c: 0801189c .word 0x0801189c
|
|
|
- 800f840: 080118a8 .word 0x080118a8
|
|
|
+ 800f838: 08011808 .word 0x08011808
|
|
|
+ 800f83c: 08011814 .word 0x08011814
|
|
|
+ 800f840: 08011820 .word 0x08011820
|
|
|
|
|
|
0800f844 <SETTINGS_SetTempWebParamsDef>:
|
|
|
|
|
|
@@ -27934,8941 +27934,8837 @@ void SETTINGS_SetTempWebParamsDef(void)
|
|
|
800f84c: f7f9 ffe8 bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sWebTempParams.gate, "192.168.1.1");
|
|
|
800f850: 4908 ldr r1, [pc, #32] ; (800f874 <SETTINGS_SetTempWebParamsDef+0x30>)
|
|
|
- 800f852: f104 000f add.w r0, r4, #15
|
|
|
+ 800f852: f104 0010 add.w r0, r4, #16
|
|
|
800f856: f7f9 ffe3 bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sWebTempParams.mask, "255.255.255.0");
|
|
|
- 800f85a: f104 001e add.w r0, r4, #30
|
|
|
+ 800f85a: f104 0020 add.w r0, r4, #32
|
|
|
800f85e: 4906 ldr r1, [pc, #24] ; (800f878 <SETTINGS_SetTempWebParamsDef+0x34>)
|
|
|
800f860: f7f9 ffde bl 8009820 <strcpy>
|
|
|
sSettings.sWebTempParams.dhcpEnable = 1;
|
|
|
800f864: 2201 movs r2, #1
|
|
|
- 800f866: f884 202d strb.w r2, [r4, #45] ; 0x2d
|
|
|
+ 800f866: f884 2030 strb.w r2, [r4, #48] ; 0x30
|
|
|
800f86a: bd10 pop {r4, pc}
|
|
|
- 800f86c: 200083bc .word 0x200083bc
|
|
|
- 800f870: 08011890 .word 0x08011890
|
|
|
- 800f874: 0801189c .word 0x0801189c
|
|
|
- 800f878: 080118a8 .word 0x080118a8
|
|
|
+ 800f86c: 200083bf .word 0x200083bf
|
|
|
+ 800f870: 08011808 .word 0x08011808
|
|
|
+ 800f874: 08011814 .word 0x08011814
|
|
|
+ 800f878: 08011820 .word 0x08011820
|
|
|
|
|
|
-0800f87c <SETTINGS_SetSnmpDef>:
|
|
|
-
|
|
|
-/**
|
|
|
- * @brief Установить параметры SNMP по умолчанию
|
|
|
- */
|
|
|
-void SETTINGS_SetSnmpDef(void)
|
|
|
-{
|
|
|
- 800f87c: b570 push {r4, r5, r6, lr}
|
|
|
- strcpy(sSettings.sSnmp.sysDescr, "");
|
|
|
- 800f87e: 4c19 ldr r4, [pc, #100] ; (800f8e4 <SETTINGS_SetSnmpDef+0x68>)
|
|
|
- 800f880: 4d19 ldr r5, [pc, #100] ; (800f8e8 <SETTINGS_SetSnmpDef+0x6c>)
|
|
|
- strcpy(sSettings.sSnmp.readCommunity, "public");
|
|
|
- 800f882: 4e1a ldr r6, [pc, #104] ; (800f8ec <SETTINGS_SetSnmpDef+0x70>)
|
|
|
-/**
|
|
|
- * @brief Установить параметры SNMP по умолчанию
|
|
|
- */
|
|
|
-void SETTINGS_SetSnmpDef(void)
|
|
|
-{
|
|
|
- strcpy(sSettings.sSnmp.sysDescr, "");
|
|
|
- 800f884: 4629 mov r1, r5
|
|
|
- 800f886: 4620 mov r0, r4
|
|
|
- 800f888: f7f9 ffca bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.readCommunity, "public");
|
|
|
- 800f88c: 4631 mov r1, r6
|
|
|
- 800f88e: f104 00a0 add.w r0, r4, #160 ; 0xa0
|
|
|
- 800f892: f7f9 ffc5 bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.writeCommunity, "public");
|
|
|
- 800f896: 4631 mov r1, r6
|
|
|
- 800f898: f104 00b4 add.w r0, r4, #180 ; 0xb4
|
|
|
- 800f89c: f7f9 ffc0 bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.sysContact, "");
|
|
|
- 800f8a0: 4629 mov r1, r5
|
|
|
- 800f8a2: f104 00c8 add.w r0, r4, #200 ; 0xc8
|
|
|
- 800f8a6: f7f9 ffbb bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.sysName, "BT-6701");
|
|
|
- 800f8aa: f104 00fa add.w r0, r4, #250 ; 0xfa
|
|
|
- 800f8ae: 4910 ldr r1, [pc, #64] ; (800f8f0 <SETTINGS_SetSnmpDef+0x74>)
|
|
|
- 800f8b0: f7f9 ffb6 bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.sysLocation, "");
|
|
|
- 800f8b4: 4629 mov r1, r5
|
|
|
- strcpy(sSettings.sSnmp.managerIP, "0.0.0.0");
|
|
|
- 800f8b6: 4d0f ldr r5, [pc, #60] ; (800f8f4 <SETTINGS_SetSnmpDef+0x78>)
|
|
|
- strcpy(sSettings.sSnmp.sysDescr, "");
|
|
|
- strcpy(sSettings.sSnmp.readCommunity, "public");
|
|
|
- strcpy(sSettings.sSnmp.writeCommunity, "public");
|
|
|
- strcpy(sSettings.sSnmp.sysContact, "");
|
|
|
- strcpy(sSettings.sSnmp.sysName, "BT-6701");
|
|
|
- strcpy(sSettings.sSnmp.sysLocation, "");
|
|
|
- 800f8b8: f504 7087 add.w r0, r4, #270 ; 0x10e
|
|
|
- 800f8bc: f7f9 ffb0 bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.managerIP, "0.0.0.0");
|
|
|
- 800f8c0: 4629 mov r1, r5
|
|
|
- 800f8c2: f504 70be add.w r0, r4, #380 ; 0x17c
|
|
|
- 800f8c6: f7f9 ffab bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.managerIP2, "0.0.0.0");
|
|
|
- 800f8ca: 4629 mov r1, r5
|
|
|
- 800f8cc: f504 70c8 add.w r0, r4, #400 ; 0x190
|
|
|
- 800f8d0: f7f9 ffa6 bl 8009820 <strcpy>
|
|
|
- strcpy(sSettings.sSnmp.managerIP3, "0.0.0.0");
|
|
|
- 800f8d4: f504 70d2 add.w r0, r4, #420 ; 0x1a4
|
|
|
- 800f8d8: 4629 mov r1, r5
|
|
|
-}
|
|
|
- 800f8da: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
|
|
|
- strcpy(sSettings.sSnmp.sysContact, "");
|
|
|
- strcpy(sSettings.sSnmp.sysName, "BT-6701");
|
|
|
- strcpy(sSettings.sSnmp.sysLocation, "");
|
|
|
- strcpy(sSettings.sSnmp.managerIP, "0.0.0.0");
|
|
|
- strcpy(sSettings.sSnmp.managerIP2, "0.0.0.0");
|
|
|
- strcpy(sSettings.sSnmp.managerIP3, "0.0.0.0");
|
|
|
- 800f8de: f7f9 bf9f b.w 8009820 <strcpy>
|
|
|
- 800f8e2: bf00 nop
|
|
|
- 800f8e4: 200083ea .word 0x200083ea
|
|
|
- 800f8e8: 0801365a .word 0x0801365a
|
|
|
- 800f8ec: 080118b6 .word 0x080118b6
|
|
|
- 800f8f0: 080118bd .word 0x080118bd
|
|
|
- 800f8f4: 080118c5 .word 0x080118c5
|
|
|
-
|
|
|
-0800f8f8 <SETTINGS_SetInfoDef>:
|
|
|
+0800f87c <SETTINGS_SetInfoDef>:
|
|
|
|
|
|
/**
|
|
|
* @brief Установить Информацию об устройстве по умолчанию
|
|
|
*/
|
|
|
void SETTINGS_SetInfoDef(void)
|
|
|
{
|
|
|
- 800f8f8: b510 push {r4, lr}
|
|
|
+ 800f87c: b510 push {r4, lr}
|
|
|
strcpy(sSettings.sInfo.productionData, "09.10.2015");
|
|
|
- 800f8fa: 4c0b ldr r4, [pc, #44] ; (800f928 <SETTINGS_SetInfoDef+0x30>)
|
|
|
- 800f8fc: 490b ldr r1, [pc, #44] ; (800f92c <SETTINGS_SetInfoDef+0x34>)
|
|
|
- 800f8fe: 4620 mov r0, r4
|
|
|
- 800f900: f7f9 ff8e bl 8009820 <strcpy>
|
|
|
+ 800f87e: 4c0b ldr r4, [pc, #44] ; (800f8ac <SETTINGS_SetInfoDef+0x30>)
|
|
|
+ 800f880: 490b ldr r1, [pc, #44] ; (800f8b0 <SETTINGS_SetInfoDef+0x34>)
|
|
|
+ 800f882: 4620 mov r0, r4
|
|
|
+ 800f884: f7f9 ffcc bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sInfo.mac, DEVICE_MAC);
|
|
|
- 800f904: f104 0028 add.w r0, r4, #40 ; 0x28
|
|
|
- 800f908: 4909 ldr r1, [pc, #36] ; (800f930 <SETTINGS_SetInfoDef+0x38>)
|
|
|
- 800f90a: f7f9 ff89 bl 8009820 <strcpy>
|
|
|
+ 800f888: f104 0028 add.w r0, r4, #40 ; 0x28
|
|
|
+ 800f88c: 4909 ldr r1, [pc, #36] ; (800f8b4 <SETTINGS_SetInfoDef+0x38>)
|
|
|
+ 800f88e: f7f9 ffc7 bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sInfo.serialNumber, "KN-03-00003");
|
|
|
- 800f90e: f104 003a add.w r0, r4, #58 ; 0x3a
|
|
|
- 800f912: 4908 ldr r1, [pc, #32] ; (800f934 <SETTINGS_SetInfoDef+0x3c>)
|
|
|
- 800f914: f7f9 ff84 bl 8009820 <strcpy>
|
|
|
+ 800f892: f104 003a add.w r0, r4, #58 ; 0x3a
|
|
|
+ 800f896: 4908 ldr r1, [pc, #32] ; (800f8b8 <SETTINGS_SetInfoDef+0x3c>)
|
|
|
+ 800f898: f7f9 ffc2 bl 8009820 <strcpy>
|
|
|
strcpy(sSettings.sInfo.comments, "");
|
|
|
- 800f918: 4907 ldr r1, [pc, #28] ; (800f938 <SETTINGS_SetInfoDef+0x40>)
|
|
|
- 800f91a: f104 004a add.w r0, r4, #74 ; 0x4a
|
|
|
+ 800f89c: 4907 ldr r1, [pc, #28] ; (800f8bc <SETTINGS_SetInfoDef+0x40>)
|
|
|
+ 800f89e: f104 004a add.w r0, r4, #74 ; 0x4a
|
|
|
}
|
|
|
- 800f91e: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
+ 800f8a2: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
void SETTINGS_SetInfoDef(void)
|
|
|
{
|
|
|
strcpy(sSettings.sInfo.productionData, "09.10.2015");
|
|
|
strcpy(sSettings.sInfo.mac, DEVICE_MAC);
|
|
|
strcpy(sSettings.sInfo.serialNumber, "KN-03-00003");
|
|
|
strcpy(sSettings.sInfo.comments, "");
|
|
|
- 800f922: f7f9 bf7d b.w 8009820 <strcpy>
|
|
|
- 800f926: bf00 nop
|
|
|
- 800f928: 200085a2 .word 0x200085a2
|
|
|
- 800f92c: 080118cd .word 0x080118cd
|
|
|
- 800f930: 080118d8 .word 0x080118d8
|
|
|
- 800f934: 080118ea .word 0x080118ea
|
|
|
- 800f938: 0801365a .word 0x0801365a
|
|
|
-
|
|
|
-0800f93c <SETTINGS_ReadFromFlash>:
|
|
|
+ 800f8a6: f7f9 bfbb b.w 8009820 <strcpy>
|
|
|
+ 800f8aa: bf00 nop
|
|
|
+ 800f8ac: 200083f0 .word 0x200083f0
|
|
|
+ 800f8b0: 0801182e .word 0x0801182e
|
|
|
+ 800f8b4: 08011839 .word 0x08011839
|
|
|
+ 800f8b8: 0801184b .word 0x0801184b
|
|
|
+ 800f8bc: 080135ba .word 0x080135ba
|
|
|
+
|
|
|
+0800f8c0 <SETTINGS_ReadFromFlash>:
|
|
|
*/
|
|
|
void SETTINGS_ReadFromFlash(uint8_t *data, uint32_t size)
|
|
|
{
|
|
|
uint32_t baseAddress = SETTINGS_SECTOR;
|
|
|
|
|
|
for (uint32_t i = 0; i < size; i++)
|
|
|
- 800f93c: 2300 movs r3, #0
|
|
|
- 800f93e: e006 b.n 800f94e <SETTINGS_ReadFromFlash+0x12>
|
|
|
+ 800f8c0: 2300 movs r3, #0
|
|
|
+ 800f8c2: e006 b.n 800f8d2 <SETTINGS_ReadFromFlash+0x12>
|
|
|
*data++ = (*(uint32_t*)baseAddress++);;
|
|
|
- 800f940: f103 6200 add.w r2, r3, #134217728 ; 0x8000000
|
|
|
- 800f944: f502 4280 add.w r2, r2, #16384 ; 0x4000
|
|
|
- 800f948: 6812 ldr r2, [r2, #0]
|
|
|
- 800f94a: 54c2 strb r2, [r0, r3]
|
|
|
+ 800f8c4: f103 6200 add.w r2, r3, #134217728 ; 0x8000000
|
|
|
+ 800f8c8: f502 4280 add.w r2, r2, #16384 ; 0x4000
|
|
|
+ 800f8cc: 6812 ldr r2, [r2, #0]
|
|
|
+ 800f8ce: 54c2 strb r2, [r0, r3]
|
|
|
*/
|
|
|
void SETTINGS_ReadFromFlash(uint8_t *data, uint32_t size)
|
|
|
{
|
|
|
uint32_t baseAddress = SETTINGS_SECTOR;
|
|
|
|
|
|
for (uint32_t i = 0; i < size; i++)
|
|
|
- 800f94c: 3301 adds r3, #1
|
|
|
- 800f94e: 428b cmp r3, r1
|
|
|
- 800f950: d1f6 bne.n 800f940 <SETTINGS_ReadFromFlash+0x4>
|
|
|
+ 800f8d0: 3301 adds r3, #1
|
|
|
+ 800f8d2: 428b cmp r3, r1
|
|
|
+ 800f8d4: d1f6 bne.n 800f8c4 <SETTINGS_ReadFromFlash+0x4>
|
|
|
*data++ = (*(uint32_t*)baseAddress++);;
|
|
|
}
|
|
|
- 800f952: 4770 bx lr
|
|
|
+ 800f8d6: 4770 bx lr
|
|
|
|
|
|
-0800f954 <SETTINGS_EraseFlashSector>:
|
|
|
+0800f8d8 <SETTINGS_EraseFlashSector>:
|
|
|
*/
|
|
|
void SETTINGS_EraseFlashSector(void)
|
|
|
{
|
|
|
FLASH_Status status;
|
|
|
|
|
|
if ((status = FLASH_EraseSector(FLASH_Sector_1, VoltageRange_3)) != FLASH_COMPLETE) {
|
|
|
- 800f954: 2008 movs r0, #8
|
|
|
- 800f956: 2102 movs r1, #2
|
|
|
- 800f958: f7fa ba34 b.w 8009dc4 <FLASH_EraseSector>
|
|
|
+ 800f8d8: 2008 movs r0, #8
|
|
|
+ 800f8da: 2102 movs r1, #2
|
|
|
+ 800f8dc: f7fa ba72 b.w 8009dc4 <FLASH_EraseSector>
|
|
|
|
|
|
-0800f95c <SETTINGS_GetCRC>:
|
|
|
+0800f8e0 <SETTINGS_GetCRC>:
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
uint32_t SETTINGS_GetCRC(void)
|
|
|
{
|
|
|
- 800f95c: b508 push {r3, lr}
|
|
|
+ 800f8e0: b508 push {r3, lr}
|
|
|
CRC_ResetDR();
|
|
|
- 800f95e: f7fa f9a1 bl 8009ca4 <CRC_ResetDR>
|
|
|
+ 800f8e2: f7fa f9df bl 8009ca4 <CRC_ResetDR>
|
|
|
return CRC_CalcBlockCRC((uint32_t*)&sSettings, sizeof(sSettings)/4);
|
|
|
- 800f962: 4803 ldr r0, [pc, #12] ; (800f970 <SETTINGS_GetCRC+0x14>)
|
|
|
- 800f964: 21b9 movs r1, #185 ; 0xb9
|
|
|
+ 800f8e6: 4803 ldr r0, [pc, #12] ; (800f8f4 <SETTINGS_GetCRC+0x14>)
|
|
|
+ 800f8e8: 2148 movs r1, #72 ; 0x48
|
|
|
}
|
|
|
- 800f966: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
+ 800f8ea: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
* @retval
|
|
|
*/
|
|
|
uint32_t SETTINGS_GetCRC(void)
|
|
|
{
|
|
|
CRC_ResetDR();
|
|
|
return CRC_CalcBlockCRC((uint32_t*)&sSettings, sizeof(sSettings)/4);
|
|
|
- 800f96a: f7fa b9a1 b.w 8009cb0 <CRC_CalcBlockCRC>
|
|
|
- 800f96e: bf00 nop
|
|
|
- 800f970: 2000838c .word 0x2000838c
|
|
|
+ 800f8ee: f7fa b9df b.w 8009cb0 <CRC_CalcBlockCRC>
|
|
|
+ 800f8f2: bf00 nop
|
|
|
+ 800f8f4: 2000838c .word 0x2000838c
|
|
|
|
|
|
-0800f974 <SETTINGS_WriteToFlash>:
|
|
|
+0800f8f8 <SETTINGS_WriteToFlash>:
|
|
|
|
|
|
/**
|
|
|
* @brief
|
|
|
*/
|
|
|
void SETTINGS_WriteToFlash(uint8_t *data, uint32_t size)
|
|
|
{
|
|
|
- 800f974: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
- 800f978: 4606 mov r6, r0
|
|
|
- 800f97a: 468a mov sl, r1
|
|
|
+ 800f8f8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
+ 800f8fc: 4606 mov r6, r0
|
|
|
+ 800f8fe: 468a mov sl, r1
|
|
|
uint32_t baseAddress = SETTINGS_SECTOR;
|
|
|
uint32_t checkCrc = 0;
|
|
|
uint32_t crc = SETTINGS_GetCRC();
|
|
|
- 800f97c: f7ff ffee bl 800f95c <SETTINGS_GetCRC>
|
|
|
+ 800f900: f7ff ffee bl 800f8e0 <SETTINGS_GetCRC>
|
|
|
/**
|
|
|
* @brief
|
|
|
*/
|
|
|
void SETTINGS_WriteToFlash(uint8_t *data, uint32_t size)
|
|
|
{
|
|
|
uint32_t baseAddress = SETTINGS_SECTOR;
|
|
|
- 800f980: 4c17 ldr r4, [pc, #92] ; (800f9e0 <SETTINGS_WriteToFlash+0x6c>)
|
|
|
+ 800f904: 4c17 ldr r4, [pc, #92] ; (800f964 <SETTINGS_WriteToFlash+0x6c>)
|
|
|
uint32_t checkCrc = 0;
|
|
|
uint32_t crc = SETTINGS_GetCRC();
|
|
|
- 800f982: 4680 mov r8, r0
|
|
|
- 800f984: 2703 movs r7, #3
|
|
|
+ 800f906: 4680 mov r8, r0
|
|
|
+ 800f908: 2703 movs r7, #3
|
|
|
FLASH_Status status;
|
|
|
|
|
|
for (uint8_t i = 0; i < 3; i++)
|
|
|
{
|
|
|
fAlarm = 0;
|
|
|
FLASH_Unlock();
|
|
|
- 800f986: f7fa f9a3 bl 8009cd0 <FLASH_Unlock>
|
|
|
- 800f98a: 4635 mov r5, r6
|
|
|
+ 800f90a: f7fa f9e1 bl 8009cd0 <FLASH_Unlock>
|
|
|
+ 800f90e: 4635 mov r5, r6
|
|
|
|
|
|
SETTINGS_EraseFlashSector();
|
|
|
- 800f98c: f7ff ffe2 bl 800f954 <SETTINGS_EraseFlashSector>
|
|
|
+ 800f910: f7ff ffe2 bl 800f8d8 <SETTINGS_EraseFlashSector>
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
* @brief
|
|
|
*/
|
|
|
void SETTINGS_WriteToFlash(uint8_t *data, uint32_t size)
|
|
|
- 800f990: eb04 0b0a add.w fp, r4, sl
|
|
|
+ 800f914: eb04 0b0a add.w fp, r4, sl
|
|
|
fAlarm = 0;
|
|
|
FLASH_Unlock();
|
|
|
|
|
|
SETTINGS_EraseFlashSector();
|
|
|
|
|
|
for (uint32_t i = 0; i < size; i++)
|
|
|
- 800f994: e00a b.n 800f9ac <SETTINGS_WriteToFlash+0x38>
|
|
|
+ 800f918: e00a b.n 800f930 <SETTINGS_WriteToFlash+0x38>
|
|
|
if ((status = FLASH_ProgramByte(baseAddress++, *data++)) != FLASH_COMPLETE) {
|
|
|
- 800f996: f815 1b01 ldrb.w r1, [r5], #1
|
|
|
- 800f99a: 4620 mov r0, r4
|
|
|
- 800f99c: f7fa f9d8 bl 8009d50 <FLASH_ProgramByte>
|
|
|
- 800f9a0: f104 0901 add.w r9, r4, #1
|
|
|
- 800f9a4: 2808 cmp r0, #8
|
|
|
- 800f9a6: 462e mov r6, r5
|
|
|
- 800f9a8: 464c mov r4, r9
|
|
|
- 800f9aa: d102 bne.n 800f9b2 <SETTINGS_WriteToFlash+0x3e>
|
|
|
+ 800f91a: f815 1b01 ldrb.w r1, [r5], #1
|
|
|
+ 800f91e: 4620 mov r0, r4
|
|
|
+ 800f920: f7fa fa16 bl 8009d50 <FLASH_ProgramByte>
|
|
|
+ 800f924: f104 0901 add.w r9, r4, #1
|
|
|
+ 800f928: 2808 cmp r0, #8
|
|
|
+ 800f92a: 462e mov r6, r5
|
|
|
+ 800f92c: 464c mov r4, r9
|
|
|
+ 800f92e: d102 bne.n 800f936 <SETTINGS_WriteToFlash+0x3e>
|
|
|
fAlarm = 0;
|
|
|
FLASH_Unlock();
|
|
|
|
|
|
SETTINGS_EraseFlashSector();
|
|
|
|
|
|
for (uint32_t i = 0; i < size; i++)
|
|
|
- 800f9ac: 455c cmp r4, fp
|
|
|
- 800f9ae: 462e mov r6, r5
|
|
|
- 800f9b0: d1f1 bne.n 800f996 <SETTINGS_WriteToFlash+0x22>
|
|
|
+ 800f930: 455c cmp r4, fp
|
|
|
+ 800f932: 462e mov r6, r5
|
|
|
+ 800f934: d1f1 bne.n 800f91a <SETTINGS_WriteToFlash+0x22>
|
|
|
if ((status = FLASH_ProgramByte(baseAddress++, *data++)) != FLASH_COMPLETE) {
|
|
|
DBG printf("FLASH_ProgramByte error: status = %d\r\n", status);
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
if ((status = FLASH_ProgramWord((uint32_t)CRC_ADDRESS, crc)) != FLASH_COMPLETE) {
|
|
|
- 800f9b2: 4641 mov r1, r8
|
|
|
- 800f9b4: 480b ldr r0, [pc, #44] ; (800f9e4 <SETTINGS_WriteToFlash+0x70>)
|
|
|
- 800f9b6: f7fa f9e7 bl 8009d88 <FLASH_ProgramWord>
|
|
|
+ 800f936: 4641 mov r1, r8
|
|
|
+ 800f938: 480b ldr r0, [pc, #44] ; (800f968 <SETTINGS_WriteToFlash+0x70>)
|
|
|
+ 800f93a: f7fa fa25 bl 8009d88 <FLASH_ProgramWord>
|
|
|
DBG printf("FLASH_ProgramWord error: status = %d\r\n", status);
|
|
|
}
|
|
|
|
|
|
FLASH_Lock();
|
|
|
- 800f9ba: f7fa f997 bl 8009cec <FLASH_Lock>
|
|
|
+ 800f93e: f7fa f9d5 bl 8009cec <FLASH_Lock>
|
|
|
|
|
|
/* Считываем что записали */
|
|
|
SETTINGS_ReadFromFlash((uint8_t*)&sSettings, sizeof(sSettings));
|
|
|
- 800f9be: 480a ldr r0, [pc, #40] ; (800f9e8 <SETTINGS_WriteToFlash+0x74>)
|
|
|
- 800f9c0: f44f 7139 mov.w r1, #740 ; 0x2e4
|
|
|
- 800f9c4: f7ff ffba bl 800f93c <SETTINGS_ReadFromFlash>
|
|
|
+ 800f942: 480a ldr r0, [pc, #40] ; (800f96c <SETTINGS_WriteToFlash+0x74>)
|
|
|
+ 800f944: f44f 7190 mov.w r1, #288 ; 0x120
|
|
|
+ 800f948: f7ff ffba bl 800f8c0 <SETTINGS_ReadFromFlash>
|
|
|
|
|
|
checkCrc = SETTINGS_GetCRC();
|
|
|
- 800f9c8: f7ff ffc8 bl 800f95c <SETTINGS_GetCRC>
|
|
|
+ 800f94c: f7ff ffc8 bl 800f8e0 <SETTINGS_GetCRC>
|
|
|
|
|
|
/* Проверяем CRC того что было записано */
|
|
|
if (checkCrc == crc)
|
|
|
- 800f9cc: 4540 cmp r0, r8
|
|
|
- 800f9ce: d004 beq.n 800f9da <SETTINGS_WriteToFlash+0x66>
|
|
|
- 800f9d0: 3f01 subs r7, #1
|
|
|
+ 800f950: 4540 cmp r0, r8
|
|
|
+ 800f952: d004 beq.n 800f95e <SETTINGS_WriteToFlash+0x66>
|
|
|
+ 800f954: 3f01 subs r7, #1
|
|
|
uint32_t checkCrc = 0;
|
|
|
uint32_t crc = SETTINGS_GetCRC();
|
|
|
bool fAlarm = 0;
|
|
|
FLASH_Status status;
|
|
|
|
|
|
for (uint8_t i = 0; i < 3; i++)
|
|
|
- 800f9d2: f017 07ff ands.w r7, r7, #255 ; 0xff
|
|
|
- 800f9d6: d1d6 bne.n 800f986 <SETTINGS_WriteToFlash+0x12>
|
|
|
- 800f9d8: e7fe b.n 800f9d8 <SETTINGS_WriteToFlash+0x64>
|
|
|
- 800f9da: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
- 800f9de: bf00 nop
|
|
|
- 800f9e0: 08004000 .word 0x08004000
|
|
|
- 800f9e4: 08007f9c .word 0x08007f9c
|
|
|
- 800f9e8: 2000838c .word 0x2000838c
|
|
|
-
|
|
|
-0800f9ec <SETTINGS_GetCritSecCRC>:
|
|
|
+ 800f956: f017 07ff ands.w r7, r7, #255 ; 0xff
|
|
|
+ 800f95a: d1d6 bne.n 800f90a <SETTINGS_WriteToFlash+0x12>
|
|
|
+ 800f95c: e7fe b.n 800f95c <SETTINGS_WriteToFlash+0x64>
|
|
|
+ 800f95e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
+ 800f962: bf00 nop
|
|
|
+ 800f964: 08004000 .word 0x08004000
|
|
|
+ 800f968: 08005f9c .word 0x08005f9c
|
|
|
+ 800f96c: 2000838c .word 0x2000838c
|
|
|
+
|
|
|
+0800f970 <SETTINGS_GetCritSecCRC>:
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
uint32_t SETTINGS_GetCritSecCRC(void)
|
|
|
{
|
|
|
- 800f9ec: b508 push {r3, lr}
|
|
|
+ 800f970: b508 push {r3, lr}
|
|
|
CRC_ResetDR();
|
|
|
- 800f9ee: f7fa f959 bl 8009ca4 <CRC_ResetDR>
|
|
|
+ 800f972: f7fa f997 bl 8009ca4 <CRC_ResetDR>
|
|
|
uint32_t critsec_len = (uint32_t)((uint8_t *)(&sSettings.CritSecCRC) - (uint8_t *)&sSettings) / 4;
|
|
|
return CRC_CalcBlockCRC((uint32_t *)&sSettings, critsec_len);
|
|
|
- 800f9f2: 4803 ldr r0, [pc, #12] ; (800fa00 <SETTINGS_GetCritSecCRC+0x14>)
|
|
|
- 800f9f4: 21b8 movs r1, #184 ; 0xb8
|
|
|
+ 800f976: 4803 ldr r0, [pc, #12] ; (800f984 <SETTINGS_GetCritSecCRC+0x14>)
|
|
|
+ 800f978: 2147 movs r1, #71 ; 0x47
|
|
|
}
|
|
|
- 800f9f6: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
+ 800f97a: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
*/
|
|
|
uint32_t SETTINGS_GetCritSecCRC(void)
|
|
|
{
|
|
|
CRC_ResetDR();
|
|
|
uint32_t critsec_len = (uint32_t)((uint8_t *)(&sSettings.CritSecCRC) - (uint8_t *)&sSettings) / 4;
|
|
|
return CRC_CalcBlockCRC((uint32_t *)&sSettings, critsec_len);
|
|
|
- 800f9fa: f7fa b959 b.w 8009cb0 <CRC_CalcBlockCRC>
|
|
|
- 800f9fe: bf00 nop
|
|
|
- 800fa00: 2000838c .word 0x2000838c
|
|
|
+ 800f97e: f7fa b997 b.w 8009cb0 <CRC_CalcBlockCRC>
|
|
|
+ 800f982: bf00 nop
|
|
|
+ 800f984: 2000838c .word 0x2000838c
|
|
|
|
|
|
-0800fa04 <SETTINGS_Save>:
|
|
|
+0800f988 <SETTINGS_Save>:
|
|
|
|
|
|
/**
|
|
|
* @brief Запись структуры настроек во flesh
|
|
|
*/
|
|
|
void SETTINGS_Save(void)
|
|
|
{
|
|
|
- 800fa04: b508 push {r3, lr}
|
|
|
+ 800f988: b508 push {r3, lr}
|
|
|
/* Calc critical section CRC and store to the settings structure */
|
|
|
sSettings.CritSecCRC = SETTINGS_GetCritSecCRC();
|
|
|
- 800fa06: f7ff fff1 bl 800f9ec <SETTINGS_GetCritSecCRC>
|
|
|
- 800fa0a: 4b05 ldr r3, [pc, #20] ; (800fa20 <SETTINGS_Save+0x1c>)
|
|
|
+ 800f98a: f7ff fff1 bl 800f970 <SETTINGS_GetCritSecCRC>
|
|
|
+ 800f98e: 4b05 ldr r3, [pc, #20] ; (800f9a4 <SETTINGS_Save+0x1c>)
|
|
|
|
|
|
SETTINGS_WriteToFlash((uint8_t*)&sSettings, sizeof(sSettings));
|
|
|
- 800fa0c: f44f 7139 mov.w r1, #740 ; 0x2e4
|
|
|
+ 800f990: f44f 7190 mov.w r1, #288 ; 0x120
|
|
|
* @brief Запись структуры настроек во flesh
|
|
|
*/
|
|
|
void SETTINGS_Save(void)
|
|
|
{
|
|
|
/* Calc critical section CRC and store to the settings structure */
|
|
|
sSettings.CritSecCRC = SETTINGS_GetCritSecCRC();
|
|
|
- 800fa10: f8c3 02e0 str.w r0, [r3, #736] ; 0x2e0
|
|
|
+ 800f994: f8c3 011c str.w r0, [r3, #284] ; 0x11c
|
|
|
|
|
|
SETTINGS_WriteToFlash((uint8_t*)&sSettings, sizeof(sSettings));
|
|
|
- 800fa14: 4618 mov r0, r3
|
|
|
+ 800f998: 4618 mov r0, r3
|
|
|
}
|
|
|
- 800fa16: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
+ 800f99a: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
void SETTINGS_Save(void)
|
|
|
{
|
|
|
/* Calc critical section CRC and store to the settings structure */
|
|
|
sSettings.CritSecCRC = SETTINGS_GetCritSecCRC();
|
|
|
|
|
|
SETTINGS_WriteToFlash((uint8_t*)&sSettings, sizeof(sSettings));
|
|
|
- 800fa1a: f7ff bfab b.w 800f974 <SETTINGS_WriteToFlash>
|
|
|
- 800fa1e: bf00 nop
|
|
|
- 800fa20: 2000838c .word 0x2000838c
|
|
|
+ 800f99e: f7ff bfab b.w 800f8f8 <SETTINGS_WriteToFlash>
|
|
|
+ 800f9a2: bf00 nop
|
|
|
+ 800f9a4: 2000838c .word 0x2000838c
|
|
|
|
|
|
-0800fa24 <SETTINGS_SetAllDefault>:
|
|
|
+0800f9a8 <SETTINGS_SetAllDefault>:
|
|
|
|
|
|
/**
|
|
|
* @brief Сброс всех настроек в значения по умолчанию
|
|
|
*/
|
|
|
void SETTINGS_SetAllDefault(void)
|
|
|
{
|
|
|
- 800fa24: b510 push {r4, lr}
|
|
|
-/**
|
|
|
- * @brief Установить флаги по умолчанию
|
|
|
- */
|
|
|
-void SETTINGS_SetFlagsDef(void)
|
|
|
-{
|
|
|
- sSettings.sFlags.netsettingsChanged = false;
|
|
|
- 800fa26: 4c09 ldr r4, [pc, #36] ; (800fa4c <SETTINGS_SetAllDefault+0x28>)
|
|
|
-/**
|
|
|
- * @brief Сброс всех настроек в значения по умолчанию
|
|
|
- */
|
|
|
-void SETTINGS_SetAllDefault(void)
|
|
|
-{
|
|
|
+ 800f9a8: b508 push {r3, lr}
|
|
|
SETTINGS_SetBootParamsDef();
|
|
|
- 800fa28: f7ff fee8 bl 800f7fc <SETTINGS_SetBootParamsDef>
|
|
|
+ 800f9aa: f7ff ff27 bl 800f7fc <SETTINGS_SetBootParamsDef>
|
|
|
SETTINGS_SetWebParamsDef();
|
|
|
- 800fa2c: f7ff feee bl 800f80c <SETTINGS_SetWebParamsDef>
|
|
|
+ 800f9ae: f7ff ff2d bl 800f80c <SETTINGS_SetWebParamsDef>
|
|
|
SETTINGS_SetTempWebParamsDef();
|
|
|
- 800fa30: f7ff ff08 bl 800f844 <SETTINGS_SetTempWebParamsDef>
|
|
|
- SETTINGS_SetSnmpDef();
|
|
|
- 800fa34: f7ff ff22 bl 800f87c <SETTINGS_SetSnmpDef>
|
|
|
+ 800f9b2: f7ff ff47 bl 800f844 <SETTINGS_SetTempWebParamsDef>
|
|
|
SETTINGS_SetInfoDef();
|
|
|
- 800fa38: f7ff ff5e bl 800f8f8 <SETTINGS_SetInfoDef>
|
|
|
-/**
|
|
|
- * @brief Установить флаги по умолчанию
|
|
|
- */
|
|
|
-void SETTINGS_SetFlagsDef(void)
|
|
|
-{
|
|
|
- sSettings.sFlags.netsettingsChanged = false;
|
|
|
- 800fa3c: 2300 movs r3, #0
|
|
|
- 800fa3e: f884 32ce strb.w r3, [r4, #718] ; 0x2ce
|
|
|
- SETTINGS_SetTempWebParamsDef();
|
|
|
- SETTINGS_SetSnmpDef();
|
|
|
- SETTINGS_SetInfoDef();
|
|
|
- SETTINGS_SetFlagsDef();
|
|
|
+ 800f9b6: f7ff ff61 bl 800f87c <SETTINGS_SetInfoDef>
|
|
|
|
|
|
sSettings.CritSecCRC = SETTINGS_GetCritSecCRC();
|
|
|
- 800fa42: f7ff ffd3 bl 800f9ec <SETTINGS_GetCritSecCRC>
|
|
|
- 800fa46: f8c4 02e0 str.w r0, [r4, #736] ; 0x2e0
|
|
|
- 800fa4a: bd10 pop {r4, pc}
|
|
|
- 800fa4c: 2000838c .word 0x2000838c
|
|
|
+ 800f9ba: f7ff ffd9 bl 800f970 <SETTINGS_GetCritSecCRC>
|
|
|
+ 800f9be: 4b02 ldr r3, [pc, #8] ; (800f9c8 <SETTINGS_SetAllDefault+0x20>)
|
|
|
+ 800f9c0: f8c3 011c str.w r0, [r3, #284] ; 0x11c
|
|
|
+ 800f9c4: bd08 pop {r3, pc}
|
|
|
+ 800f9c6: bf00 nop
|
|
|
+ 800f9c8: 2000838c .word 0x2000838c
|
|
|
|
|
|
-0800fa50 <SETTINGS_Load>:
|
|
|
+0800f9cc <SETTINGS_Load>:
|
|
|
|
|
|
/**
|
|
|
* @brief Загрузка структуры настроек из flesh
|
|
|
*/
|
|
|
void SETTINGS_Load(void)
|
|
|
{
|
|
|
- 800fa50: b510 push {r4, lr}
|
|
|
+ 800f9cc: b510 push {r4, lr}
|
|
|
SETTINGS_ReadFromFlash((uint8_t*)&sSettings, sizeof(sSettings));
|
|
|
- 800fa52: 4c0b ldr r4, [pc, #44] ; (800fa80 <SETTINGS_Load+0x30>)
|
|
|
- 800fa54: f44f 7139 mov.w r1, #740 ; 0x2e4
|
|
|
- 800fa58: 4620 mov r0, r4
|
|
|
- 800fa5a: f7ff ff6f bl 800f93c <SETTINGS_ReadFromFlash>
|
|
|
+ 800f9ce: 4c0b ldr r4, [pc, #44] ; (800f9fc <SETTINGS_Load+0x30>)
|
|
|
+ 800f9d0: f44f 7190 mov.w r1, #288 ; 0x120
|
|
|
+ 800f9d4: 4620 mov r0, r4
|
|
|
+ 800f9d6: f7ff ff73 bl 800f8c0 <SETTINGS_ReadFromFlash>
|
|
|
|
|
|
/* Проверка CRC критической секции сектора настроек.
|
|
|
* Если CRC не совпадает, скорее всего настройки отсутствуют,
|
|
|
* прошиваем значения по умолчанию */
|
|
|
uint32_t crc = SETTINGS_GetCritSecCRC();
|
|
|
- 800fa5e: f7ff ffc5 bl 800f9ec <SETTINGS_GetCritSecCRC>
|
|
|
+ 800f9da: f7ff ffc9 bl 800f970 <SETTINGS_GetCritSecCRC>
|
|
|
|
|
|
if (sSettings.CritSecCRC != crc) {
|
|
|
- 800fa62: f8d4 32e0 ldr.w r3, [r4, #736] ; 0x2e0
|
|
|
- 800fa66: 4283 cmp r3, r0
|
|
|
- 800fa68: d008 beq.n 800fa7c <SETTINGS_Load+0x2c>
|
|
|
+ 800f9de: f8d4 311c ldr.w r3, [r4, #284] ; 0x11c
|
|
|
+ 800f9e2: 4283 cmp r3, r0
|
|
|
+ 800f9e4: d008 beq.n 800f9f8 <SETTINGS_Load+0x2c>
|
|
|
printf("\n\rIAP: Bad critical settings sector CRC. Factory defaults restored.\n\r");
|
|
|
- 800fa6a: 4806 ldr r0, [pc, #24] ; (800fa84 <SETTINGS_Load+0x34>)
|
|
|
- 800fa6c: f001 fe02 bl 8011674 <tfp_printf>
|
|
|
+ 800f9e6: 4806 ldr r0, [pc, #24] ; (800fa00 <SETTINGS_Load+0x34>)
|
|
|
+ 800f9e8: f001 fe00 bl 80115ec <tfp_printf>
|
|
|
SETTINGS_SetAllDefault();
|
|
|
- 800fa70: f7ff ffd8 bl 800fa24 <SETTINGS_SetAllDefault>
|
|
|
+ 800f9ec: f7ff ffdc bl 800f9a8 <SETTINGS_SetAllDefault>
|
|
|
SETTINGS_Save();
|
|
|
}
|
|
|
}
|
|
|
- 800fa74: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
+ 800f9f0: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
uint32_t crc = SETTINGS_GetCritSecCRC();
|
|
|
|
|
|
if (sSettings.CritSecCRC != crc) {
|
|
|
printf("\n\rIAP: Bad critical settings sector CRC. Factory defaults restored.\n\r");
|
|
|
SETTINGS_SetAllDefault();
|
|
|
SETTINGS_Save();
|
|
|
- 800fa78: f7ff bfc4 b.w 800fa04 <SETTINGS_Save>
|
|
|
- 800fa7c: bd10 pop {r4, pc}
|
|
|
- 800fa7e: bf00 nop
|
|
|
- 800fa80: 2000838c .word 0x2000838c
|
|
|
- 800fa84: 080118f6 .word 0x080118f6
|
|
|
+ 800f9f4: f7ff bfc8 b.w 800f988 <SETTINGS_Save>
|
|
|
+ 800f9f8: bd10 pop {r4, pc}
|
|
|
+ 800f9fa: bf00 nop
|
|
|
+ 800f9fc: 2000838c .word 0x2000838c
|
|
|
+ 800fa00: 08011857 .word 0x08011857
|
|
|
|
|
|
-0800fa88 <SETTINGS_GetMac>:
|
|
|
+0800fa04 <SETTINGS_GetMac>:
|
|
|
/**
|
|
|
* @brief Преобразует mac адрес строкового формата в массив uint8_t
|
|
|
* @param mac - буфер для вывода mac адреса
|
|
|
*/
|
|
|
void SETTINGS_GetMac(uint8_t *mac)
|
|
|
{
|
|
|
- 800fa88: b573 push {r0, r1, r4, r5, r6, lr}
|
|
|
+ 800fa04: b573 push {r0, r1, r4, r5, r6, lr}
|
|
|
char dummy[2];
|
|
|
char *macPtr = sSettings.sInfo.mac;
|
|
|
|
|
|
for (uint8_t i = 0; i < 6; i++)
|
|
|
{
|
|
|
strncpy(dummy, macPtr+i*3, 2);
|
|
|
- 800fa8a: 4e0b ldr r6, [pc, #44] ; (800fab8 <SETTINGS_GetMac+0x30>)
|
|
|
+ 800fa06: 4e0a ldr r6, [pc, #40] ; (800fa30 <SETTINGS_GetMac+0x2c>)
|
|
|
|
|
|
/**
|
|
|
* @brief Преобразует mac адрес строкового формата в массив uint8_t
|
|
|
* @param mac - буфер для вывода mac адреса
|
|
|
*/
|
|
|
void SETTINGS_GetMac(uint8_t *mac)
|
|
|
- 800fa8c: 1e45 subs r5, r0, #1
|
|
|
- 800fa8e: 2400 movs r4, #0
|
|
|
+ 800fa08: 1e45 subs r5, r0, #1
|
|
|
+ 800fa0a: 2400 movs r4, #0
|
|
|
char dummy[2];
|
|
|
char *macPtr = sSettings.sInfo.mac;
|
|
|
|
|
|
for (uint8_t i = 0; i < 6; i++)
|
|
|
{
|
|
|
strncpy(dummy, macPtr+i*3, 2);
|
|
|
- 800fa90: f504 710e add.w r1, r4, #568 ; 0x238
|
|
|
- 800fa94: 1989 adds r1, r1, r6
|
|
|
- 800fa96: 3106 adds r1, #6
|
|
|
- 800fa98: 2202 movs r2, #2
|
|
|
- 800fa9a: a801 add r0, sp, #4
|
|
|
- 800fa9c: f7f9 ff74 bl 8009988 <strncpy>
|
|
|
+ 800fa0c: 1931 adds r1, r6, r4
|
|
|
+ 800fa0e: 318c adds r1, #140 ; 0x8c
|
|
|
+ 800fa10: 2202 movs r2, #2
|
|
|
+ 800fa12: a801 add r0, sp, #4
|
|
|
+ 800fa14: f7f9 ffb8 bl 8009988 <strncpy>
|
|
|
mac[i] = (uint8_t)strtol(dummy, NULL, 16);
|
|
|
- 800faa0: 2100 movs r1, #0
|
|
|
- 800faa2: 2210 movs r2, #16
|
|
|
- 800faa4: a801 add r0, sp, #4
|
|
|
- 800faa6: f7fa f843 bl 8009b30 <strtol>
|
|
|
- 800faaa: 3403 adds r4, #3
|
|
|
+ 800fa18: 2100 movs r1, #0
|
|
|
+ 800fa1a: 2210 movs r2, #16
|
|
|
+ 800fa1c: a801 add r0, sp, #4
|
|
|
+ 800fa1e: f7fa f887 bl 8009b30 <strtol>
|
|
|
+ 800fa22: 3403 adds r4, #3
|
|
|
void SETTINGS_GetMac(uint8_t *mac)
|
|
|
{
|
|
|
char dummy[2];
|
|
|
char *macPtr = sSettings.sInfo.mac;
|
|
|
|
|
|
for (uint8_t i = 0; i < 6; i++)
|
|
|
- 800faac: 2c12 cmp r4, #18
|
|
|
+ 800fa24: 2c12 cmp r4, #18
|
|
|
{
|
|
|
strncpy(dummy, macPtr+i*3, 2);
|
|
|
mac[i] = (uint8_t)strtol(dummy, NULL, 16);
|
|
|
- 800faae: f805 0f01 strb.w r0, [r5, #1]!
|
|
|
+ 800fa26: f805 0f01 strb.w r0, [r5, #1]!
|
|
|
void SETTINGS_GetMac(uint8_t *mac)
|
|
|
{
|
|
|
char dummy[2];
|
|
|
char *macPtr = sSettings.sInfo.mac;
|
|
|
|
|
|
for (uint8_t i = 0; i < 6; i++)
|
|
|
- 800fab2: d1ed bne.n 800fa90 <SETTINGS_GetMac+0x8>
|
|
|
+ 800fa2a: d1ef bne.n 800fa0c <SETTINGS_GetMac+0x8>
|
|
|
{
|
|
|
strncpy(dummy, macPtr+i*3, 2);
|
|
|
mac[i] = (uint8_t)strtol(dummy, NULL, 16);
|
|
|
}
|
|
|
}
|
|
|
- 800fab4: bd7c pop {r2, r3, r4, r5, r6, pc}
|
|
|
- 800fab6: bf00 nop
|
|
|
- 800fab8: 2000838c .word 0x2000838c
|
|
|
+ 800fa2c: bd7c pop {r2, r3, r4, r5, r6, pc}
|
|
|
+ 800fa2e: bf00 nop
|
|
|
+ 800fa30: 2000838c .word 0x2000838c
|
|
|
|
|
|
-0800fabc <timer_AddFunction>:
|
|
|
+0800fa34 <timer_AddFunction>:
|
|
|
* @brief Добавить функцию в список вызова.
|
|
|
* Handler будет вызываться с заданной частотой
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void timer_AddFunction(uint16_t Frequency, TTimerHandler Handler)
|
|
|
{
|
|
|
- 800fabc: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
+ 800fa34: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
{
|
|
|
/* Найдем пустой слот */
|
|
|
if(!Handlers[i].Handler)
|
|
|
- 800fabe: 4e0c ldr r6, [pc, #48] ; (800faf0 <timer_AddFunction+0x34>)
|
|
|
+ 800fa36: 4e0c ldr r6, [pc, #48] ; (800fa68 <timer_AddFunction+0x34>)
|
|
|
*/
|
|
|
void timer_AddFunction(uint16_t Frequency, TTimerHandler Handler)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
- 800fac0: 2300 movs r3, #0
|
|
|
+ 800fa38: 2300 movs r3, #0
|
|
|
/**
|
|
|
* @brief Добавить функцию в список вызова.
|
|
|
* Handler будет вызываться с заданной частотой
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void timer_AddFunction(uint16_t Frequency, TTimerHandler Handler)
|
|
|
- 800fac2: 270c movs r7, #12
|
|
|
- 800fac4: fb07 f203 mul.w r2, r7, r3
|
|
|
+ 800fa3a: 270c movs r7, #12
|
|
|
+ 800fa3c: fb07 f203 mul.w r2, r7, r3
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
{
|
|
|
/* Найдем пустой слот */
|
|
|
if(!Handlers[i].Handler)
|
|
|
- 800fac8: 4c09 ldr r4, [pc, #36] ; (800faf0 <timer_AddFunction+0x34>)
|
|
|
- 800faca: 5995 ldr r5, [r2, r6]
|
|
|
- 800facc: b95d cbnz r5, 800fae6 <timer_AddFunction+0x2a>
|
|
|
+ 800fa40: 4c09 ldr r4, [pc, #36] ; (800fa68 <timer_AddFunction+0x34>)
|
|
|
+ 800fa42: 5995 ldr r5, [r2, r6]
|
|
|
+ 800fa44: b95d cbnz r5, 800fa5e <timer_AddFunction+0x2a>
|
|
|
{
|
|
|
/* Обработчик, частота опроса */
|
|
|
Handlers[i].Run = true;
|
|
|
- 800face: 18a3 adds r3, r4, r2
|
|
|
- 800fad0: 2601 movs r6, #1
|
|
|
- 800fad2: 721e strb r6, [r3, #8]
|
|
|
+ 800fa46: 18a3 adds r3, r4, r2
|
|
|
+ 800fa48: 2601 movs r6, #1
|
|
|
+ 800fa4a: 721e strb r6, [r3, #8]
|
|
|
Handlers[i].Fired = false;
|
|
|
- 800fad4: 725d strb r5, [r3, #9]
|
|
|
+ 800fa4c: 725d strb r5, [r3, #9]
|
|
|
Handlers[i].Handler = Handler;
|
|
|
Handlers[i].Reload = Frequency;
|
|
|
- 800fad6: 80d8 strh r0, [r3, #6]
|
|
|
+ 800fa4e: 80d8 strh r0, [r3, #6]
|
|
|
Handlers[i].Countdown = Handlers[i].Reload;
|
|
|
- 800fad8: 8098 strh r0, [r3, #4]
|
|
|
+ 800fa50: 8098 strh r0, [r3, #4]
|
|
|
|
|
|
TimerCount++;
|
|
|
- 800fada: 4b06 ldr r3, [pc, #24] ; (800faf4 <timer_AddFunction+0x38>)
|
|
|
+ 800fa52: 4b06 ldr r3, [pc, #24] ; (800fa6c <timer_AddFunction+0x38>)
|
|
|
if(!Handlers[i].Handler)
|
|
|
{
|
|
|
/* Обработчик, частота опроса */
|
|
|
Handlers[i].Run = true;
|
|
|
Handlers[i].Fired = false;
|
|
|
Handlers[i].Handler = Handler;
|
|
|
- 800fadc: 50a1 str r1, [r4, r2]
|
|
|
+ 800fa54: 50a1 str r1, [r4, r2]
|
|
|
Handlers[i].Reload = Frequency;
|
|
|
Handlers[i].Countdown = Handlers[i].Reload;
|
|
|
|
|
|
TimerCount++;
|
|
|
- 800fade: 681a ldr r2, [r3, #0]
|
|
|
- 800fae0: 1992 adds r2, r2, r6
|
|
|
- 800fae2: 601a str r2, [r3, #0]
|
|
|
+ 800fa56: 681a ldr r2, [r3, #0]
|
|
|
+ 800fa58: 1992 adds r2, r2, r6
|
|
|
+ 800fa5a: 601a str r2, [r3, #0]
|
|
|
|
|
|
return;
|
|
|
- 800fae4: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 800fa5c: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
*/
|
|
|
void timer_AddFunction(uint16_t Frequency, TTimerHandler Handler)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
- 800fae6: 3301 adds r3, #1
|
|
|
- 800fae8: 2b14 cmp r3, #20
|
|
|
- 800faea: d1eb bne.n 800fac4 <timer_AddFunction+0x8>
|
|
|
- 800faec: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
- 800faee: bf00 nop
|
|
|
- 800faf0: 20006c8c .word 0x20006c8c
|
|
|
- 800faf4: 20006d7c .word 0x20006d7c
|
|
|
-
|
|
|
-0800faf8 <timer_Main>:
|
|
|
+ 800fa5e: 3301 adds r3, #1
|
|
|
+ 800fa60: 2b14 cmp r3, #20
|
|
|
+ 800fa62: d1eb bne.n 800fa3c <timer_AddFunction+0x8>
|
|
|
+ 800fa64: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 800fa66: bf00 nop
|
|
|
+ 800fa68: 20006c8c .word 0x20006c8c
|
|
|
+ 800fa6c: 20006d7c .word 0x20006d7c
|
|
|
+
|
|
|
+0800fa70 <timer_Main>:
|
|
|
* @brief Функция перебора и вызова актуальных задач.
|
|
|
* Должна вызываться в главном цикле
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void timer_Main(void)
|
|
|
{
|
|
|
- 800faf8: b570 push {r4, r5, r6, lr}
|
|
|
- 800fafa: 4c06 ldr r4, [pc, #24] ; (800fb14 <timer_Main+0x1c>)
|
|
|
+ 800fa70: b570 push {r4, r5, r6, lr}
|
|
|
+ 800fa72: 4c06 ldr r4, [pc, #24] ; (800fa8c <timer_Main+0x1c>)
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
{
|
|
|
/* Если сработало - вызовем */
|
|
|
if(Handlers[i].Fired)
|
|
|
{
|
|
|
Handlers[i].Fired = false;
|
|
|
- 800fafc: 2600 movs r6, #0
|
|
|
+ 800fa74: 2600 movs r6, #0
|
|
|
/**
|
|
|
* @brief Функция перебора и вызова актуальных задач.
|
|
|
* Должна вызываться в главном цикле
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void timer_Main(void)
|
|
|
- 800fafe: f104 05f0 add.w r5, r4, #240 ; 0xf0
|
|
|
+ 800fa76: f104 05f0 add.w r5, r4, #240 ; 0xf0
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
{
|
|
|
/* Если сработало - вызовем */
|
|
|
if(Handlers[i].Fired)
|
|
|
- 800fb02: 7a63 ldrb r3, [r4, #9]
|
|
|
- 800fb04: b113 cbz r3, 800fb0c <timer_Main+0x14>
|
|
|
+ 800fa7a: 7a63 ldrb r3, [r4, #9]
|
|
|
+ 800fa7c: b113 cbz r3, 800fa84 <timer_Main+0x14>
|
|
|
{
|
|
|
Handlers[i].Fired = false;
|
|
|
- 800fb06: 7266 strb r6, [r4, #9]
|
|
|
+ 800fa7e: 7266 strb r6, [r4, #9]
|
|
|
Handlers[i].Handler();
|
|
|
- 800fb08: 6823 ldr r3, [r4, #0]
|
|
|
- 800fb0a: 4798 blx r3
|
|
|
- 800fb0c: 340c adds r4, #12
|
|
|
+ 800fa80: 6823 ldr r3, [r4, #0]
|
|
|
+ 800fa82: 4798 blx r3
|
|
|
+ 800fa84: 340c adds r4, #12
|
|
|
*/
|
|
|
void timer_Main(void)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
- 800fb0e: 42ac cmp r4, r5
|
|
|
- 800fb10: d1f7 bne.n 800fb02 <timer_Main+0xa>
|
|
|
+ 800fa86: 42ac cmp r4, r5
|
|
|
+ 800fa88: d1f7 bne.n 800fa7a <timer_Main+0xa>
|
|
|
{
|
|
|
Handlers[i].Fired = false;
|
|
|
Handlers[i].Handler();
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
- 800fb12: bd70 pop {r4, r5, r6, pc}
|
|
|
- 800fb14: 20006c8c .word 0x20006c8c
|
|
|
+ 800fa8a: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 800fa8c: 20006c8c .word 0x20006c8c
|
|
|
|
|
|
-0800fb18 <Delay_ms>:
|
|
|
+0800fa90 <Delay_ms>:
|
|
|
* @brief Задержка в миллисекундах
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void Delay_ms(uint32_t nTime)
|
|
|
{
|
|
|
TimingDelay = nTime;
|
|
|
- 800fb18: 4b02 ldr r3, [pc, #8] ; (800fb24 <Delay_ms+0xc>)
|
|
|
- 800fb1a: 6018 str r0, [r3, #0]
|
|
|
+ 800fa90: 4b02 ldr r3, [pc, #8] ; (800fa9c <Delay_ms+0xc>)
|
|
|
+ 800fa92: 6018 str r0, [r3, #0]
|
|
|
while(TimingDelay);
|
|
|
- 800fb1c: 681a ldr r2, [r3, #0]
|
|
|
- 800fb1e: 2a00 cmp r2, #0
|
|
|
- 800fb20: d1fc bne.n 800fb1c <Delay_ms+0x4>
|
|
|
+ 800fa94: 681a ldr r2, [r3, #0]
|
|
|
+ 800fa96: 2a00 cmp r2, #0
|
|
|
+ 800fa98: d1fc bne.n 800fa94 <Delay_ms+0x4>
|
|
|
}
|
|
|
- 800fb22: 4770 bx lr
|
|
|
- 800fb24: 20008670 .word 0x20008670
|
|
|
+ 800fa9a: 4770 bx lr
|
|
|
+ 800fa9c: 200084ac .word 0x200084ac
|
|
|
|
|
|
-0800fb28 <TimingDelay_Decrement>:
|
|
|
+0800faa0 <TimingDelay_Decrement>:
|
|
|
* @brief Вспомогательная функция для реализации Delay_ms
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void TimingDelay_Decrement(void) {
|
|
|
|
|
|
if (TimingDelay)
|
|
|
- 800fb28: 4b03 ldr r3, [pc, #12] ; (800fb38 <TimingDelay_Decrement+0x10>)
|
|
|
- 800fb2a: 681a ldr r2, [r3, #0]
|
|
|
- 800fb2c: b112 cbz r2, 800fb34 <TimingDelay_Decrement+0xc>
|
|
|
+ 800faa0: 4b03 ldr r3, [pc, #12] ; (800fab0 <TimingDelay_Decrement+0x10>)
|
|
|
+ 800faa2: 681a ldr r2, [r3, #0]
|
|
|
+ 800faa4: b112 cbz r2, 800faac <TimingDelay_Decrement+0xc>
|
|
|
TimingDelay--;
|
|
|
- 800fb2e: 681a ldr r2, [r3, #0]
|
|
|
- 800fb30: 3a01 subs r2, #1
|
|
|
- 800fb32: 601a str r2, [r3, #0]
|
|
|
- 800fb34: 4770 bx lr
|
|
|
- 800fb36: bf00 nop
|
|
|
- 800fb38: 20008670 .word 0x20008670
|
|
|
-
|
|
|
-0800fb3c <SysTick_Handler>:
|
|
|
+ 800faa6: 681a ldr r2, [r3, #0]
|
|
|
+ 800faa8: 3a01 subs r2, #1
|
|
|
+ 800faaa: 601a str r2, [r3, #0]
|
|
|
+ 800faac: 4770 bx lr
|
|
|
+ 800faae: bf00 nop
|
|
|
+ 800fab0: 200084ac .word 0x200084ac
|
|
|
+
|
|
|
+0800fab4 <SysTick_Handler>:
|
|
|
/**
|
|
|
* @brief Обработчик прерывания системного таймера
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void SysTick_Handler(void)
|
|
|
{
|
|
|
- 800fb3c: b508 push {r3, lr}
|
|
|
+ 800fab4: b508 push {r3, lr}
|
|
|
int i;
|
|
|
|
|
|
Time_Update();
|
|
|
- 800fb3e: f001 fa37 bl 8010fb0 <Time_Update>
|
|
|
+ 800fab6: f001 fa37 bl 8010f28 <Time_Update>
|
|
|
|
|
|
TimingDelay_Decrement();
|
|
|
- 800fb42: f7ff fff1 bl 800fb28 <TimingDelay_Decrement>
|
|
|
- 800fb46: 4b0b ldr r3, [pc, #44] ; (800fb74 <SysTick_Handler+0x38>)
|
|
|
+ 800faba: f7ff fff1 bl 800faa0 <TimingDelay_Decrement>
|
|
|
+ 800fabe: 4b0b ldr r3, [pc, #44] ; (800faec <SysTick_Handler+0x38>)
|
|
|
if(--Handlers[i].Countdown == 0)
|
|
|
{
|
|
|
Handlers[i].Countdown = Handlers[i].Reload;
|
|
|
|
|
|
/* Запишем, что сработало */
|
|
|
Handlers[i].Fired = true;
|
|
|
- 800fb48: 2001 movs r0, #1
|
|
|
+ 800fac0: 2001 movs r0, #1
|
|
|
|
|
|
/**
|
|
|
* @brief Обработчик прерывания системного таймера
|
|
|
* @retval нет
|
|
|
*/
|
|
|
void SysTick_Handler(void)
|
|
|
- 800fb4a: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
|
+ 800fac2: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
|
|
|
|
TimingDelay_Decrement();
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
{
|
|
|
if(Handlers[i].Run)
|
|
|
- 800fb4e: 781a ldrb r2, [r3, #0]
|
|
|
- 800fb50: b15a cbz r2, 800fb6a <SysTick_Handler+0x2e>
|
|
|
+ 800fac6: 781a ldrb r2, [r3, #0]
|
|
|
+ 800fac8: b15a cbz r2, 800fae2 <SysTick_Handler+0x2e>
|
|
|
{
|
|
|
if(--Handlers[i].Countdown == 0)
|
|
|
- 800fb52: f833 2c04 ldrh.w r2, [r3, #-4]
|
|
|
- 800fb56: 3a01 subs r2, #1
|
|
|
- 800fb58: b292 uxth r2, r2
|
|
|
- 800fb5a: f823 2c04 strh.w r2, [r3, #-4]
|
|
|
- 800fb5e: b922 cbnz r2, 800fb6a <SysTick_Handler+0x2e>
|
|
|
+ 800faca: f833 2c04 ldrh.w r2, [r3, #-4]
|
|
|
+ 800face: 3a01 subs r2, #1
|
|
|
+ 800fad0: b292 uxth r2, r2
|
|
|
+ 800fad2: f823 2c04 strh.w r2, [r3, #-4]
|
|
|
+ 800fad6: b922 cbnz r2, 800fae2 <SysTick_Handler+0x2e>
|
|
|
{
|
|
|
Handlers[i].Countdown = Handlers[i].Reload;
|
|
|
- 800fb60: f833 2c02 ldrh.w r2, [r3, #-2]
|
|
|
+ 800fad8: f833 2c02 ldrh.w r2, [r3, #-2]
|
|
|
|
|
|
/* Запишем, что сработало */
|
|
|
Handlers[i].Fired = true;
|
|
|
- 800fb64: 7058 strb r0, [r3, #1]
|
|
|
+ 800fadc: 7058 strb r0, [r3, #1]
|
|
|
{
|
|
|
if(Handlers[i].Run)
|
|
|
{
|
|
|
if(--Handlers[i].Countdown == 0)
|
|
|
{
|
|
|
Handlers[i].Countdown = Handlers[i].Reload;
|
|
|
- 800fb66: f823 2c04 strh.w r2, [r3, #-4]
|
|
|
- 800fb6a: 330c adds r3, #12
|
|
|
+ 800fade: f823 2c04 strh.w r2, [r3, #-4]
|
|
|
+ 800fae2: 330c adds r3, #12
|
|
|
|
|
|
Time_Update();
|
|
|
|
|
|
TimingDelay_Decrement();
|
|
|
|
|
|
for(i = 0; i < TIMER_HANDLERS; i++)
|
|
|
- 800fb6c: 428b cmp r3, r1
|
|
|
- 800fb6e: d1ee bne.n 800fb4e <SysTick_Handler+0x12>
|
|
|
+ 800fae4: 428b cmp r3, r1
|
|
|
+ 800fae6: d1ee bne.n 800fac6 <SysTick_Handler+0x12>
|
|
|
/* Запишем, что сработало */
|
|
|
Handlers[i].Fired = true;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
- 800fb70: bd08 pop {r3, pc}
|
|
|
- 800fb72: bf00 nop
|
|
|
- 800fb74: 20006c94 .word 0x20006c94
|
|
|
+ 800fae8: bd08 pop {r3, pc}
|
|
|
+ 800faea: bf00 nop
|
|
|
+ 800faec: 20006c94 .word 0x20006c94
|
|
|
|
|
|
-0800fb78 <putc_>:
|
|
|
+0800faf0 <putc_>:
|
|
|
#ifdef SWOTRACE
|
|
|
ITM_SendChar(c);
|
|
|
#endif
|
|
|
}
|
|
|
|
|
|
void putc_(void* p, char c) {
|
|
|
- 800fb78: 4770 bx lr
|
|
|
- 800fb7a: 0000 movs r0, r0
|
|
|
+ 800faf0: 4770 bx lr
|
|
|
+ 800faf2: 0000 movs r0, r0
|
|
|
|
|
|
-0800fb7c <InitUSART>:
|
|
|
+0800faf4 <InitUSART>:
|
|
|
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
void InitUSART( void) {
|
|
|
- 800fb7c: b570 push {r4, r5, r6, lr}
|
|
|
+ 800faf4: b570 push {r4, r5, r6, lr}
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
USART_InitTypeDef USART_InitStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
- 800fb7e: 2002 movs r0, #2
|
|
|
+ 800faf6: 2002 movs r0, #2
|
|
|
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
void InitUSART( void) {
|
|
|
- 800fb80: b086 sub sp, #24
|
|
|
+ 800faf8: b086 sub sp, #24
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
USART_InitTypeDef USART_InitStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
- 800fb82: 2101 movs r1, #1
|
|
|
- 800fb84: f7fa fa06 bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
+ 800fafa: 2101 movs r1, #1
|
|
|
+ 800fafc: f7fa fa4a bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
|
|
- 800fb88: 4d26 ldr r5, [pc, #152] ; (800fc24 <InitUSART+0xa8>)
|
|
|
+ 800fb00: 4d26 ldr r5, [pc, #152] ; (800fb9c <InitUSART+0xa8>)
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
USART_InitTypeDef USART_InitStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
|
|
- 800fb8a: 2010 movs r0, #16
|
|
|
- 800fb8c: 2101 movs r1, #1
|
|
|
- 800fb8e: f7fa fa19 bl 8009fc4 <RCC_APB2PeriphClockCmd>
|
|
|
+ 800fb02: 2010 movs r0, #16
|
|
|
+ 800fb04: 2101 movs r1, #1
|
|
|
+ 800fb06: f7fa fa5d bl 8009fc4 <RCC_APB2PeriphClockCmd>
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
|
|
|
- 800fb92: 23c0 movs r3, #192 ; 0xc0
|
|
|
+ 800fb0a: 23c0 movs r3, #192 ; 0xc0
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 800fb94: 2400 movs r4, #0
|
|
|
+ 800fb0c: 2400 movs r4, #0
|
|
|
USART_InitTypeDef USART_InitStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
|
|
|
- 800fb96: 9300 str r3, [sp, #0]
|
|
|
+ 800fb0e: 9300 str r3, [sp, #0]
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
- 800fb98: 2601 movs r6, #1
|
|
|
+ 800fb10: 2601 movs r6, #1
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
- 800fb9a: 2302 movs r3, #2
|
|
|
+ 800fb12: 2302 movs r3, #2
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
|
|
- 800fb9c: 4628 mov r0, r5
|
|
|
- 800fb9e: 4669 mov r1, sp
|
|
|
+ 800fb14: 4628 mov r0, r5
|
|
|
+ 800fb16: 4669 mov r1, sp
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
- 800fba0: f88d 3005 strb.w r3, [sp, #5]
|
|
|
+ 800fb18: f88d 3005 strb.w r3, [sp, #5]
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
- 800fba4: f88d 3004 strb.w r3, [sp, #4]
|
|
|
+ 800fb1c: f88d 3004 strb.w r3, [sp, #4]
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 800fba8: f88d 4006 strb.w r4, [sp, #6]
|
|
|
+ 800fb20: f88d 4006 strb.w r4, [sp, #6]
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
- 800fbac: f88d 6007 strb.w r6, [sp, #7]
|
|
|
+ 800fb24: f88d 6007 strb.w r6, [sp, #7]
|
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
|
|
- 800fbb0: f7fa f93e bl 8009e30 <GPIO_Init>
|
|
|
+ 800fb28: f7fa f982 bl 8009e30 <GPIO_Init>
|
|
|
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_USART1);
|
|
|
- 800fbb4: 4628 mov r0, r5
|
|
|
- 800fbb6: 2106 movs r1, #6
|
|
|
- 800fbb8: 2207 movs r2, #7
|
|
|
- 800fbba: f7fa f988 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 800fb2c: 4628 mov r0, r5
|
|
|
+ 800fb2e: 2106 movs r1, #6
|
|
|
+ 800fb30: 2207 movs r2, #7
|
|
|
+ 800fb32: f7fa f9cc bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_USART1);
|
|
|
- 800fbbe: 2107 movs r1, #7
|
|
|
- 800fbc0: 460a mov r2, r1
|
|
|
- 800fbc2: 4628 mov r0, r5
|
|
|
- 800fbc4: f7fa f983 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 800fb36: 2107 movs r1, #7
|
|
|
+ 800fb38: 460a mov r2, r1
|
|
|
+ 800fb3a: 4628 mov r0, r5
|
|
|
+ 800fb3c: f7fa f9c7 bl 8009ece <GPIO_PinAFConfig>
|
|
|
|
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
|
|
- 800fbc8: f44f 33e1 mov.w r3, #115200 ; 0x1c200
|
|
|
- 800fbcc: 9302 str r3, [sp, #8]
|
|
|
+ 800fb40: f44f 33e1 mov.w r3, #115200 ; 0x1c200
|
|
|
+ 800fb44: 9302 str r3, [sp, #8]
|
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
|
|
- 800fbce: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
|
+ 800fb46: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
|
|
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
|
|
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
|
|
USART_Init(USER_USART, &USART_InitStructure);
|
|
|
- 800fbd2: f5a5 4574 sub.w r5, r5, #62464 ; 0xf400
|
|
|
+ 800fb4a: f5a5 4574 sub.w r5, r5, #62464 ; 0xf400
|
|
|
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_USART1);
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_USART1);
|
|
|
|
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
|
|
- 800fbd6: f8ad 300c strh.w r3, [sp, #12]
|
|
|
+ 800fb4e: f8ad 300c strh.w r3, [sp, #12]
|
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
|
|
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
|
|
- 800fbda: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
|
- 800fbde: f8ad 3010 strh.w r3, [sp, #16]
|
|
|
+ 800fb52: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
|
+ 800fb56: f8ad 3010 strh.w r3, [sp, #16]
|
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
|
|
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
|
|
USART_Init(USER_USART, &USART_InitStructure);
|
|
|
- 800fbe2: 4628 mov r0, r5
|
|
|
+ 800fb5a: 4628 mov r0, r5
|
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
|
|
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
|
|
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
|
|
- 800fbe4: 230c movs r3, #12
|
|
|
+ 800fb5c: 230c movs r3, #12
|
|
|
USART_Init(USER_USART, &USART_InitStructure);
|
|
|
- 800fbe6: a902 add r1, sp, #8
|
|
|
+ 800fb5e: a902 add r1, sp, #8
|
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
|
|
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
|
|
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
|
|
- 800fbe8: f8ad 3012 strh.w r3, [sp, #18]
|
|
|
+ 800fb60: f8ad 3012 strh.w r3, [sp, #18]
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_USART1);
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_USART1);
|
|
|
|
|
|
USART_InitStructure.USART_BaudRate = 115200;
|
|
|
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
|
|
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
|
|
- 800fbec: f8ad 400e strh.w r4, [sp, #14]
|
|
|
+ 800fb64: f8ad 400e strh.w r4, [sp, #14]
|
|
|
USART_InitStructure.USART_Parity = USART_Parity_Even;
|
|
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
|
|
- 800fbf0: f8ad 4014 strh.w r4, [sp, #20]
|
|
|
+ 800fb68: f8ad 4014 strh.w r4, [sp, #20]
|
|
|
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
|
|
USART_Init(USER_USART, &USART_InitStructure);
|
|
|
- 800fbf4: f7fa fa7a bl 800a0ec <USART_Init>
|
|
|
+ 800fb6c: f7fa fabe bl 800a0ec <USART_Init>
|
|
|
|
|
|
USART_Cmd(USER_USART, ENABLE);
|
|
|
- 800fbf8: 4628 mov r0, r5
|
|
|
- 800fbfa: 4631 mov r1, r6
|
|
|
- 800fbfc: f7fa fad0 bl 800a1a0 <USART_Cmd>
|
|
|
+ 800fb70: 4628 mov r0, r5
|
|
|
+ 800fb72: 4631 mov r1, r6
|
|
|
+ 800fb74: f7fa fb14 bl 800a1a0 <USART_Cmd>
|
|
|
|
|
|
|
|
|
USART_ITConfig(USER_USART, USART_IT_RXNE, DISABLE);
|
|
|
- 800fc00: 4628 mov r0, r5
|
|
|
- 800fc02: 4622 mov r2, r4
|
|
|
- 800fc04: f240 5125 movw r1, #1317 ; 0x525
|
|
|
- 800fc08: f7fa fad6 bl 800a1b8 <USART_ITConfig>
|
|
|
+ 800fb78: 4628 mov r0, r5
|
|
|
+ 800fb7a: 4622 mov r2, r4
|
|
|
+ 800fb7c: f240 5125 movw r1, #1317 ; 0x525
|
|
|
+ 800fb80: f7fa fb1a bl 800a1b8 <USART_ITConfig>
|
|
|
USART_ITConfig(USER_USART, USART_IT_TXE, DISABLE);
|
|
|
- 800fc0c: 4628 mov r0, r5
|
|
|
- 800fc0e: f240 7127 movw r1, #1831 ; 0x727
|
|
|
- 800fc12: 4622 mov r2, r4
|
|
|
- 800fc14: f7fa fad0 bl 800a1b8 <USART_ITConfig>
|
|
|
+ 800fb84: 4628 mov r0, r5
|
|
|
+ 800fb86: f240 7127 movw r1, #1831 ; 0x727
|
|
|
+ 800fb8a: 4622 mov r2, r4
|
|
|
+ 800fb8c: f7fa fb14 bl 800a1b8 <USART_ITConfig>
|
|
|
|
|
|
init_printf(NULL, putc_);
|
|
|
- 800fc18: 4620 mov r0, r4
|
|
|
- 800fc1a: 4903 ldr r1, [pc, #12] ; (800fc28 <InitUSART+0xac>)
|
|
|
- 800fc1c: f001 fd20 bl 8011660 <init_printf>
|
|
|
+ 800fb90: 4620 mov r0, r4
|
|
|
+ 800fb92: 4903 ldr r1, [pc, #12] ; (800fba0 <InitUSART+0xac>)
|
|
|
+ 800fb94: f001 fd20 bl 80115d8 <init_printf>
|
|
|
}
|
|
|
- 800fc20: b006 add sp, #24
|
|
|
- 800fc22: bd70 pop {r4, r5, r6, pc}
|
|
|
- 800fc24: 40020400 .word 0x40020400
|
|
|
- 800fc28: 0800fb79 .word 0x0800fb79
|
|
|
+ 800fb98: b006 add sp, #24
|
|
|
+ 800fb9a: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 800fb9c: 40020400 .word 0x40020400
|
|
|
+ 800fba0: 0800faf1 .word 0x0800faf1
|
|
|
|
|
|
-0800fc2c <WDG_Init>:
|
|
|
+0800fba4 <WDG_Init>:
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
void WDG_Init(void)
|
|
|
{
|
|
|
- 800fc2c: b530 push {r4, r5, lr}
|
|
|
+ 800fba4: b530 push {r4, r5, lr}
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
NVIC_InitTypeDef NVIC_InitStructure;
|
|
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
- 800fc2e: 2004 movs r0, #4
|
|
|
+ 800fba6: 2004 movs r0, #4
|
|
|
/**
|
|
|
* @brief
|
|
|
* @retval
|
|
|
*/
|
|
|
void WDG_Init(void)
|
|
|
{
|
|
|
- 800fc30: b087 sub sp, #28
|
|
|
+ 800fba8: b087 sub sp, #28
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
NVIC_InitTypeDef NVIC_InitStructure;
|
|
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
- 800fc32: 2101 movs r1, #1
|
|
|
- 800fc34: f7fa f9ae bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
+ 800fbaa: 2101 movs r1, #1
|
|
|
+ 800fbac: f7fa f9f2 bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
|
|
|
- 800fc38: 2080 movs r0, #128 ; 0x80
|
|
|
- 800fc3a: 2101 movs r1, #1
|
|
|
- 800fc3c: f7fa f9b6 bl 8009fac <RCC_APB1PeriphClockCmd>
|
|
|
+ 800fbb0: 2080 movs r0, #128 ; 0x80
|
|
|
+ 800fbb2: 2101 movs r1, #1
|
|
|
+ 800fbb4: f7fa f9fa bl 8009fac <RCC_APB1PeriphClockCmd>
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = WDT_PIN;
|
|
|
- 800fc40: 2401 movs r4, #1
|
|
|
+ 800fbb8: 2401 movs r4, #1
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 800fc42: 2500 movs r5, #0
|
|
|
+ 800fbba: 2500 movs r5, #0
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = WDT_PIN;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
- 800fc44: 2302 movs r3, #2
|
|
|
+ 800fbbc: 2302 movs r3, #2
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
|
|
- 800fc46: a901 add r1, sp, #4
|
|
|
- 800fc48: 481b ldr r0, [pc, #108] ; (800fcb8 <WDG_Init+0x8c>)
|
|
|
+ 800fbbe: a901 add r1, sp, #4
|
|
|
+ 800fbc0: 481b ldr r0, [pc, #108] ; (800fc30 <WDG_Init+0x8c>)
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = WDT_PIN;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
- 800fc4a: f88d 3009 strb.w r3, [sp, #9]
|
|
|
+ 800fbc2: f88d 3009 strb.w r3, [sp, #9]
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 800fc4e: f88d 500a strb.w r5, [sp, #10]
|
|
|
+ 800fbc6: f88d 500a strb.w r5, [sp, #10]
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
|
- 800fc52: f88d 500b strb.w r5, [sp, #11]
|
|
|
+ 800fbca: f88d 500b strb.w r5, [sp, #11]
|
|
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
|
|
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
|
|
|
|
|
|
GPIO_InitStructure.GPIO_Pin = WDT_PIN;
|
|
|
- 800fc56: 9401 str r4, [sp, #4]
|
|
|
+ 800fbce: 9401 str r4, [sp, #4]
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
- 800fc58: f88d 4008 strb.w r4, [sp, #8]
|
|
|
+ 800fbd0: f88d 4008 strb.w r4, [sp, #8]
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
|
|
- 800fc5c: f7fa f8e8 bl 8009e30 <GPIO_Init>
|
|
|
+ 800fbd4: f7fa f92c bl 8009e30 <GPIO_Init>
|
|
|
|
|
|
NVIC_InitStructure.NVIC_IRQChannel = TIM8_UP_TIM13_IRQn;
|
|
|
- 800fc60: 232c movs r3, #44 ; 0x2c
|
|
|
- 800fc62: f88d 3000 strb.w r3, [sp]
|
|
|
+ 800fbd8: 232c movs r3, #44 ; 0x2c
|
|
|
+ 800fbda: f88d 3000 strb.w r3, [sp]
|
|
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x6;
|
|
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
|
|
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
|
NVIC_Init(&NVIC_InitStructure);
|
|
|
- 800fc66: 4668 mov r0, sp
|
|
|
+ 800fbde: 4668 mov r0, sp
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
|
|
|
|
|
NVIC_InitStructure.NVIC_IRQChannel = TIM8_UP_TIM13_IRQn;
|
|
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x6;
|
|
|
- 800fc68: 2306 movs r3, #6
|
|
|
- 800fc6a: f88d 3001 strb.w r3, [sp, #1]
|
|
|
+ 800fbe0: 2306 movs r3, #6
|
|
|
+ 800fbe2: f88d 3001 strb.w r3, [sp, #1]
|
|
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0;
|
|
|
- 800fc6e: f88d 5002 strb.w r5, [sp, #2]
|
|
|
+ 800fbe6: f88d 5002 strb.w r5, [sp, #2]
|
|
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
|
|
- 800fc72: f88d 4003 strb.w r4, [sp, #3]
|
|
|
+ 800fbea: f88d 4003 strb.w r4, [sp, #3]
|
|
|
NVIC_Init(&NVIC_InitStructure);
|
|
|
- 800fc76: f7f9 ffe1 bl 8009c3c <NVIC_Init>
|
|
|
+ 800fbee: f7fa f825 bl 8009c3c <NVIC_Init>
|
|
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
{
|
|
|
if(IRQn < 0) {
|
|
|
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
|
|
|
else {
|
|
|
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
|
|
|
- 800fc7a: 4b10 ldr r3, [pc, #64] ; (800fcbc <WDG_Init+0x90>)
|
|
|
- 800fc7c: 2220 movs r2, #32
|
|
|
- 800fc7e: f883 232c strb.w r2, [r3, #812] ; 0x32c
|
|
|
+ 800fbf2: 4b10 ldr r3, [pc, #64] ; (800fc34 <WDG_Init+0x90>)
|
|
|
+ 800fbf4: 2220 movs r2, #32
|
|
|
+ 800fbf6: f883 232c strb.w r2, [r3, #812] ; 0x32c
|
|
|
|
|
|
/* APB1 Timer clock is 60Mhz, configure timer clock to 10khz (1 update event per 100 us) */
|
|
|
TIM_TimeBaseStructure.TIM_Prescaler = 6000 - 1;
|
|
|
/* Configure timer period to 100ms */
|
|
|
TIM_TimeBaseStructure.TIM_Period = 1000;
|
|
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
|
|
- 800fc82: f8ad 5014 strh.w r5, [sp, #20]
|
|
|
+ 800fbfa: f8ad 5014 strh.w r5, [sp, #20]
|
|
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
|
|
- 800fc86: f8ad 500e strh.w r5, [sp, #14]
|
|
|
+ 800fbfe: f8ad 500e strh.w r5, [sp, #14]
|
|
|
TIM_TimeBaseInit(TIM13, &TIM_TimeBaseStructure);
|
|
|
- 800fc8a: 4d0d ldr r5, [pc, #52] ; (800fcc0 <WDG_Init+0x94>)
|
|
|
+ 800fc02: 4d0d ldr r5, [pc, #52] ; (800fc38 <WDG_Init+0x94>)
|
|
|
NVIC_Init(&NVIC_InitStructure);
|
|
|
|
|
|
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 2);
|
|
|
|
|
|
/* APB1 Timer clock is 60Mhz, configure timer clock to 10khz (1 update event per 100 us) */
|
|
|
TIM_TimeBaseStructure.TIM_Prescaler = 6000 - 1;
|
|
|
- 800fc8c: f241 736f movw r3, #5999 ; 0x176f
|
|
|
- 800fc90: f8ad 300c strh.w r3, [sp, #12]
|
|
|
+ 800fc04: f241 736f movw r3, #5999 ; 0x176f
|
|
|
+ 800fc08: f8ad 300c strh.w r3, [sp, #12]
|
|
|
/* Configure timer period to 100ms */
|
|
|
TIM_TimeBaseStructure.TIM_Period = 1000;
|
|
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
|
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
|
|
TIM_TimeBaseInit(TIM13, &TIM_TimeBaseStructure);
|
|
|
- 800fc94: 4628 mov r0, r5
|
|
|
+ 800fc0c: 4628 mov r0, r5
|
|
|
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 2);
|
|
|
|
|
|
/* APB1 Timer clock is 60Mhz, configure timer clock to 10khz (1 update event per 100 us) */
|
|
|
TIM_TimeBaseStructure.TIM_Prescaler = 6000 - 1;
|
|
|
/* Configure timer period to 100ms */
|
|
|
TIM_TimeBaseStructure.TIM_Period = 1000;
|
|
|
- 800fc96: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
|
+ 800fc0e: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
|
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
|
|
TIM_TimeBaseInit(TIM13, &TIM_TimeBaseStructure);
|
|
|
- 800fc9a: a903 add r1, sp, #12
|
|
|
+ 800fc12: a903 add r1, sp, #12
|
|
|
NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 2);
|
|
|
|
|
|
/* APB1 Timer clock is 60Mhz, configure timer clock to 10khz (1 update event per 100 us) */
|
|
|
TIM_TimeBaseStructure.TIM_Prescaler = 6000 - 1;
|
|
|
/* Configure timer period to 100ms */
|
|
|
TIM_TimeBaseStructure.TIM_Period = 1000;
|
|
|
- 800fc9c: 9304 str r3, [sp, #16]
|
|
|
+ 800fc14: 9304 str r3, [sp, #16]
|
|
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
|
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
|
|
TIM_TimeBaseInit(TIM13, &TIM_TimeBaseStructure);
|
|
|
- 800fc9e: f7fa f9cf bl 800a040 <TIM_TimeBaseInit>
|
|
|
+ 800fc16: f7fa fa13 bl 800a040 <TIM_TimeBaseInit>
|
|
|
|
|
|
TIM_Cmd(TIM13, ENABLE);
|
|
|
- 800fca2: 4628 mov r0, r5
|
|
|
- 800fca4: 4621 mov r1, r4
|
|
|
- 800fca6: f7fa fa09 bl 800a0bc <TIM_Cmd>
|
|
|
+ 800fc1a: 4628 mov r0, r5
|
|
|
+ 800fc1c: 4621 mov r1, r4
|
|
|
+ 800fc1e: f7fa fa4d bl 800a0bc <TIM_Cmd>
|
|
|
TIM_ITConfig(TIM13, TIM_IT_Update, ENABLE);
|
|
|
- 800fcaa: 4628 mov r0, r5
|
|
|
- 800fcac: 4621 mov r1, r4
|
|
|
- 800fcae: 4622 mov r2, r4
|
|
|
- 800fcb0: f7fa fa10 bl 800a0d4 <TIM_ITConfig>
|
|
|
+ 800fc22: 4628 mov r0, r5
|
|
|
+ 800fc24: 4621 mov r1, r4
|
|
|
+ 800fc26: 4622 mov r2, r4
|
|
|
+ 800fc28: f7fa fa54 bl 800a0d4 <TIM_ITConfig>
|
|
|
|
|
|
}
|
|
|
- 800fcb4: b007 add sp, #28
|
|
|
- 800fcb6: bd30 pop {r4, r5, pc}
|
|
|
- 800fcb8: 40020800 .word 0x40020800
|
|
|
- 800fcbc: e000e100 .word 0xe000e100
|
|
|
- 800fcc0: 40001c00 .word 0x40001c00
|
|
|
+ 800fc2c: b007 add sp, #28
|
|
|
+ 800fc2e: bd30 pop {r4, r5, pc}
|
|
|
+ 800fc30: 40020800 .word 0x40020800
|
|
|
+ 800fc34: e000e100 .word 0xe000e100
|
|
|
+ 800fc38: 40001c00 .word 0x40001c00
|
|
|
|
|
|
-0800fcc4 <TIM8_UP_TIM13_IRQHandler>:
|
|
|
+0800fc3c <TIM8_UP_TIM13_IRQHandler>:
|
|
|
/**
|
|
|
* @brief Дергаем пином (сброс внешнего WDT)
|
|
|
* @retval
|
|
|
*/
|
|
|
void TIM8_UP_TIM13_IRQHandler(void)
|
|
|
{
|
|
|
- 800fcc4: b508 push {r3, lr}
|
|
|
+ 800fc3c: b508 push {r3, lr}
|
|
|
TIM_ClearITPendingBit(TIM13, TIM_IT_Update);
|
|
|
- 800fcc6: 4805 ldr r0, [pc, #20] ; (800fcdc <TIM8_UP_TIM13_IRQHandler+0x18>)
|
|
|
- 800fcc8: 2101 movs r1, #1
|
|
|
- 800fcca: f7fa fa0c bl 800a0e6 <TIM_ClearITPendingBit>
|
|
|
+ 800fc3e: 4805 ldr r0, [pc, #20] ; (800fc54 <TIM8_UP_TIM13_IRQHandler+0x18>)
|
|
|
+ 800fc40: 2101 movs r1, #1
|
|
|
+ 800fc42: f7fa fa50 bl 800a0e6 <TIM_ClearITPendingBit>
|
|
|
GPIOC->ODR ^= WDT_PIN;
|
|
|
- 800fcce: 4b04 ldr r3, [pc, #16] ; (800fce0 <TIM8_UP_TIM13_IRQHandler+0x1c>)
|
|
|
- 800fcd0: 695a ldr r2, [r3, #20]
|
|
|
- 800fcd2: f082 0201 eor.w r2, r2, #1
|
|
|
- 800fcd6: 615a str r2, [r3, #20]
|
|
|
- 800fcd8: bd08 pop {r3, pc}
|
|
|
- 800fcda: bf00 nop
|
|
|
- 800fcdc: 40001c00 .word 0x40001c00
|
|
|
- 800fce0: 40020800 .word 0x40020800
|
|
|
-
|
|
|
-0800fce4 <http_accept>:
|
|
|
+ 800fc46: 4b04 ldr r3, [pc, #16] ; (800fc58 <TIM8_UP_TIM13_IRQHandler+0x1c>)
|
|
|
+ 800fc48: 695a ldr r2, [r3, #20]
|
|
|
+ 800fc4a: f082 0201 eor.w r2, r2, #1
|
|
|
+ 800fc4e: 615a str r2, [r3, #20]
|
|
|
+ 800fc50: bd08 pop {r3, pc}
|
|
|
+ 800fc52: bf00 nop
|
|
|
+ 800fc54: 40001c00 .word 0x40001c00
|
|
|
+ 800fc58: 40020800 .word 0x40020800
|
|
|
+
|
|
|
+0800fc5c <http_accept>:
|
|
|
* @param pcb: pointer to a tcp_pcb structure
|
|
|
* ¶m err: Lwip stack error code
|
|
|
* @retval err
|
|
|
*/
|
|
|
static err_t http_accept(void *arg, struct tcp_pcb *pcb, err_t err)
|
|
|
{
|
|
|
- 800fce4: b538 push {r3, r4, r5, lr}
|
|
|
+ 800fc5c: b538 push {r3, r4, r5, lr}
|
|
|
struct http_state *hs;
|
|
|
|
|
|
/* Allocate memory for the structure that holds the state of the connection */
|
|
|
hs = mem_malloc(sizeof(struct http_state));
|
|
|
- 800fce6: 2008 movs r0, #8
|
|
|
+ 800fc5e: 2008 movs r0, #8
|
|
|
* @param pcb: pointer to a tcp_pcb structure
|
|
|
* ¶m err: Lwip stack error code
|
|
|
* @retval err
|
|
|
*/
|
|
|
static err_t http_accept(void *arg, struct tcp_pcb *pcb, err_t err)
|
|
|
{
|
|
|
- 800fce8: 460c mov r4, r1
|
|
|
+ 800fc60: 460c mov r4, r1
|
|
|
struct http_state *hs;
|
|
|
|
|
|
/* Allocate memory for the structure that holds the state of the connection */
|
|
|
hs = mem_malloc(sizeof(struct http_state));
|
|
|
- 800fcea: f7fb fa0f bl 800b10c <mem_malloc>
|
|
|
+ 800fc62: f7fb fa53 bl 800b10c <mem_malloc>
|
|
|
|
|
|
if (hs == NULL)
|
|
|
- 800fcee: 4601 mov r1, r0
|
|
|
- 800fcf0: b1a0 cbz r0, 800fd1c <http_accept+0x38>
|
|
|
+ 800fc66: 4601 mov r1, r0
|
|
|
+ 800fc68: b1a0 cbz r0, 800fc94 <http_accept+0x38>
|
|
|
{
|
|
|
return ERR_MEM;
|
|
|
}
|
|
|
|
|
|
/* Initialize the structure. */
|
|
|
hs->file = NULL;
|
|
|
- 800fcf2: 2500 movs r5, #0
|
|
|
- 800fcf4: 6005 str r5, [r0, #0]
|
|
|
+ 800fc6a: 2500 movs r5, #0
|
|
|
+ 800fc6c: 6005 str r5, [r0, #0]
|
|
|
hs->left = 0;
|
|
|
- 800fcf6: 6045 str r5, [r0, #4]
|
|
|
+ 800fc6e: 6045 str r5, [r0, #4]
|
|
|
|
|
|
/* Tell TCP that this is the structure we wish to be passed for our
|
|
|
callbacks. */
|
|
|
tcp_arg(pcb, hs);
|
|
|
- 800fcf8: 4620 mov r0, r4
|
|
|
- 800fcfa: f7fb fea5 bl 800ba48 <tcp_arg>
|
|
|
+ 800fc70: 4620 mov r0, r4
|
|
|
+ 800fc72: f7fb fee9 bl 800ba48 <tcp_arg>
|
|
|
|
|
|
/* Tell TCP that we wish to be informed of incoming data by a call
|
|
|
to the http_recv() function. */
|
|
|
tcp_recv(pcb, http_recv);
|
|
|
- 800fcfe: 4620 mov r0, r4
|
|
|
- 800fd00: 4908 ldr r1, [pc, #32] ; (800fd24 <http_accept+0x40>)
|
|
|
- 800fd02: f7fb fea3 bl 800ba4c <tcp_recv>
|
|
|
+ 800fc76: 4620 mov r0, r4
|
|
|
+ 800fc78: 4908 ldr r1, [pc, #32] ; (800fc9c <http_accept+0x40>)
|
|
|
+ 800fc7a: f7fb fee7 bl 800ba4c <tcp_recv>
|
|
|
|
|
|
tcp_err(pcb, conn_err);
|
|
|
- 800fd06: 4620 mov r0, r4
|
|
|
- 800fd08: 4907 ldr r1, [pc, #28] ; (800fd28 <http_accept+0x44>)
|
|
|
- 800fd0a: f7fb fea3 bl 800ba54 <tcp_err>
|
|
|
+ 800fc7e: 4620 mov r0, r4
|
|
|
+ 800fc80: 4907 ldr r1, [pc, #28] ; (800fca0 <http_accept+0x44>)
|
|
|
+ 800fc82: f7fb fee7 bl 800ba54 <tcp_err>
|
|
|
|
|
|
tcp_poll(pcb, http_poll, 10);
|
|
|
- 800fd0e: 4620 mov r0, r4
|
|
|
- 800fd10: 4906 ldr r1, [pc, #24] ; (800fd2c <http_accept+0x48>)
|
|
|
- 800fd12: 220a movs r2, #10
|
|
|
- 800fd14: f7fb fea3 bl 800ba5e <tcp_poll>
|
|
|
+ 800fc86: 4620 mov r0, r4
|
|
|
+ 800fc88: 4906 ldr r1, [pc, #24] ; (800fca4 <http_accept+0x48>)
|
|
|
+ 800fc8a: 220a movs r2, #10
|
|
|
+ 800fc8c: f7fb fee7 bl 800ba5e <tcp_poll>
|
|
|
return ERR_OK;
|
|
|
- 800fd18: 4628 mov r0, r5
|
|
|
- 800fd1a: e000 b.n 800fd1e <http_accept+0x3a>
|
|
|
+ 800fc90: 4628 mov r0, r5
|
|
|
+ 800fc92: e000 b.n 800fc96 <http_accept+0x3a>
|
|
|
/* Allocate memory for the structure that holds the state of the connection */
|
|
|
hs = mem_malloc(sizeof(struct http_state));
|
|
|
|
|
|
if (hs == NULL)
|
|
|
{
|
|
|
return ERR_MEM;
|
|
|
- 800fd1c: 20ff movs r0, #255 ; 0xff
|
|
|
+ 800fc94: 20ff movs r0, #255 ; 0xff
|
|
|
|
|
|
tcp_err(pcb, conn_err);
|
|
|
|
|
|
tcp_poll(pcb, http_poll, 10);
|
|
|
return ERR_OK;
|
|
|
}
|
|
|
- 800fd1e: b240 sxtb r0, r0
|
|
|
- 800fd20: bd38 pop {r3, r4, r5, pc}
|
|
|
- 800fd22: bf00 nop
|
|
|
- 800fd24: 0800fe79 .word 0x0800fe79
|
|
|
- 800fd28: 0800fd73 .word 0x0800fd73
|
|
|
- 800fd2c: 0800fd5b .word 0x0800fd5b
|
|
|
-
|
|
|
-0800fd30 <send_data>:
|
|
|
+ 800fc96: b240 sxtb r0, r0
|
|
|
+ 800fc98: bd38 pop {r3, r4, r5, pc}
|
|
|
+ 800fc9a: bf00 nop
|
|
|
+ 800fc9c: 0800fdf1 .word 0x0800fdf1
|
|
|
+ 800fca0: 0800fceb .word 0x0800fceb
|
|
|
+ 800fca4: 0800fcd3 .word 0x0800fcd3
|
|
|
+
|
|
|
+0800fca8 <send_data>:
|
|
|
* @param pcb: pointer to a tcp_pcb struct
|
|
|
* @param hs: pointer to a http_state struct
|
|
|
* @retval none
|
|
|
*/
|
|
|
static void send_data(struct tcp_pcb *pcb, struct http_state *hs)
|
|
|
{
|
|
|
- 800fd30: b538 push {r3, r4, r5, lr}
|
|
|
+ 800fca8: b538 push {r3, r4, r5, lr}
|
|
|
err_t err;
|
|
|
u16_t len;
|
|
|
|
|
|
/* We cannot send more data than space available in the send
|
|
|
buffer */
|
|
|
if (tcp_sndbuf(pcb) < hs->left)
|
|
|
- 800fd32: 684b ldr r3, [r1, #4]
|
|
|
- 800fd34: f8b0 5066 ldrh.w r5, [r0, #102] ; 0x66
|
|
|
- 800fd38: 429d cmp r5, r3
|
|
|
+ 800fcaa: 684b ldr r3, [r1, #4]
|
|
|
+ 800fcac: f8b0 5066 ldrh.w r5, [r0, #102] ; 0x66
|
|
|
+ 800fcb0: 429d cmp r5, r3
|
|
|
{
|
|
|
len = tcp_sndbuf(pcb);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
len = hs->left;
|
|
|
- 800fd3a: bf28 it cs
|
|
|
- 800fd3c: b29d uxthcs r5, r3
|
|
|
+ 800fcb2: bf28 it cs
|
|
|
+ 800fcb4: b29d uxthcs r5, r3
|
|
|
* @param pcb: pointer to a tcp_pcb struct
|
|
|
* @param hs: pointer to a http_state struct
|
|
|
* @retval none
|
|
|
*/
|
|
|
static void send_data(struct tcp_pcb *pcb, struct http_state *hs)
|
|
|
{
|
|
|
- 800fd3e: 460c mov r4, r1
|
|
|
+ 800fcb6: 460c mov r4, r1
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
len = hs->left;
|
|
|
}
|
|
|
err = tcp_write(pcb, hs->file, len, 0);
|
|
|
- 800fd40: 462a mov r2, r5
|
|
|
- 800fd42: 6809 ldr r1, [r1, #0]
|
|
|
- 800fd44: 2300 movs r3, #0
|
|
|
- 800fd46: f7fd fa41 bl 800d1cc <tcp_write>
|
|
|
+ 800fcb8: 462a mov r2, r5
|
|
|
+ 800fcba: 6809 ldr r1, [r1, #0]
|
|
|
+ 800fcbc: 2300 movs r3, #0
|
|
|
+ 800fcbe: f7fd fa85 bl 800d1cc <tcp_write>
|
|
|
if (err == ERR_OK)
|
|
|
- 800fd4a: b928 cbnz r0, 800fd58 <send_data+0x28>
|
|
|
+ 800fcc2: b928 cbnz r0, 800fcd0 <send_data+0x28>
|
|
|
{
|
|
|
hs->file += len;
|
|
|
- 800fd4c: 6823 ldr r3, [r4, #0]
|
|
|
- 800fd4e: 195b adds r3, r3, r5
|
|
|
- 800fd50: 6023 str r3, [r4, #0]
|
|
|
+ 800fcc4: 6823 ldr r3, [r4, #0]
|
|
|
+ 800fcc6: 195b adds r3, r3, r5
|
|
|
+ 800fcc8: 6023 str r3, [r4, #0]
|
|
|
hs->left -= len;
|
|
|
- 800fd52: 6863 ldr r3, [r4, #4]
|
|
|
- 800fd54: 1b5d subs r5, r3, r5
|
|
|
- 800fd56: 6065 str r5, [r4, #4]
|
|
|
- 800fd58: bd38 pop {r3, r4, r5, pc}
|
|
|
+ 800fcca: 6863 ldr r3, [r4, #4]
|
|
|
+ 800fccc: 1b5d subs r5, r3, r5
|
|
|
+ 800fcce: 6065 str r5, [r4, #4]
|
|
|
+ 800fcd0: bd38 pop {r3, r4, r5, pc}
|
|
|
|
|
|
-0800fd5a <http_poll>:
|
|
|
+0800fcd2 <http_poll>:
|
|
|
* @param arg: pointer to an argument to be passed to callback function
|
|
|
* @param pcb: pointer on tcp_pcb structure
|
|
|
* @retval err_t
|
|
|
*/
|
|
|
static err_t http_poll(void *arg, struct tcp_pcb *pcb)
|
|
|
{
|
|
|
- 800fd5a: b508 push {r3, lr}
|
|
|
+ 800fcd2: b508 push {r3, lr}
|
|
|
if (arg == NULL)
|
|
|
- 800fd5c: 4603 mov r3, r0
|
|
|
+ 800fcd4: 4603 mov r3, r0
|
|
|
{
|
|
|
tcp_close(pcb);
|
|
|
- 800fd5e: 4608 mov r0, r1
|
|
|
+ 800fcd6: 4608 mov r0, r1
|
|
|
* @param pcb: pointer on tcp_pcb structure
|
|
|
* @retval err_t
|
|
|
*/
|
|
|
static err_t http_poll(void *arg, struct tcp_pcb *pcb)
|
|
|
{
|
|
|
if (arg == NULL)
|
|
|
- 800fd60: b913 cbnz r3, 800fd68 <http_poll+0xe>
|
|
|
+ 800fcd8: b913 cbnz r3, 800fce0 <http_poll+0xe>
|
|
|
{
|
|
|
tcp_close(pcb);
|
|
|
- 800fd62: f7fc f9cb bl 800c0fc <tcp_close>
|
|
|
- 800fd66: e002 b.n 800fd6e <http_poll+0x14>
|
|
|
+ 800fcda: f7fc fa0f bl 800c0fc <tcp_close>
|
|
|
+ 800fcde: e002 b.n 800fce6 <http_poll+0x14>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
send_data(pcb, (struct http_state *)arg);
|
|
|
- 800fd68: 4619 mov r1, r3
|
|
|
- 800fd6a: f7ff ffe1 bl 800fd30 <send_data>
|
|
|
+ 800fce0: 4619 mov r1, r3
|
|
|
+ 800fce2: f7ff ffe1 bl 800fca8 <send_data>
|
|
|
}
|
|
|
return ERR_OK;
|
|
|
}
|
|
|
- 800fd6e: 2000 movs r0, #0
|
|
|
- 800fd70: bd08 pop {r3, pc}
|
|
|
+ 800fce6: 2000 movs r0, #0
|
|
|
+ 800fce8: bd08 pop {r3, pc}
|
|
|
|
|
|
-0800fd72 <conn_err>:
|
|
|
+0800fcea <conn_err>:
|
|
|
static void conn_err(void *arg, err_t err)
|
|
|
{
|
|
|
struct http_state *hs;
|
|
|
|
|
|
hs = arg;
|
|
|
mem_free(hs);
|
|
|
- 800fd72: f7fb b905 b.w 800af80 <mem_free>
|
|
|
- 800fd76: 0000 movs r0, r0
|
|
|
+ 800fcea: f7fb b949 b.w 800af80 <mem_free>
|
|
|
+ 800fcee: 0000 movs r0, r0
|
|
|
|
|
|
-0800fd78 <close_conn>:
|
|
|
+0800fcf0 <close_conn>:
|
|
|
* @param pcb: pointer to a tcp_pcb struct
|
|
|
* @param hs: pointer to a http_state struct
|
|
|
* @retval
|
|
|
*/
|
|
|
static void close_conn(struct tcp_pcb *pcb, struct http_state *hs)
|
|
|
{
|
|
|
- 800fd78: b538 push {r3, r4, r5, lr}
|
|
|
- 800fd7a: 4604 mov r4, r0
|
|
|
- 800fd7c: 460d mov r5, r1
|
|
|
+ 800fcf0: b538 push {r3, r4, r5, lr}
|
|
|
+ 800fcf2: 4604 mov r4, r0
|
|
|
+ 800fcf4: 460d mov r5, r1
|
|
|
tcp_arg(pcb, NULL);
|
|
|
- 800fd7e: 2100 movs r1, #0
|
|
|
- 800fd80: f7fb fe62 bl 800ba48 <tcp_arg>
|
|
|
+ 800fcf6: 2100 movs r1, #0
|
|
|
+ 800fcf8: f7fb fea6 bl 800ba48 <tcp_arg>
|
|
|
tcp_sent(pcb, NULL);
|
|
|
- 800fd84: 4620 mov r0, r4
|
|
|
- 800fd86: 2100 movs r1, #0
|
|
|
- 800fd88: f7fb fe62 bl 800ba50 <tcp_sent>
|
|
|
+ 800fcfc: 4620 mov r0, r4
|
|
|
+ 800fcfe: 2100 movs r1, #0
|
|
|
+ 800fd00: f7fb fea6 bl 800ba50 <tcp_sent>
|
|
|
tcp_recv(pcb, NULL);
|
|
|
- 800fd8c: 2100 movs r1, #0
|
|
|
- 800fd8e: 4620 mov r0, r4
|
|
|
- 800fd90: f7fb fe5c bl 800ba4c <tcp_recv>
|
|
|
+ 800fd04: 2100 movs r1, #0
|
|
|
+ 800fd06: 4620 mov r0, r4
|
|
|
+ 800fd08: f7fb fea0 bl 800ba4c <tcp_recv>
|
|
|
mem_free(hs);
|
|
|
- 800fd94: 4628 mov r0, r5
|
|
|
- 800fd96: f7fb f8f3 bl 800af80 <mem_free>
|
|
|
+ 800fd0c: 4628 mov r0, r5
|
|
|
+ 800fd0e: f7fb f937 bl 800af80 <mem_free>
|
|
|
tcp_close(pcb);
|
|
|
- 800fd9a: 4620 mov r0, r4
|
|
|
- 800fd9c: f7fc f9ae bl 800c0fc <tcp_close>
|
|
|
+ 800fd12: 4620 mov r0, r4
|
|
|
+ 800fd14: f7fc f9f2 bl 800c0fc <tcp_close>
|
|
|
|
|
|
reqCounter++;
|
|
|
- 800fda0: 4b02 ldr r3, [pc, #8] ; (800fdac <close_conn+0x34>)
|
|
|
- 800fda2: 781a ldrb r2, [r3, #0]
|
|
|
- 800fda4: 3201 adds r2, #1
|
|
|
- 800fda6: 701a strb r2, [r3, #0]
|
|
|
- 800fda8: bd38 pop {r3, r4, r5, pc}
|
|
|
- 800fdaa: bf00 nop
|
|
|
- 800fdac: 20006d82 .word 0x20006d82
|
|
|
-
|
|
|
-0800fdb0 <fs_open>:
|
|
|
+ 800fd18: 4b02 ldr r3, [pc, #8] ; (800fd24 <close_conn+0x34>)
|
|
|
+ 800fd1a: 781a ldrb r2, [r3, #0]
|
|
|
+ 800fd1c: 3201 adds r2, #1
|
|
|
+ 800fd1e: 701a strb r2, [r3, #0]
|
|
|
+ 800fd20: bd38 pop {r3, r4, r5, pc}
|
|
|
+ 800fd22: bf00 nop
|
|
|
+ 800fd24: 20006d82 .word 0x20006d82
|
|
|
+
|
|
|
+0800fd28 <fs_open>:
|
|
|
* @param name : pointer to a file name
|
|
|
* @param file : pointer to a fs_file structure
|
|
|
* @retval 1 if success, 0 if fail
|
|
|
*/
|
|
|
static int fs_open(char *name, struct fs_file *file)
|
|
|
{
|
|
|
- 800fdb0: b570 push {r4, r5, r6, lr}
|
|
|
+ 800fd28: b570 push {r4, r5, r6, lr}
|
|
|
struct fsdata_file_noconst *f;
|
|
|
|
|
|
for (f = (struct fsdata_file_noconst *)FS_ROOT; f != NULL; f = (struct fsdata_file_noconst *)f->next)
|
|
|
- 800fdb2: 4c09 ldr r4, [pc, #36] ; (800fdd8 <fs_open+0x28>)
|
|
|
+ 800fd2a: 4c09 ldr r4, [pc, #36] ; (800fd50 <fs_open+0x28>)
|
|
|
* @param name : pointer to a file name
|
|
|
* @param file : pointer to a fs_file structure
|
|
|
* @retval 1 if success, 0 if fail
|
|
|
*/
|
|
|
static int fs_open(char *name, struct fs_file *file)
|
|
|
{
|
|
|
- 800fdb4: 4606 mov r6, r0
|
|
|
- 800fdb6: 460d mov r5, r1
|
|
|
+ 800fd2c: 4606 mov r6, r0
|
|
|
+ 800fd2e: 460d mov r5, r1
|
|
|
struct fsdata_file_noconst *f;
|
|
|
|
|
|
for (f = (struct fsdata_file_noconst *)FS_ROOT; f != NULL; f = (struct fsdata_file_noconst *)f->next)
|
|
|
{
|
|
|
if (!strcmp(name, f->name))
|
|
|
- 800fdb8: 4630 mov r0, r6
|
|
|
- 800fdba: 6861 ldr r1, [r4, #4]
|
|
|
- 800fdbc: f7f9 fc42 bl 8009644 <strcmp>
|
|
|
- 800fdc0: b928 cbnz r0, 800fdce <fs_open+0x1e>
|
|
|
+ 800fd30: 4630 mov r0, r6
|
|
|
+ 800fd32: 6861 ldr r1, [r4, #4]
|
|
|
+ 800fd34: f7f9 fc86 bl 8009644 <strcmp>
|
|
|
+ 800fd38: b928 cbnz r0, 800fd46 <fs_open+0x1e>
|
|
|
{
|
|
|
file->data = f->data;
|
|
|
- 800fdc2: 68a3 ldr r3, [r4, #8]
|
|
|
- 800fdc4: 602b str r3, [r5, #0]
|
|
|
+ 800fd3a: 68a3 ldr r3, [r4, #8]
|
|
|
+ 800fd3c: 602b str r3, [r5, #0]
|
|
|
file->len = f->len;
|
|
|
- 800fdc6: 68e3 ldr r3, [r4, #12]
|
|
|
+ 800fd3e: 68e3 ldr r3, [r4, #12]
|
|
|
return 1;
|
|
|
- 800fdc8: 2001 movs r0, #1
|
|
|
+ 800fd40: 2001 movs r0, #1
|
|
|
for (f = (struct fsdata_file_noconst *)FS_ROOT; f != NULL; f = (struct fsdata_file_noconst *)f->next)
|
|
|
{
|
|
|
if (!strcmp(name, f->name))
|
|
|
{
|
|
|
file->data = f->data;
|
|
|
file->len = f->len;
|
|
|
- 800fdca: 606b str r3, [r5, #4]
|
|
|
+ 800fd42: 606b str r3, [r5, #4]
|
|
|
return 1;
|
|
|
- 800fdcc: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 800fd44: bd70 pop {r4, r5, r6, pc}
|
|
|
*/
|
|
|
static int fs_open(char *name, struct fs_file *file)
|
|
|
{
|
|
|
struct fsdata_file_noconst *f;
|
|
|
|
|
|
for (f = (struct fsdata_file_noconst *)FS_ROOT; f != NULL; f = (struct fsdata_file_noconst *)f->next)
|
|
|
- 800fdce: 6824 ldr r4, [r4, #0]
|
|
|
- 800fdd0: 2c00 cmp r4, #0
|
|
|
- 800fdd2: d1f1 bne.n 800fdb8 <fs_open+0x8>
|
|
|
+ 800fd46: 6824 ldr r4, [r4, #0]
|
|
|
+ 800fd48: 2c00 cmp r4, #0
|
|
|
+ 800fd4a: d1f1 bne.n 800fd30 <fs_open+0x8>
|
|
|
file->data = f->data;
|
|
|
file->len = f->len;
|
|
|
return 1;
|
|
|
}
|
|
|
}
|
|
|
return 0;
|
|
|
- 800fdd4: 4620 mov r0, r4
|
|
|
+ 800fd4c: 4620 mov r0, r4
|
|
|
}
|
|
|
- 800fdd6: bd70 pop {r4, r5, r6, pc}
|
|
|
- 800fdd8: 08012258 .word 0x08012258
|
|
|
+ 800fd4e: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 800fd50: 080121b8 .word 0x080121b8
|
|
|
|
|
|
-0800fddc <IAP_HTTP_writedata>:
|
|
|
+0800fd54 <IAP_HTTP_writedata>:
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
{
|
|
|
- 800fddc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
+ 800fd54: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
uint32_t count, i=0, j=0;
|
|
|
/* check if any left bytes from previous packet transfer*/
|
|
|
/* if it is the case do a concat with new data to create a 32-bit word */
|
|
|
if (LeftBytes)
|
|
|
- 800fdde: 4b21 ldr r3, [pc, #132] ; (800fe64 <IAP_HTTP_writedata+0x88>)
|
|
|
- 800fde0: 781a ldrb r2, [r3, #0]
|
|
|
+ 800fd56: 4b21 ldr r3, [pc, #132] ; (800fddc <IAP_HTTP_writedata+0x88>)
|
|
|
+ 800fd58: 781a ldrb r2, [r3, #0]
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
{
|
|
|
- 800fde2: 4606 mov r6, r0
|
|
|
- 800fde4: 460c mov r4, r1
|
|
|
+ 800fd5a: 4606 mov r6, r0
|
|
|
+ 800fd5c: 460c mov r4, r1
|
|
|
uint32_t count, i=0, j=0;
|
|
|
/* check if any left bytes from previous packet transfer*/
|
|
|
/* if it is the case do a concat with new data to create a 32-bit word */
|
|
|
if (LeftBytes)
|
|
|
- 800fde6: b94a cbnz r2, 800fdfc <IAP_HTTP_writedata+0x20>
|
|
|
- 800fde8: e01a b.n 800fe20 <IAP_HTTP_writedata+0x44>
|
|
|
+ 800fd5e: b94a cbnz r2, 800fd74 <IAP_HTTP_writedata+0x20>
|
|
|
+ 800fd60: e01a b.n 800fd98 <IAP_HTTP_writedata+0x44>
|
|
|
{
|
|
|
while(LeftBytes<=3)
|
|
|
{
|
|
|
if(len>(j+1))
|
|
|
- 800fdea: 3501 adds r5, #1
|
|
|
- 800fdec: 42ac cmp r4, r5
|
|
|
+ 800fd62: 3501 adds r5, #1
|
|
|
+ 800fd64: 42ac cmp r4, r5
|
|
|
* @brief writes received data in flash
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
- 800fdee: bf89 itett hi
|
|
|
- 800fdf0: 1977 addhi r7, r6, r5
|
|
|
+ 800fd66: bf89 itett hi
|
|
|
+ 800fd68: 1977 addhi r7, r6, r5
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = *(ptr+j);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = 0xFF;
|
|
|
- 800fdf2: 54c8 strbls r0, [r1, r3]
|
|
|
+ 800fd6a: 54c8 strbls r0, [r1, r3]
|
|
|
{
|
|
|
while(LeftBytes<=3)
|
|
|
{
|
|
|
if(len>(j+1))
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = *(ptr+j);
|
|
|
- 800fdf4: f817 7c01 ldrbhi.w r7, [r7, #-1]
|
|
|
- 800fdf8: 54cf strbhi r7, [r1, r3]
|
|
|
- 800fdfa: e002 b.n 800fe02 <IAP_HTTP_writedata+0x26>
|
|
|
- 800fdfc: 491a ldr r1, [pc, #104] ; (800fe68 <IAP_HTTP_writedata+0x8c>)
|
|
|
+ 800fd6c: f817 7c01 ldrbhi.w r7, [r7, #-1]
|
|
|
+ 800fd70: 54cf strbhi r7, [r1, r3]
|
|
|
+ 800fd72: e002 b.n 800fd7a <IAP_HTTP_writedata+0x26>
|
|
|
+ 800fd74: 491a ldr r1, [pc, #104] ; (800fde0 <IAP_HTTP_writedata+0x8c>)
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
{
|
|
|
uint32_t count, i=0, j=0;
|
|
|
/* check if any left bytes from previous packet transfer*/
|
|
|
/* if it is the case do a concat with new data to create a 32-bit word */
|
|
|
if (LeftBytes)
|
|
|
- 800fdfe: 2500 movs r5, #0
|
|
|
+ 800fd76: 2500 movs r5, #0
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = *(ptr+j);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = 0xFF;
|
|
|
- 800fe00: 20ff movs r0, #255 ; 0xff
|
|
|
+ 800fd78: 20ff movs r0, #255 ; 0xff
|
|
|
* @brief writes received data in flash
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
- 800fe02: 1953 adds r3, r2, r5
|
|
|
- 800fe04: b2db uxtb r3, r3
|
|
|
+ 800fd7a: 1953 adds r3, r2, r5
|
|
|
+ 800fd7c: b2db uxtb r3, r3
|
|
|
uint32_t count, i=0, j=0;
|
|
|
/* check if any left bytes from previous packet transfer*/
|
|
|
/* if it is the case do a concat with new data to create a 32-bit word */
|
|
|
if (LeftBytes)
|
|
|
{
|
|
|
while(LeftBytes<=3)
|
|
|
- 800fe06: 2b03 cmp r3, #3
|
|
|
- 800fe08: d9ef bls.n 800fdea <IAP_HTTP_writedata+0xe>
|
|
|
- 800fe0a: 4f16 ldr r7, [pc, #88] ; (800fe64 <IAP_HTTP_writedata+0x88>)
|
|
|
+ 800fd7e: 2b03 cmp r3, #3
|
|
|
+ 800fd80: d9ef bls.n 800fd62 <IAP_HTTP_writedata+0xe>
|
|
|
+ 800fd82: 4f16 ldr r7, [pc, #88] ; (800fddc <IAP_HTTP_writedata+0x88>)
|
|
|
{
|
|
|
LeftBytesTab[LeftBytes++] = 0xFF;
|
|
|
}
|
|
|
j++;
|
|
|
}
|
|
|
FLASH_If_Write(&FlashWriteAddress, (u32*)(LeftBytesTab),1);
|
|
|
- 800fe0c: 4817 ldr r0, [pc, #92] ; (800fe6c <IAP_HTTP_writedata+0x90>)
|
|
|
- 800fe0e: 4916 ldr r1, [pc, #88] ; (800fe68 <IAP_HTTP_writedata+0x8c>)
|
|
|
- 800fe10: 703b strb r3, [r7, #0]
|
|
|
- 800fe12: 2201 movs r2, #1
|
|
|
- 800fe14: f7ff fc4a bl 800f6ac <FLASH_If_Write>
|
|
|
+ 800fd84: 4817 ldr r0, [pc, #92] ; (800fde4 <IAP_HTTP_writedata+0x90>)
|
|
|
+ 800fd86: 4916 ldr r1, [pc, #88] ; (800fde0 <IAP_HTTP_writedata+0x8c>)
|
|
|
+ 800fd88: 703b strb r3, [r7, #0]
|
|
|
+ 800fd8a: 2201 movs r2, #1
|
|
|
+ 800fd8c: f7ff fc8e bl 800f6ac <FLASH_If_Write>
|
|
|
|
|
|
LeftBytes =0;
|
|
|
- 800fe18: 2300 movs r3, #0
|
|
|
- 800fe1a: 703b strb r3, [r7, #0]
|
|
|
+ 800fd90: 2300 movs r3, #0
|
|
|
+ 800fd92: 703b strb r3, [r7, #0]
|
|
|
|
|
|
/* update data pointer */
|
|
|
ptr = (char*)(ptr+j);
|
|
|
- 800fe1c: 1976 adds r6, r6, r5
|
|
|
+ 800fd94: 1976 adds r6, r6, r5
|
|
|
len = len -j;
|
|
|
- 800fe1e: 1b64 subs r4, r4, r5
|
|
|
+ 800fd96: 1b64 subs r4, r4, r5
|
|
|
}
|
|
|
|
|
|
/* write received bytes into flash */
|
|
|
count = len/4;
|
|
|
- 800fe20: 08a2 lsrs r2, r4, #2
|
|
|
+ 800fd98: 08a2 lsrs r2, r4, #2
|
|
|
|
|
|
/* check if remaining bytes < 4 */
|
|
|
i= len%4;
|
|
|
if (i>0)
|
|
|
- 800fe22: f014 0103 ands.w r1, r4, #3
|
|
|
- 800fe26: d015 beq.n 800fe54 <IAP_HTTP_writedata+0x78>
|
|
|
+ 800fd9a: f014 0103 ands.w r1, r4, #3
|
|
|
+ 800fd9e: d015 beq.n 800fdcc <IAP_HTTP_writedata+0x78>
|
|
|
{
|
|
|
if (TotalReceived != size)
|
|
|
- 800fe28: 4b11 ldr r3, [pc, #68] ; (800fe70 <IAP_HTTP_writedata+0x94>)
|
|
|
- 800fe2a: 4812 ldr r0, [pc, #72] ; (800fe74 <IAP_HTTP_writedata+0x98>)
|
|
|
- 800fe2c: 681b ldr r3, [r3, #0]
|
|
|
- 800fe2e: 6800 ldr r0, [r0, #0]
|
|
|
- 800fe30: 4298 cmp r0, r3
|
|
|
- 800fe32: d00e beq.n 800fe52 <IAP_HTTP_writedata+0x76>
|
|
|
+ 800fda0: 4b11 ldr r3, [pc, #68] ; (800fde8 <IAP_HTTP_writedata+0x94>)
|
|
|
+ 800fda2: 4812 ldr r0, [pc, #72] ; (800fdec <IAP_HTTP_writedata+0x98>)
|
|
|
+ 800fda4: 681b ldr r3, [r3, #0]
|
|
|
+ 800fda6: 6800 ldr r0, [r0, #0]
|
|
|
+ 800fda8: 4298 cmp r0, r3
|
|
|
+ 800fdaa: d00e beq.n 800fdca <IAP_HTTP_writedata+0x76>
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
- 800fe34: 480b ldr r0, [pc, #44] ; (800fe64 <IAP_HTTP_writedata+0x88>)
|
|
|
+ 800fdac: 480b ldr r0, [pc, #44] ; (800fddc <IAP_HTTP_writedata+0x88>)
|
|
|
for(;i>0;i--)
|
|
|
LeftBytesTab[LeftBytes++] = *(char*)(ptr+ len-i);
|
|
|
- 800fe36: 4d0c ldr r5, [pc, #48] ; (800fe68 <IAP_HTTP_writedata+0x8c>)
|
|
|
+ 800fdae: 4d0c ldr r5, [pc, #48] ; (800fde0 <IAP_HTTP_writedata+0x8c>)
|
|
|
if (i>0)
|
|
|
{
|
|
|
if (TotalReceived != size)
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
- 800fe38: 2300 movs r3, #0
|
|
|
+ 800fdb0: 2300 movs r3, #0
|
|
|
* @brief writes received data in flash
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
- 800fe3a: 1a64 subs r4, r4, r1
|
|
|
+ 800fdb2: 1a64 subs r4, r4, r1
|
|
|
if (i>0)
|
|
|
{
|
|
|
if (TotalReceived != size)
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
- 800fe3c: 7003 strb r3, [r0, #0]
|
|
|
+ 800fdb4: 7003 strb r3, [r0, #0]
|
|
|
* @brief writes received data in flash
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
- 800fe3e: 1934 adds r4, r6, r4
|
|
|
+ 800fdb6: 1934 adds r4, r6, r4
|
|
|
if (TotalReceived != size)
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
for(;i>0;i--)
|
|
|
LeftBytesTab[LeftBytes++] = *(char*)(ptr+ len-i);
|
|
|
- 800fe40: 5ce7 ldrb r7, [r4, r3]
|
|
|
+ 800fdb8: 5ce7 ldrb r7, [r4, r3]
|
|
|
* @brief writes received data in flash
|
|
|
* @param ptr: data pointer
|
|
|
* @param len: data length
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_HTTP_writedata(char * ptr, uint32_t len)
|
|
|
- 800fe42: b2d8 uxtb r0, r3
|
|
|
- 800fe44: 3301 adds r3, #1
|
|
|
+ 800fdba: b2d8 uxtb r0, r3
|
|
|
+ 800fdbc: 3301 adds r3, #1
|
|
|
{
|
|
|
if (TotalReceived != size)
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
for(;i>0;i--)
|
|
|
- 800fe46: 428b cmp r3, r1
|
|
|
+ 800fdbe: 428b cmp r3, r1
|
|
|
LeftBytesTab[LeftBytes++] = *(char*)(ptr+ len-i);
|
|
|
- 800fe48: 542f strb r7, [r5, r0]
|
|
|
+ 800fdc0: 542f strb r7, [r5, r0]
|
|
|
{
|
|
|
if (TotalReceived != size)
|
|
|
{
|
|
|
/* store bytes in LeftBytesTab */
|
|
|
LeftBytes=0;
|
|
|
for(;i>0;i--)
|
|
|
- 800fe4a: d1f9 bne.n 800fe40 <IAP_HTTP_writedata+0x64>
|
|
|
- 800fe4c: 4905 ldr r1, [pc, #20] ; (800fe64 <IAP_HTTP_writedata+0x88>)
|
|
|
- 800fe4e: 700b strb r3, [r1, #0]
|
|
|
- 800fe50: e000 b.n 800fe54 <IAP_HTTP_writedata+0x78>
|
|
|
+ 800fdc2: d1f9 bne.n 800fdb8 <IAP_HTTP_writedata+0x64>
|
|
|
+ 800fdc4: 4905 ldr r1, [pc, #20] ; (800fddc <IAP_HTTP_writedata+0x88>)
|
|
|
+ 800fdc6: 700b strb r3, [r1, #0]
|
|
|
+ 800fdc8: e000 b.n 800fdcc <IAP_HTTP_writedata+0x78>
|
|
|
LeftBytesTab[LeftBytes++] = *(char*)(ptr+ len-i);
|
|
|
}
|
|
|
else count++;
|
|
|
- 800fe52: 3201 adds r2, #1
|
|
|
+ 800fdca: 3201 adds r2, #1
|
|
|
}
|
|
|
FLASH_If_Write(&FlashWriteAddress, (u32*)ptr ,count);
|
|
|
- 800fe54: 4805 ldr r0, [pc, #20] ; (800fe6c <IAP_HTTP_writedata+0x90>)
|
|
|
- 800fe56: 4631 mov r1, r6
|
|
|
- 800fe58: b292 uxth r2, r2
|
|
|
+ 800fdcc: 4805 ldr r0, [pc, #20] ; (800fde4 <IAP_HTTP_writedata+0x90>)
|
|
|
+ 800fdce: 4631 mov r1, r6
|
|
|
+ 800fdd0: b292 uxth r2, r2
|
|
|
}
|
|
|
- 800fe5a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
|
|
|
+ 800fdd2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
|
|
|
for(;i>0;i--)
|
|
|
LeftBytesTab[LeftBytes++] = *(char*)(ptr+ len-i);
|
|
|
}
|
|
|
else count++;
|
|
|
}
|
|
|
FLASH_If_Write(&FlashWriteAddress, (u32*)ptr ,count);
|
|
|
- 800fe5e: f7ff bc25 b.w 800f6ac <FLASH_If_Write>
|
|
|
- 800fe62: bf00 nop
|
|
|
- 800fe64: 20006d94 .word 0x20006d94
|
|
|
- 800fe68: 20006d83 .word 0x20006d83
|
|
|
- 800fe6c: 20006d90 .word 0x20006d90
|
|
|
- 800fe70: 20006da4 .word 0x20006da4
|
|
|
- 800fe74: 20006da0 .word 0x20006da0
|
|
|
-
|
|
|
-0800fe78 <http_recv>:
|
|
|
+ 800fdd6: f7ff bc69 b.w 800f6ac <FLASH_If_Write>
|
|
|
+ 800fdda: bf00 nop
|
|
|
+ 800fddc: 20006d94 .word 0x20006d94
|
|
|
+ 800fde0: 20006d83 .word 0x20006d83
|
|
|
+ 800fde4: 20006d90 .word 0x20006d90
|
|
|
+ 800fde8: 20006da4 .word 0x20006da4
|
|
|
+ 800fdec: 20006da0 .word 0x20006da0
|
|
|
+
|
|
|
+0800fdf0 <http_recv>:
|
|
|
* @retval err
|
|
|
*/
|
|
|
/* goback.cgi - возврат в основную прошивку */
|
|
|
/* upload.cgi - загрузка новой прошивки */
|
|
|
static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
|
|
|
{
|
|
|
- 800fe78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
- 800fe7c: b087 sub sp, #28
|
|
|
- 800fe7e: 4617 mov r7, r2
|
|
|
+ 800fdf0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
+ 800fdf4: b087 sub sp, #28
|
|
|
+ 800fdf6: 4617 mov r7, r2
|
|
|
int32_t i, len=0;
|
|
|
uint32_t DataOffset, FilenameOffset;
|
|
|
char *data, *ptr, filename[13];
|
|
|
struct fs_file file = {0, 0};
|
|
|
- 800fe80: 2200 movs r2, #0
|
|
|
+ 800fdf8: 2200 movs r2, #0
|
|
|
* @retval err
|
|
|
*/
|
|
|
/* goback.cgi - возврат в основную прошивку */
|
|
|
/* upload.cgi - загрузка новой прошивки */
|
|
|
static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
|
|
|
{
|
|
|
- 800fe82: 4604 mov r4, r0
|
|
|
- 800fe84: 460d mov r5, r1
|
|
|
+ 800fdfa: 4604 mov r4, r0
|
|
|
+ 800fdfc: 460d mov r5, r1
|
|
|
int32_t i, len=0;
|
|
|
uint32_t DataOffset, FilenameOffset;
|
|
|
char *data, *ptr, filename[13];
|
|
|
struct fs_file file = {0, 0};
|
|
|
- 800fe86: 9200 str r2, [sp, #0]
|
|
|
- 800fe88: 9201 str r2, [sp, #4]
|
|
|
+ 800fdfe: 9200 str r2, [sp, #0]
|
|
|
+ 800fe00: 9201 str r2, [sp, #4]
|
|
|
|
|
|
hs = arg;
|
|
|
|
|
|
|
|
|
|
|
|
if (err == ERR_OK && p != NULL)
|
|
|
- 800fe8a: 2b00 cmp r3, #0
|
|
|
- 800fe8c: f040 820a bne.w 80102a4 <http_recv+0x42c>
|
|
|
+ 800fe02: 2b00 cmp r3, #0
|
|
|
+ 800fe04: f040 820a bne.w 801021c <http_recv+0x42c>
|
|
|
{
|
|
|
/* Inform TCP that we have taken the data */
|
|
|
tcp_recved(pcb, p->tot_len);
|
|
|
- 800fe90: 4608 mov r0, r1
|
|
|
+ 800fe08: 4608 mov r0, r1
|
|
|
|
|
|
hs = arg;
|
|
|
|
|
|
|
|
|
|
|
|
if (err == ERR_OK && p != NULL)
|
|
|
- 800fe92: 2f00 cmp r7, #0
|
|
|
- 800fe94: f000 8203 beq.w 801029e <http_recv+0x426>
|
|
|
+ 800fe0a: 2f00 cmp r7, #0
|
|
|
+ 800fe0c: f000 8203 beq.w 8010216 <http_recv+0x426>
|
|
|
{
|
|
|
/* Inform TCP that we have taken the data */
|
|
|
tcp_recved(pcb, p->tot_len);
|
|
|
- 800fe98: 8939 ldrh r1, [r7, #8]
|
|
|
- 800fe9a: f7fb fda1 bl 800b9e0 <tcp_recved>
|
|
|
+ 800fe10: 8939 ldrh r1, [r7, #8]
|
|
|
+ 800fe12: f7fb fde5 bl 800b9e0 <tcp_recved>
|
|
|
|
|
|
if (hs->file == NULL)
|
|
|
- 800fe9e: 6823 ldr r3, [r4, #0]
|
|
|
- 800fea0: 2b00 cmp r3, #0
|
|
|
- 800fea2: f040 81ec bne.w 801027e <http_recv+0x406>
|
|
|
+ 800fe16: 6823 ldr r3, [r4, #0]
|
|
|
+ 800fe18: 2b00 cmp r3, #0
|
|
|
+ 800fe1a: f040 81ec bne.w 80101f6 <http_recv+0x406>
|
|
|
{
|
|
|
data = p->payload;
|
|
|
- 800fea6: 687e ldr r6, [r7, #4]
|
|
|
+ 800fe1e: 687e ldr r6, [r7, #4]
|
|
|
len = p->tot_len;
|
|
|
- 800fea8: f8b7 8008 ldrh.w r8, [r7, #8]
|
|
|
+ 800fe20: f8b7 8008 ldrh.w r8, [r7, #8]
|
|
|
|
|
|
printLen = p->tot_len;
|
|
|
- 800feac: 4b9f ldr r3, [pc, #636] ; (801012c <http_recv+0x2b4>)
|
|
|
+ 800fe24: 4b9f ldr r3, [pc, #636] ; (80100a4 <http_recv+0x2b4>)
|
|
|
memcpy(printBuf, p->payload , printLen);
|
|
|
- 800feae: 48a0 ldr r0, [pc, #640] ; (8010130 <http_recv+0x2b8>)
|
|
|
+ 800fe26: 48a0 ldr r0, [pc, #640] ; (80100a8 <http_recv+0x2b8>)
|
|
|
if (hs->file == NULL)
|
|
|
{
|
|
|
data = p->payload;
|
|
|
len = p->tot_len;
|
|
|
|
|
|
printLen = p->tot_len;
|
|
|
- 800feb0: f8a3 8000 strh.w r8, [r3]
|
|
|
+ 800fe28: f8a3 8000 strh.w r8, [r3]
|
|
|
memcpy(printBuf, p->payload , printLen);
|
|
|
- 800feb4: 4631 mov r1, r6
|
|
|
- 800feb6: 4642 mov r2, r8
|
|
|
- 800feb8: f7f9 faa4 bl 8009404 <memcpy>
|
|
|
+ 800fe2c: 4631 mov r1, r6
|
|
|
+ 800fe2e: 4642 mov r2, r8
|
|
|
+ 800fe30: f7f9 fae8 bl 8009404 <memcpy>
|
|
|
//printf(printBuf);
|
|
|
|
|
|
/* process HTTP GET requests */
|
|
|
if (strncmp(data, "GET /", 5) == 0)
|
|
|
- 800febc: 4630 mov r0, r6
|
|
|
- 800febe: 499d ldr r1, [pc, #628] ; (8010134 <http_recv+0x2bc>)
|
|
|
- 800fec0: 2205 movs r2, #5
|
|
|
- 800fec2: f7f9 fd0b bl 80098dc <strncmp>
|
|
|
- 800fec6: 4681 mov r9, r0
|
|
|
+ 800fe34: 4630 mov r0, r6
|
|
|
+ 800fe36: 499d ldr r1, [pc, #628] ; (80100ac <http_recv+0x2bc>)
|
|
|
+ 800fe38: 2205 movs r2, #5
|
|
|
+ 800fe3a: f7f9 fd4f bl 80098dc <strncmp>
|
|
|
+ 800fe3e: 4681 mov r9, r0
|
|
|
pbuf_free(p);
|
|
|
send_data(pcb, hs);
|
|
|
resetpage = 1;
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}*/
|
|
|
if (strncmp(data, "GET /upload.css", 15) == 0)
|
|
|
- 800fec8: 4630 mov r0, r6
|
|
|
+ 800fe40: 4630 mov r0, r6
|
|
|
printLen = p->tot_len;
|
|
|
memcpy(printBuf, p->payload , printLen);
|
|
|
//printf(printBuf);
|
|
|
|
|
|
/* process HTTP GET requests */
|
|
|
if (strncmp(data, "GET /", 5) == 0)
|
|
|
- 800feca: f1b9 0f00 cmp.w r9, #0
|
|
|
- 800fece: d14e bne.n 800ff6e <http_recv+0xf6>
|
|
|
+ 800fe42: f1b9 0f00 cmp.w r9, #0
|
|
|
+ 800fe46: d14e bne.n 800fee6 <http_recv+0xf6>
|
|
|
pbuf_free(p);
|
|
|
send_data(pcb, hs);
|
|
|
resetpage = 1;
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}*/
|
|
|
if (strncmp(data, "GET /upload.css", 15) == 0)
|
|
|
- 800fed0: 4999 ldr r1, [pc, #612] ; (8010138 <http_recv+0x2c0>)
|
|
|
- 800fed2: 220f movs r2, #15
|
|
|
- 800fed4: f7f9 fd02 bl 80098dc <strncmp>
|
|
|
- 800fed8: b908 cbnz r0, 800fede <http_recv+0x66>
|
|
|
+ 800fe48: 4999 ldr r1, [pc, #612] ; (80100b0 <http_recv+0x2c0>)
|
|
|
+ 800fe4a: 220f movs r2, #15
|
|
|
+ 800fe4c: f7f9 fd46 bl 80098dc <strncmp>
|
|
|
+ 800fe50: b908 cbnz r0, 800fe56 <http_recv+0x66>
|
|
|
{
|
|
|
fs_open("/upload.css", &file);
|
|
|
- 800feda: 4898 ldr r0, [pc, #608] ; (801013c <http_recv+0x2c4>)
|
|
|
- 800fedc: e006 b.n 800feec <http_recv+0x74>
|
|
|
+ 800fe52: 4898 ldr r0, [pc, #608] ; (80100b4 <http_recv+0x2c4>)
|
|
|
+ 800fe54: e006 b.n 800fe64 <http_recv+0x74>
|
|
|
hs->left = file.len;
|
|
|
pbuf_free(p);
|
|
|
send_data(pcb, hs);
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}
|
|
|
else if (strncmp(data, "GET /upload.js", 14) == 0)
|
|
|
- 800fede: 4630 mov r0, r6
|
|
|
- 800fee0: 4997 ldr r1, [pc, #604] ; (8010140 <http_recv+0x2c8>)
|
|
|
- 800fee2: 220e movs r2, #14
|
|
|
- 800fee4: f7f9 fcfa bl 80098dc <strncmp>
|
|
|
- 800fee8: b998 cbnz r0, 800ff12 <http_recv+0x9a>
|
|
|
+ 800fe56: 4630 mov r0, r6
|
|
|
+ 800fe58: 4997 ldr r1, [pc, #604] ; (80100b8 <http_recv+0x2c8>)
|
|
|
+ 800fe5a: 220e movs r2, #14
|
|
|
+ 800fe5c: f7f9 fd3e bl 80098dc <strncmp>
|
|
|
+ 800fe60: b998 cbnz r0, 800fe8a <http_recv+0x9a>
|
|
|
{
|
|
|
fs_open("/upload.js", &file);
|
|
|
- 800feea: 4896 ldr r0, [pc, #600] ; (8010144 <http_recv+0x2cc>)
|
|
|
- 800feec: 4669 mov r1, sp
|
|
|
- 800feee: f7ff ff5f bl 800fdb0 <fs_open>
|
|
|
+ 800fe62: 4896 ldr r0, [pc, #600] ; (80100bc <http_recv+0x2cc>)
|
|
|
+ 800fe64: 4669 mov r1, sp
|
|
|
+ 800fe66: f7ff ff5f bl 800fd28 <fs_open>
|
|
|
hs->file = file.data;
|
|
|
- 800fef2: 9b00 ldr r3, [sp, #0]
|
|
|
- 800fef4: 6023 str r3, [r4, #0]
|
|
|
+ 800fe6a: 9b00 ldr r3, [sp, #0]
|
|
|
+ 800fe6c: 6023 str r3, [r4, #0]
|
|
|
hs->left = file.len;
|
|
|
- 800fef6: 9b01 ldr r3, [sp, #4]
|
|
|
+ 800fe6e: 9b01 ldr r3, [sp, #4]
|
|
|
pbuf_free(p);
|
|
|
- 800fef8: 4638 mov r0, r7
|
|
|
+ 800fe70: 4638 mov r0, r7
|
|
|
}
|
|
|
else if (strncmp(data, "GET /upload.js", 14) == 0)
|
|
|
{
|
|
|
fs_open("/upload.js", &file);
|
|
|
hs->file = file.data;
|
|
|
hs->left = file.len;
|
|
|
- 800fefa: 6063 str r3, [r4, #4]
|
|
|
+ 800fe72: 6063 str r3, [r4, #4]
|
|
|
pbuf_free(p);
|
|
|
- 800fefc: f7fb fae2 bl 800b4c4 <pbuf_free>
|
|
|
+ 800fe74: f7fb fb26 bl 800b4c4 <pbuf_free>
|
|
|
send_data(pcb, hs);
|
|
|
- 800ff00: 4628 mov r0, r5
|
|
|
- 800ff02: 4621 mov r1, r4
|
|
|
- 800ff04: f7ff ff14 bl 800fd30 <send_data>
|
|
|
+ 800fe78: 4628 mov r0, r5
|
|
|
+ 800fe7a: 4621 mov r1, r4
|
|
|
+ 800fe7c: f7ff ff14 bl 800fca8 <send_data>
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
- 800ff08: 4628 mov r0, r5
|
|
|
- 800ff0a: 498f ldr r1, [pc, #572] ; (8010148 <http_recv+0x2d0>)
|
|
|
- 800ff0c: f7fb fda0 bl 800ba50 <tcp_sent>
|
|
|
- 800ff10: e1c8 b.n 80102a4 <http_recv+0x42c>
|
|
|
+ 800fe80: 4628 mov r0, r5
|
|
|
+ 800fe82: 498f ldr r1, [pc, #572] ; (80100c0 <http_recv+0x2d0>)
|
|
|
+ 800fe84: f7fb fde4 bl 800ba50 <tcp_sent>
|
|
|
+ 800fe88: e1c8 b.n 801021c <http_recv+0x42c>
|
|
|
}
|
|
|
/* Возврат в основную прошивку. Сбрасываем флаг loadmode,
|
|
|
сохраняем настройки и перезагружаемся */
|
|
|
else if (strncmp(data, "GET /goback.cgi", 15)==0)
|
|
|
- 800ff12: 498e ldr r1, [pc, #568] ; (801014c <http_recv+0x2d4>)
|
|
|
- 800ff14: 4630 mov r0, r6
|
|
|
- 800ff16: 220f movs r2, #15
|
|
|
- 800ff18: f7f9 fce0 bl 80098dc <strncmp>
|
|
|
- 800ff1c: 4601 mov r1, r0
|
|
|
- 800ff1e: b990 cbnz r0, 800ff46 <http_recv+0xce>
|
|
|
+ 800fe8a: 498e ldr r1, [pc, #568] ; (80100c4 <http_recv+0x2d4>)
|
|
|
+ 800fe8c: 4630 mov r0, r6
|
|
|
+ 800fe8e: 220f movs r2, #15
|
|
|
+ 800fe90: f7f9 fd24 bl 80098dc <strncmp>
|
|
|
+ 800fe94: 4601 mov r1, r0
|
|
|
+ 800fe96: b990 cbnz r0, 800febe <http_recv+0xce>
|
|
|
{
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR1, 0);
|
|
|
- 800ff20: 2001 movs r0, #1
|
|
|
- 800ff22: f7fa f867 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 800fe98: 2001 movs r0, #1
|
|
|
+ 800fe9a: f7fa f8ab bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
/* sSettings.bootParams.loadMode = 0;
|
|
|
SETTINGS_Save();*/
|
|
|
Delay_ms(1010);
|
|
|
- 800ff26: f240 30f2 movw r0, #1010 ; 0x3f2
|
|
|
- 800ff2a: f7ff fdf5 bl 800fb18 <Delay_ms>
|
|
|
+ 800fe9e: f240 30f2 movw r0, #1010 ; 0x3f2
|
|
|
+ 800fea2: f7ff fdf5 bl 800fa90 <Delay_ms>
|
|
|
This function acts as a special kind of Data Memory Barrier.
|
|
|
It completes when all explicit memory accesses before this instruction complete.
|
|
|
*/
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
|
|
{
|
|
|
__ASM volatile ("dsb");
|
|
|
- 800ff2e: f3bf 8f4f dsb sy
|
|
|
+ 800fea6: f3bf 8f4f dsb sy
|
|
|
//static inline void NVIC_SystemReset(void)
|
|
|
{
|
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
|
buffered write are completed before reset */
|
|
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
|
|
- 800ff32: 4a87 ldr r2, [pc, #540] ; (8010150 <http_recv+0x2d8>)
|
|
|
- 800ff34: 4b87 ldr r3, [pc, #540] ; (8010154 <http_recv+0x2dc>)
|
|
|
- 800ff36: 68d1 ldr r1, [r2, #12]
|
|
|
- 800ff38: f401 61e0 and.w r1, r1, #1792 ; 0x700
|
|
|
- 800ff3c: 430b orrs r3, r1
|
|
|
+ 800feaa: 4a87 ldr r2, [pc, #540] ; (80100c8 <http_recv+0x2d8>)
|
|
|
+ 800feac: 4b87 ldr r3, [pc, #540] ; (80100cc <http_recv+0x2dc>)
|
|
|
+ 800feae: 68d1 ldr r1, [r2, #12]
|
|
|
+ 800feb0: f401 61e0 and.w r1, r1, #1792 ; 0x700
|
|
|
+ 800feb4: 430b orrs r3, r1
|
|
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
|
|
//static inline void NVIC_SystemReset(void)
|
|
|
{
|
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
|
buffered write are completed before reset */
|
|
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
- 800ff3e: 60d3 str r3, [r2, #12]
|
|
|
- 800ff40: f3bf 8f4f dsb sy
|
|
|
- 800ff44: e7fe b.n 800ff44 <http_recv+0xcc>
|
|
|
+ 800feb6: 60d3 str r3, [r2, #12]
|
|
|
+ 800feb8: f3bf 8f4f dsb sy
|
|
|
+ 800febc: e7fe b.n 800febc <http_recv+0xcc>
|
|
|
NVIC_SystemReset();
|
|
|
}
|
|
|
else if (strncmp(data, "GET /favicon.ico", 16) == 0)
|
|
|
- 800ff46: 4630 mov r0, r6
|
|
|
- 800ff48: 4983 ldr r1, [pc, #524] ; (8010158 <http_recv+0x2e0>)
|
|
|
- 800ff4a: 2210 movs r2, #16
|
|
|
- 800ff4c: f7f9 fcc6 bl 80098dc <strncmp>
|
|
|
- 800ff50: b940 cbnz r0, 800ff64 <http_recv+0xec>
|
|
|
+ 800febe: 4630 mov r0, r6
|
|
|
+ 800fec0: 4983 ldr r1, [pc, #524] ; (80100d0 <http_recv+0x2e0>)
|
|
|
+ 800fec2: 2210 movs r2, #16
|
|
|
+ 800fec4: f7f9 fd0a bl 80098dc <strncmp>
|
|
|
+ 800fec8: b940 cbnz r0, 800fedc <http_recv+0xec>
|
|
|
{
|
|
|
fs_open("/favicon.ico", &file);
|
|
|
- 800ff52: 4882 ldr r0, [pc, #520] ; (801015c <http_recv+0x2e4>)
|
|
|
- 800ff54: 4669 mov r1, sp
|
|
|
- 800ff56: f7ff ff2b bl 800fdb0 <fs_open>
|
|
|
+ 800feca: 4882 ldr r0, [pc, #520] ; (80100d4 <http_recv+0x2e4>)
|
|
|
+ 800fecc: 4669 mov r1, sp
|
|
|
+ 800fece: f7ff ff2b bl 800fd28 <fs_open>
|
|
|
hs->file = file.data;
|
|
|
- 800ff5a: 9b00 ldr r3, [sp, #0]
|
|
|
- 800ff5c: 6023 str r3, [r4, #0]
|
|
|
+ 800fed2: 9b00 ldr r3, [sp, #0]
|
|
|
+ 800fed4: 6023 str r3, [r4, #0]
|
|
|
hs->left = file.len;
|
|
|
- 800ff5e: 9b01 ldr r3, [sp, #4]
|
|
|
- 800ff60: 6063 str r3, [r4, #4]
|
|
|
- 800ff62: e7cd b.n 800ff00 <http_recv+0x88>
|
|
|
+ 800fed6: 9b01 ldr r3, [sp, #4]
|
|
|
+ 800fed8: 6063 str r3, [r4, #4]
|
|
|
+ 800feda: e7cd b.n 800fe78 <http_recv+0x88>
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/*send the login page (which is the index page) */
|
|
|
htmlpage = LoginPage;
|
|
|
- 800ff64: 4b7e ldr r3, [pc, #504] ; (8010160 <http_recv+0x2e8>)
|
|
|
+ 800fedc: 4b7e ldr r3, [pc, #504] ; (80100d8 <http_recv+0x2e8>)
|
|
|
fs_open("/index.html", &file);
|
|
|
- 800ff66: 487f ldr r0, [pc, #508] ; (8010164 <http_recv+0x2ec>)
|
|
|
+ 800fede: 487f ldr r0, [pc, #508] ; (80100dc <http_recv+0x2ec>)
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/*send the login page (which is the index page) */
|
|
|
htmlpage = LoginPage;
|
|
|
- 800ff68: f883 9000 strb.w r9, [r3]
|
|
|
- 800ff6c: e7be b.n 800feec <http_recv+0x74>
|
|
|
+ 800fee0: f883 9000 strb.w r9, [r3]
|
|
|
+ 800fee4: e7be b.n 800fe64 <http_recv+0x74>
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
}
|
|
|
}
|
|
|
#if 1
|
|
|
/* process POST request for file upload and incoming data packets after POST request*/
|
|
|
else if ((strncmp(data, "POST /upload.cgi",16) == 0) || (DataFlag >= 1))
|
|
|
- 800ff6e: 497e ldr r1, [pc, #504] ; (8010168 <http_recv+0x2f0>)
|
|
|
- 800ff70: 2210 movs r2, #16
|
|
|
- 800ff72: f7f9 fcb3 bl 80098dc <strncmp>
|
|
|
- 800ff76: b120 cbz r0, 800ff82 <http_recv+0x10a>
|
|
|
- 800ff78: 4b7c ldr r3, [pc, #496] ; (801016c <http_recv+0x2f4>)
|
|
|
- 800ff7a: 681b ldr r3, [r3, #0]
|
|
|
- 800ff7c: 2b00 cmp r3, #0
|
|
|
- 800ff7e: f000 817e beq.w 801027e <http_recv+0x406>
|
|
|
+ 800fee6: 497e ldr r1, [pc, #504] ; (80100e0 <http_recv+0x2f0>)
|
|
|
+ 800fee8: 2210 movs r2, #16
|
|
|
+ 800feea: f7f9 fcf7 bl 80098dc <strncmp>
|
|
|
+ 800feee: b120 cbz r0, 800fefa <http_recv+0x10a>
|
|
|
+ 800fef0: 4b7c ldr r3, [pc, #496] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 800fef2: 681b ldr r3, [r3, #0]
|
|
|
+ 800fef4: 2b00 cmp r3, #0
|
|
|
+ 800fef6: f000 817e beq.w 80101f6 <http_recv+0x406>
|
|
|
{
|
|
|
if (fEraseFlash) {
|
|
|
- 800ff82: f8df 9210 ldr.w r9, [pc, #528] ; 8010194 <http_recv+0x31c>
|
|
|
- 800ff86: f899 3000 ldrb.w r3, [r9]
|
|
|
- 800ff8a: b12b cbz r3, 800ff98 <http_recv+0x120>
|
|
|
+ 800fefa: f8df 9210 ldr.w r9, [pc, #528] ; 801010c <http_recv+0x31c>
|
|
|
+ 800fefe: f899 3000 ldrb.w r3, [r9]
|
|
|
+ 800ff02: b12b cbz r3, 800ff10 <http_recv+0x120>
|
|
|
FLASH_If_Erase(USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
- 800ff8c: 4878 ldr r0, [pc, #480] ; (8010170 <http_recv+0x2f8>)
|
|
|
- 800ff8e: f7ff fb5f bl 800f650 <FLASH_If_Erase>
|
|
|
+ 800ff04: 4878 ldr r0, [pc, #480] ; (80100e8 <http_recv+0x2f8>)
|
|
|
+ 800ff06: f7ff fba3 bl 800f650 <FLASH_If_Erase>
|
|
|
fEraseFlash = false;
|
|
|
- 800ff92: 2300 movs r3, #0
|
|
|
- 800ff94: f889 3000 strb.w r3, [r9]
|
|
|
+ 800ff0a: 2300 movs r3, #0
|
|
|
+ 800ff0c: f889 3000 strb.w r3, [r9]
|
|
|
}
|
|
|
|
|
|
DataOffset = 0;
|
|
|
|
|
|
/* POST Packet received */
|
|
|
if (DataFlag == 0)
|
|
|
- 800ff98: 4b74 ldr r3, [pc, #464] ; (801016c <http_recv+0x2f4>)
|
|
|
- 800ff9a: 681b ldr r3, [r3, #0]
|
|
|
- 800ff9c: 2b00 cmp r3, #0
|
|
|
- 800ff9e: d15e bne.n 801005e <http_recv+0x1e6>
|
|
|
+ 800ff10: 4b74 ldr r3, [pc, #464] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 800ff12: 681b ldr r3, [r3, #0]
|
|
|
+ 800ff14: 2b00 cmp r3, #0
|
|
|
+ 800ff16: d15e bne.n 800ffd6 <http_recv+0x1e6>
|
|
|
{
|
|
|
BrowserFlag = 0;
|
|
|
- 800ffa0: 4a74 ldr r2, [pc, #464] ; (8010174 <http_recv+0x2fc>)
|
|
|
+ 800ff18: 4a74 ldr r2, [pc, #464] ; (80100ec <http_recv+0x2fc>)
|
|
|
TotalReceived = 0;
|
|
|
|
|
|
/* parse packet for Content-length field */
|
|
|
size = Parse_Content_Length(data, p->tot_len);
|
|
|
- 800ffa2: f8b7 a008 ldrh.w sl, [r7, #8]
|
|
|
+ 800ff1a: f8b7 a008 ldrh.w sl, [r7, #8]
|
|
|
DataOffset = 0;
|
|
|
|
|
|
/* POST Packet received */
|
|
|
if (DataFlag == 0)
|
|
|
{
|
|
|
BrowserFlag = 0;
|
|
|
- 800ffa6: 6013 str r3, [r2, #0]
|
|
|
+ 800ff1e: 6013 str r3, [r2, #0]
|
|
|
TotalReceived = 0;
|
|
|
- 800ffa8: 4a73 ldr r2, [pc, #460] ; (8010178 <http_recv+0x300>)
|
|
|
- 800ffaa: 6013 str r3, [r2, #0]
|
|
|
+ 800ff20: 4a73 ldr r2, [pc, #460] ; (80100f0 <http_recv+0x300>)
|
|
|
+ 800ff22: 6013 str r3, [r2, #0]
|
|
|
{
|
|
|
uint32_t i=0,size=0, S=1;
|
|
|
int32_t j=0;
|
|
|
char sizestring[6], *ptr;
|
|
|
|
|
|
ContentLengthOffset =0;
|
|
|
- 800ffac: 4a73 ldr r2, [pc, #460] ; (801017c <http_recv+0x304>)
|
|
|
+ 800ff24: 4a73 ldr r2, [pc, #460] ; (80100f4 <http_recv+0x304>)
|
|
|
|
|
|
/* find Content-Length data in packet buffer */
|
|
|
for (i=0;i<len;i++)
|
|
|
- 800ffae: 4699 mov r9, r3
|
|
|
+ 800ff26: 4699 mov r9, r3
|
|
|
{
|
|
|
uint32_t i=0,size=0, S=1;
|
|
|
int32_t j=0;
|
|
|
char sizestring[6], *ptr;
|
|
|
|
|
|
ContentLengthOffset =0;
|
|
|
- 800ffb0: 6013 str r3, [r2, #0]
|
|
|
- 800ffb2: e00d b.n 800ffd0 <http_recv+0x158>
|
|
|
+ 800ff28: 6013 str r3, [r2, #0]
|
|
|
+ 800ff2a: e00d b.n 800ff48 <http_recv+0x158>
|
|
|
|
|
|
/* find Content-Length data in packet buffer */
|
|
|
for (i=0;i<len;i++)
|
|
|
{
|
|
|
if (strncmp ((char*)(data+i), Content_Length, 16)==0)
|
|
|
- 800ffb4: eb06 0009 add.w r0, r6, r9
|
|
|
- 800ffb8: 4971 ldr r1, [pc, #452] ; (8010180 <http_recv+0x308>)
|
|
|
- 800ffba: 2210 movs r2, #16
|
|
|
- 800ffbc: f7f9 fc8e bl 80098dc <strncmp>
|
|
|
- 800ffc0: b920 cbnz r0, 800ffcc <http_recv+0x154>
|
|
|
+ 800ff2c: eb06 0009 add.w r0, r6, r9
|
|
|
+ 800ff30: 4971 ldr r1, [pc, #452] ; (80100f8 <http_recv+0x308>)
|
|
|
+ 800ff32: 2210 movs r2, #16
|
|
|
+ 800ff34: f7f9 fcd2 bl 80098dc <strncmp>
|
|
|
+ 800ff38: b920 cbnz r0, 800ff44 <http_recv+0x154>
|
|
|
{
|
|
|
ContentLengthOffset = i+16;
|
|
|
- 800ffc2: 4b6e ldr r3, [pc, #440] ; (801017c <http_recv+0x304>)
|
|
|
- 800ffc4: f109 0210 add.w r2, r9, #16
|
|
|
- 800ffc8: 601a str r2, [r3, #0]
|
|
|
- 800ffca: e003 b.n 800ffd4 <http_recv+0x15c>
|
|
|
+ 800ff3a: 4b6e ldr r3, [pc, #440] ; (80100f4 <http_recv+0x304>)
|
|
|
+ 800ff3c: f109 0210 add.w r2, r9, #16
|
|
|
+ 800ff40: 601a str r2, [r3, #0]
|
|
|
+ 800ff42: e003 b.n 800ff4c <http_recv+0x15c>
|
|
|
char sizestring[6], *ptr;
|
|
|
|
|
|
ContentLengthOffset =0;
|
|
|
|
|
|
/* find Content-Length data in packet buffer */
|
|
|
for (i=0;i<len;i++)
|
|
|
- 800ffcc: f109 0901 add.w r9, r9, #1
|
|
|
- 800ffd0: 45d1 cmp r9, sl
|
|
|
- 800ffd2: d3ef bcc.n 800ffb4 <http_recv+0x13c>
|
|
|
+ 800ff44: f109 0901 add.w r9, r9, #1
|
|
|
+ 800ff48: 45d1 cmp r9, sl
|
|
|
+ 800ff4a: d3ef bcc.n 800ff2c <http_recv+0x13c>
|
|
|
ContentLengthOffset = i+16;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
/* read Content-Length value */
|
|
|
if (ContentLengthOffset)
|
|
|
- 800ffd4: 4b69 ldr r3, [pc, #420] ; (801017c <http_recv+0x304>)
|
|
|
- 800ffd6: 681a ldr r2, [r3, #0]
|
|
|
- 800ffd8: 4618 mov r0, r3
|
|
|
- 800ffda: b90a cbnz r2, 800ffe0 <http_recv+0x168>
|
|
|
+ 800ff4c: 4b69 ldr r3, [pc, #420] ; (80100f4 <http_recv+0x304>)
|
|
|
+ 800ff4e: 681a ldr r2, [r3, #0]
|
|
|
+ 800ff50: 4618 mov r0, r3
|
|
|
+ 800ff52: b90a cbnz r2, 800ff58 <http_recv+0x168>
|
|
|
* @param len : buffer length
|
|
|
* @retval size : Content_length in numeric format
|
|
|
*/
|
|
|
static uint32_t Parse_Content_Length(char *data, uint32_t len)
|
|
|
{
|
|
|
uint32_t i=0,size=0, S=1;
|
|
|
- 800ffdc: 2200 movs r2, #0
|
|
|
- 800ffde: e023 b.n 8010028 <http_recv+0x1b0>
|
|
|
+ 800ff54: 2200 movs r2, #0
|
|
|
+ 800ff56: e023 b.n 800ffa0 <http_recv+0x1b0>
|
|
|
}
|
|
|
/* read Content-Length value */
|
|
|
if (ContentLengthOffset)
|
|
|
{
|
|
|
i=0;
|
|
|
ptr = (char*)(data + ContentLengthOffset);
|
|
|
- 800ffe0: eb06 0c02 add.w ip, r6, r2
|
|
|
+ 800ff58: eb06 0c02 add.w ip, r6, r2
|
|
|
}
|
|
|
}
|
|
|
/* read Content-Length value */
|
|
|
if (ContentLengthOffset)
|
|
|
{
|
|
|
i=0;
|
|
|
- 800ffe4: 2300 movs r3, #0
|
|
|
- 800ffe6: e004 b.n 800fff2 <http_recv+0x17a>
|
|
|
+ 800ff5c: 2300 movs r3, #0
|
|
|
+ 800ff5e: e004 b.n 800ff6a <http_recv+0x17a>
|
|
|
ptr = (char*)(data + ContentLengthOffset);
|
|
|
while(*(ptr+i)!=0x0d)
|
|
|
{
|
|
|
sizestring[i] = *(ptr+i);
|
|
|
- 800ffe8: f10d 0e08 add.w lr, sp, #8
|
|
|
- 800ffec: f803 100e strb.w r1, [r3, lr]
|
|
|
+ 800ff60: f10d 0e08 add.w lr, sp, #8
|
|
|
+ 800ff64: f803 100e strb.w r1, [r3, lr]
|
|
|
i++;
|
|
|
- 800fff0: 3301 adds r3, #1
|
|
|
+ 800ff68: 3301 adds r3, #1
|
|
|
/* read Content-Length value */
|
|
|
if (ContentLengthOffset)
|
|
|
{
|
|
|
i=0;
|
|
|
ptr = (char*)(data + ContentLengthOffset);
|
|
|
while(*(ptr+i)!=0x0d)
|
|
|
- 800fff2: f81c 1003 ldrb.w r1, [ip, r3]
|
|
|
- 800fff6: 290d cmp r1, #13
|
|
|
- 800fff8: eb03 0e02 add.w lr, r3, r2
|
|
|
- 800fffc: d1f4 bne.n 800ffe8 <http_recv+0x170>
|
|
|
- 800fffe: f8c0 e000 str.w lr, [r0]
|
|
|
+ 800ff6a: f81c 1003 ldrb.w r1, [ip, r3]
|
|
|
+ 800ff6e: 290d cmp r1, #13
|
|
|
+ 800ff70: eb03 0e02 add.w lr, r3, r2
|
|
|
+ 800ff74: d1f4 bne.n 800ff60 <http_recv+0x170>
|
|
|
+ 800ff76: f8c0 e000 str.w lr, [r0]
|
|
|
{
|
|
|
sizestring[i] = *(ptr+i);
|
|
|
i++;
|
|
|
ContentLengthOffset++;
|
|
|
}
|
|
|
if (i>0)
|
|
|
- 8010002: 2b00 cmp r3, #0
|
|
|
- 8010004: d0ea beq.n 800ffdc <http_recv+0x164>
|
|
|
+ 800ff7a: 2b00 cmp r3, #0
|
|
|
+ 800ff7c: d0ea beq.n 800ff54 <http_recv+0x164>
|
|
|
{
|
|
|
/* transform string data into numeric format */
|
|
|
for(j=i-1;j>=0;j--)
|
|
|
- 8010006: 3b01 subs r3, #1
|
|
|
+ 800ff7e: 3b01 subs r3, #1
|
|
|
* @param len : buffer length
|
|
|
* @retval size : Content_length in numeric format
|
|
|
*/
|
|
|
static uint32_t Parse_Content_Length(char *data, uint32_t len)
|
|
|
{
|
|
|
uint32_t i=0,size=0, S=1;
|
|
|
- 8010008: 2101 movs r1, #1
|
|
|
- 801000a: 2200 movs r2, #0
|
|
|
+ 800ff80: 2101 movs r1, #1
|
|
|
+ 800ff82: 2200 movs r2, #0
|
|
|
{
|
|
|
/* transform string data into numeric format */
|
|
|
for(j=i-1;j>=0;j--)
|
|
|
{
|
|
|
size += (sizestring[j]-0x30)*S;
|
|
|
S=S*10;
|
|
|
- 801000c: 200a movs r0, #10
|
|
|
- 801000e: e009 b.n 8010024 <http_recv+0x1ac>
|
|
|
+ 800ff84: 200a movs r0, #10
|
|
|
+ 800ff86: e009 b.n 800ff9c <http_recv+0x1ac>
|
|
|
if (i>0)
|
|
|
{
|
|
|
/* transform string data into numeric format */
|
|
|
for(j=i-1;j>=0;j--)
|
|
|
{
|
|
|
size += (sizestring[j]-0x30)*S;
|
|
|
- 8010010: f10d 0e08 add.w lr, sp, #8
|
|
|
- 8010014: f813 e00e ldrb.w lr, [r3, lr]
|
|
|
- 8010018: f1ae 0e30 sub.w lr, lr, #48 ; 0x30
|
|
|
- 801001c: fb01 220e mla r2, r1, lr, r2
|
|
|
+ 800ff88: f10d 0e08 add.w lr, sp, #8
|
|
|
+ 800ff8c: f813 e00e ldrb.w lr, [r3, lr]
|
|
|
+ 800ff90: f1ae 0e30 sub.w lr, lr, #48 ; 0x30
|
|
|
+ 800ff94: fb01 220e mla r2, r1, lr, r2
|
|
|
ContentLengthOffset++;
|
|
|
}
|
|
|
if (i>0)
|
|
|
{
|
|
|
/* transform string data into numeric format */
|
|
|
for(j=i-1;j>=0;j--)
|
|
|
- 8010020: 3b01 subs r3, #1
|
|
|
+ 800ff98: 3b01 subs r3, #1
|
|
|
{
|
|
|
size += (sizestring[j]-0x30)*S;
|
|
|
S=S*10;
|
|
|
- 8010022: 4341 muls r1, r0
|
|
|
+ 800ff9a: 4341 muls r1, r0
|
|
|
ContentLengthOffset++;
|
|
|
}
|
|
|
if (i>0)
|
|
|
{
|
|
|
/* transform string data into numeric format */
|
|
|
for(j=i-1;j>=0;j--)
|
|
|
- 8010024: 2b00 cmp r3, #0
|
|
|
- 8010026: daf3 bge.n 8010010 <http_recv+0x198>
|
|
|
+ 800ff9c: 2b00 cmp r3, #0
|
|
|
+ 800ff9e: daf3 bge.n 800ff88 <http_recv+0x198>
|
|
|
{
|
|
|
BrowserFlag = 0;
|
|
|
TotalReceived = 0;
|
|
|
|
|
|
/* parse packet for Content-length field */
|
|
|
size = Parse_Content_Length(data, p->tot_len);
|
|
|
- 8010028: 4b56 ldr r3, [pc, #344] ; (8010184 <http_recv+0x30c>)
|
|
|
+ 800ffa0: 4b56 ldr r3, [pc, #344] ; (80100fc <http_recv+0x30c>)
|
|
|
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 801002a: f04f 0900 mov.w r9, #0
|
|
|
+ 800ffa2: f04f 0900 mov.w r9, #0
|
|
|
{
|
|
|
BrowserFlag = 0;
|
|
|
TotalReceived = 0;
|
|
|
|
|
|
/* parse packet for Content-length field */
|
|
|
size = Parse_Content_Length(data, p->tot_len);
|
|
|
- 801002e: 601a str r2, [r3, #0]
|
|
|
+ 800ffa6: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 8010030: e012 b.n 8010058 <http_recv+0x1e0>
|
|
|
+ 800ffa8: e012 b.n 800ffd0 <http_recv+0x1e0>
|
|
|
{
|
|
|
if (strncmp ((char*)(data+i), octet_stream, 13)==0)
|
|
|
- 8010032: eb06 0009 add.w r0, r6, r9
|
|
|
- 8010036: 4954 ldr r1, [pc, #336] ; (8010188 <http_recv+0x310>)
|
|
|
- 8010038: 220d movs r2, #13
|
|
|
- 801003a: f7f9 fc4f bl 80098dc <strncmp>
|
|
|
- 801003e: b948 cbnz r0, 8010054 <http_recv+0x1dc>
|
|
|
+ 800ffaa: eb06 0009 add.w r0, r6, r9
|
|
|
+ 800ffae: 4954 ldr r1, [pc, #336] ; (8010100 <http_recv+0x310>)
|
|
|
+ 800ffb0: 220d movs r2, #13
|
|
|
+ 800ffb2: f7f9 fc93 bl 80098dc <strncmp>
|
|
|
+ 800ffb6: b948 cbnz r0, 800ffcc <http_recv+0x1dc>
|
|
|
|
|
|
}
|
|
|
/* case of Mozilla Firefox v3.6 : we receive data in the POST packet*/
|
|
|
else
|
|
|
{
|
|
|
TotalReceived = len - (ContentLengthOffset + 4);
|
|
|
- 8010040: 4b4e ldr r3, [pc, #312] ; (801017c <http_recv+0x304>)
|
|
|
- 8010042: 681a ldr r2, [r3, #0]
|
|
|
- 8010044: 4b4c ldr r3, [pc, #304] ; (8010178 <http_recv+0x300>)
|
|
|
- 8010046: ebc2 0208 rsb r2, r2, r8
|
|
|
- 801004a: 3a04 subs r2, #4
|
|
|
+ 800ffb8: 4b4e ldr r3, [pc, #312] ; (80100f4 <http_recv+0x304>)
|
|
|
+ 800ffba: 681a ldr r2, [r3, #0]
|
|
|
+ 800ffbc: 4b4c ldr r3, [pc, #304] ; (80100f0 <http_recv+0x300>)
|
|
|
+ 800ffbe: ebc2 0208 rsb r2, r2, r8
|
|
|
+ 800ffc2: 3a04 subs r2, #4
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
{
|
|
|
if (strncmp ((char*)(data+i), octet_stream, 13)==0)
|
|
|
{
|
|
|
DataOffset = i + 16;
|
|
|
- 801004c: f109 0a10 add.w sl, r9, #16
|
|
|
+ 800ffc4: f109 0a10 add.w sl, r9, #16
|
|
|
|
|
|
}
|
|
|
/* case of Mozilla Firefox v3.6 : we receive data in the POST packet*/
|
|
|
else
|
|
|
{
|
|
|
TotalReceived = len - (ContentLengthOffset + 4);
|
|
|
- 8010050: 601a str r2, [r3, #0]
|
|
|
- 8010052: e006 b.n 8010062 <http_recv+0x1ea>
|
|
|
+ 800ffc8: 601a str r2, [r3, #0]
|
|
|
+ 800ffca: e006 b.n 800ffda <http_recv+0x1ea>
|
|
|
|
|
|
/* parse packet for Content-length field */
|
|
|
size = Parse_Content_Length(data, p->tot_len);
|
|
|
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 8010054: f109 0901 add.w r9, r9, #1
|
|
|
- 8010058: 45c1 cmp r9, r8
|
|
|
- 801005a: dbea blt.n 8010032 <http_recv+0x1ba>
|
|
|
- 801005c: e114 b.n 8010288 <http_recv+0x410>
|
|
|
+ 800ffcc: f109 0901 add.w r9, r9, #1
|
|
|
+ 800ffd0: 45c1 cmp r9, r8
|
|
|
+ 800ffd2: dbea blt.n 800ffaa <http_recv+0x1ba>
|
|
|
+ 800ffd4: e114 b.n 8010200 <http_recv+0x410>
|
|
|
if (fEraseFlash) {
|
|
|
FLASH_If_Erase(USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
fEraseFlash = false;
|
|
|
}
|
|
|
|
|
|
DataOffset = 0;
|
|
|
- 801005e: f04f 0a00 mov.w sl, #0
|
|
|
+ 800ffd6: f04f 0a00 mov.w sl, #0
|
|
|
{
|
|
|
TotalReceived = len - (ContentLengthOffset + 4);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
if (((DataFlag ==1)&&(BrowserFlag==1)) || ((DataFlag ==0)&&(BrowserFlag==0)))
|
|
|
- 8010062: 4b42 ldr r3, [pc, #264] ; (801016c <http_recv+0x2f4>)
|
|
|
- 8010064: 681a ldr r2, [r3, #0]
|
|
|
- 8010066: 2a01 cmp r2, #1
|
|
|
- 8010068: d103 bne.n 8010072 <http_recv+0x1fa>
|
|
|
- 801006a: 4a42 ldr r2, [pc, #264] ; (8010174 <http_recv+0x2fc>)
|
|
|
- 801006c: 6812 ldr r2, [r2, #0]
|
|
|
- 801006e: 2a01 cmp r2, #1
|
|
|
- 8010070: d008 beq.n 8010084 <http_recv+0x20c>
|
|
|
- 8010072: 681b ldr r3, [r3, #0]
|
|
|
- 8010074: 2b00 cmp r3, #0
|
|
|
- 8010076: f040 80ae bne.w 80101d6 <http_recv+0x35e>
|
|
|
- 801007a: 4b3e ldr r3, [pc, #248] ; (8010174 <http_recv+0x2fc>)
|
|
|
- 801007c: 681b ldr r3, [r3, #0]
|
|
|
- 801007e: 2b00 cmp r3, #0
|
|
|
- 8010080: f040 80a9 bne.w 80101d6 <http_recv+0x35e>
|
|
|
+ 800ffda: 4b42 ldr r3, [pc, #264] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 800ffdc: 681a ldr r2, [r3, #0]
|
|
|
+ 800ffde: 2a01 cmp r2, #1
|
|
|
+ 800ffe0: d103 bne.n 800ffea <http_recv+0x1fa>
|
|
|
+ 800ffe2: 4a42 ldr r2, [pc, #264] ; (80100ec <http_recv+0x2fc>)
|
|
|
+ 800ffe4: 6812 ldr r2, [r2, #0]
|
|
|
+ 800ffe6: 2a01 cmp r2, #1
|
|
|
+ 800ffe8: d008 beq.n 800fffc <http_recv+0x20c>
|
|
|
+ 800ffea: 681b ldr r3, [r3, #0]
|
|
|
+ 800ffec: 2b00 cmp r3, #0
|
|
|
+ 800ffee: f040 80ae bne.w 801014e <http_recv+0x35e>
|
|
|
+ 800fff2: 4b3e ldr r3, [pc, #248] ; (80100ec <http_recv+0x2fc>)
|
|
|
+ 800fff4: 681b ldr r3, [r3, #0]
|
|
|
+ 800fff6: 2b00 cmp r3, #0
|
|
|
+ 800fff8: f040 80a9 bne.w 801014e <http_recv+0x35e>
|
|
|
{
|
|
|
if ((DataFlag ==0)&&(BrowserFlag==0))
|
|
|
- 8010084: 4b39 ldr r3, [pc, #228] ; (801016c <http_recv+0x2f4>)
|
|
|
- 8010086: 6819 ldr r1, [r3, #0]
|
|
|
- 8010088: 461a mov r2, r3
|
|
|
- 801008a: b919 cbnz r1, 8010094 <http_recv+0x21c>
|
|
|
- 801008c: 4939 ldr r1, [pc, #228] ; (8010174 <http_recv+0x2fc>)
|
|
|
- 801008e: 6809 ldr r1, [r1, #0]
|
|
|
- 8010090: b901 cbnz r1, 8010094 <http_recv+0x21c>
|
|
|
- 8010092: e01d b.n 80100d0 <http_recv+0x258>
|
|
|
+ 800fffc: 4b39 ldr r3, [pc, #228] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 800fffe: 6819 ldr r1, [r3, #0]
|
|
|
+ 8010000: 461a mov r2, r3
|
|
|
+ 8010002: b919 cbnz r1, 801000c <http_recv+0x21c>
|
|
|
+ 8010004: 4939 ldr r1, [pc, #228] ; (80100ec <http_recv+0x2fc>)
|
|
|
+ 8010006: 6809 ldr r1, [r1, #0]
|
|
|
+ 8010008: b901 cbnz r1, 801000c <http_recv+0x21c>
|
|
|
+ 801000a: e01d b.n 8010048 <http_recv+0x258>
|
|
|
{
|
|
|
DataFlag++;
|
|
|
}
|
|
|
else if ((DataFlag ==1)&&(BrowserFlag==1))
|
|
|
- 8010094: 6813 ldr r3, [r2, #0]
|
|
|
- 8010096: 2b01 cmp r3, #1
|
|
|
- 8010098: d11d bne.n 80100d6 <http_recv+0x25e>
|
|
|
- 801009a: 4b36 ldr r3, [pc, #216] ; (8010174 <http_recv+0x2fc>)
|
|
|
- 801009c: 681b ldr r3, [r3, #0]
|
|
|
- 801009e: 2b01 cmp r3, #1
|
|
|
- 80100a0: d119 bne.n 80100d6 <http_recv+0x25e>
|
|
|
- 80100a2: e00c b.n 80100be <http_recv+0x246>
|
|
|
+ 801000c: 6813 ldr r3, [r2, #0]
|
|
|
+ 801000e: 2b01 cmp r3, #1
|
|
|
+ 8010010: d11d bne.n 801004e <http_recv+0x25e>
|
|
|
+ 8010012: 4b36 ldr r3, [pc, #216] ; (80100ec <http_recv+0x2fc>)
|
|
|
+ 8010014: 681b ldr r3, [r3, #0]
|
|
|
+ 8010016: 2b01 cmp r3, #1
|
|
|
+ 8010018: d119 bne.n 801004e <http_recv+0x25e>
|
|
|
+ 801001a: e00c b.n 8010036 <http_recv+0x246>
|
|
|
{
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
{
|
|
|
if (strncmp ((char*)(data+i), octet_stream, 13)==0)
|
|
|
- 80100a4: eb06 0009 add.w r0, r6, r9
|
|
|
- 80100a8: 4937 ldr r1, [pc, #220] ; (8010188 <http_recv+0x310>)
|
|
|
- 80100aa: 220d movs r2, #13
|
|
|
- 80100ac: f7f9 fc16 bl 80098dc <strncmp>
|
|
|
- 80100b0: b910 cbnz r0, 80100b8 <http_recv+0x240>
|
|
|
+ 801001c: eb06 0009 add.w r0, r6, r9
|
|
|
+ 8010020: 4937 ldr r1, [pc, #220] ; (8010100 <http_recv+0x310>)
|
|
|
+ 8010022: 220d movs r2, #13
|
|
|
+ 8010024: f7f9 fc5a bl 80098dc <strncmp>
|
|
|
+ 8010028: b910 cbnz r0, 8010030 <http_recv+0x240>
|
|
|
{
|
|
|
DataOffset = i+16;
|
|
|
- 80100b2: f109 0a10 add.w sl, r9, #16
|
|
|
+ 801002a: f109 0a10 add.w sl, r9, #16
|
|
|
break;
|
|
|
- 80100b6: e006 b.n 80100c6 <http_recv+0x24e>
|
|
|
+ 801002e: e006 b.n 801003e <http_recv+0x24e>
|
|
|
DataFlag++;
|
|
|
}
|
|
|
else if ((DataFlag ==1)&&(BrowserFlag==1))
|
|
|
{
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 80100b8: f109 0901 add.w r9, r9, #1
|
|
|
- 80100bc: e001 b.n 80100c2 <http_recv+0x24a>
|
|
|
+ 8010030: f109 0901 add.w r9, r9, #1
|
|
|
+ 8010034: e001 b.n 801003a <http_recv+0x24a>
|
|
|
{
|
|
|
if ((DataFlag ==0)&&(BrowserFlag==0))
|
|
|
{
|
|
|
DataFlag++;
|
|
|
}
|
|
|
else if ((DataFlag ==1)&&(BrowserFlag==1))
|
|
|
- 80100be: f04f 0900 mov.w r9, #0
|
|
|
+ 8010036: f04f 0900 mov.w r9, #0
|
|
|
{
|
|
|
/* parse packet for the octet-stream field */
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 80100c2: 45c1 cmp r9, r8
|
|
|
- 80100c4: dbee blt.n 80100a4 <http_recv+0x22c>
|
|
|
+ 801003a: 45c1 cmp r9, r8
|
|
|
+ 801003c: dbee blt.n 801001c <http_recv+0x22c>
|
|
|
{
|
|
|
DataOffset = i+16;
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
TotalReceived += len;
|
|
|
- 80100c6: 4b2c ldr r3, [pc, #176] ; (8010178 <http_recv+0x300>)
|
|
|
- 80100c8: 681a ldr r2, [r3, #0]
|
|
|
- 80100ca: 4442 add r2, r8
|
|
|
- 80100cc: 601a str r2, [r3, #0]
|
|
|
+ 801003e: 4b2c ldr r3, [pc, #176] ; (80100f0 <http_recv+0x300>)
|
|
|
+ 8010040: 681a ldr r2, [r3, #0]
|
|
|
+ 8010042: 4442 add r2, r8
|
|
|
+ 8010044: 601a str r2, [r3, #0]
|
|
|
DataFlag++;
|
|
|
- 80100ce: 4b27 ldr r3, [pc, #156] ; (801016c <http_recv+0x2f4>)
|
|
|
- 80100d0: 681a ldr r2, [r3, #0]
|
|
|
- 80100d2: 3201 adds r2, #1
|
|
|
- 80100d4: 601a str r2, [r3, #0]
|
|
|
+ 8010046: 4b27 ldr r3, [pc, #156] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 8010048: 681a ldr r2, [r3, #0]
|
|
|
+ 801004a: 3201 adds r2, #1
|
|
|
+ 801004c: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* parse packet for the filename field */
|
|
|
FilenameOffset = 0;
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 80100d6: f04f 0900 mov.w r9, #0
|
|
|
- 80100da: e00b b.n 80100f4 <http_recv+0x27c>
|
|
|
+ 801004e: f04f 0900 mov.w r9, #0
|
|
|
+ 8010052: e00b b.n 801006c <http_recv+0x27c>
|
|
|
* @param err: LwIP error code
|
|
|
* @retval err
|
|
|
*/
|
|
|
/* goback.cgi - возврат в основную прошивку */
|
|
|
/* upload.cgi - загрузка новой прошивки */
|
|
|
static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
|
|
|
- 80100dc: eb06 0b09 add.w fp, r6, r9
|
|
|
+ 8010054: eb06 0b09 add.w fp, r6, r9
|
|
|
|
|
|
/* parse packet for the filename field */
|
|
|
FilenameOffset = 0;
|
|
|
for (i = 0; i < len; i++)
|
|
|
{
|
|
|
if (strncmp ((char*)(data+i), "filename=", 9)==0)
|
|
|
- 80100e0: 4658 mov r0, fp
|
|
|
- 80100e2: 492a ldr r1, [pc, #168] ; (801018c <http_recv+0x314>)
|
|
|
- 80100e4: 2209 movs r2, #9
|
|
|
- 80100e6: f7f9 fbf9 bl 80098dc <strncmp>
|
|
|
- 80100ea: b908 cbnz r0, 80100f0 <http_recv+0x278>
|
|
|
- 80100ec: 4603 mov r3, r0
|
|
|
- 80100ee: e056 b.n 801019e <http_recv+0x326>
|
|
|
+ 8010058: 4658 mov r0, fp
|
|
|
+ 801005a: 492a ldr r1, [pc, #168] ; (8010104 <http_recv+0x314>)
|
|
|
+ 801005c: 2209 movs r2, #9
|
|
|
+ 801005e: f7f9 fc3d bl 80098dc <strncmp>
|
|
|
+ 8010062: b908 cbnz r0, 8010068 <http_recv+0x278>
|
|
|
+ 8010064: 4603 mov r3, r0
|
|
|
+ 8010066: e056 b.n 8010116 <http_recv+0x326>
|
|
|
DataFlag++;
|
|
|
}
|
|
|
|
|
|
/* parse packet for the filename field */
|
|
|
FilenameOffset = 0;
|
|
|
for (i = 0; i < len; i++)
|
|
|
- 80100f0: f109 0901 add.w r9, r9, #1
|
|
|
- 80100f4: 45c1 cmp r9, r8
|
|
|
- 80100f6: dbf1 blt.n 80100dc <http_recv+0x264>
|
|
|
+ 8010068: f109 0901 add.w r9, r9, #1
|
|
|
+ 801006c: 45c1 cmp r9, r8
|
|
|
+ 801006e: dbf1 blt.n 8010054 <http_recv+0x264>
|
|
|
filename[i] = 0x0;
|
|
|
}
|
|
|
|
|
|
if (i==0)
|
|
|
{
|
|
|
htmlpage = FileUploadPage;
|
|
|
- 80100f8: 4b19 ldr r3, [pc, #100] ; (8010160 <http_recv+0x2e8>)
|
|
|
+ 8010070: 4b19 ldr r3, [pc, #100] ; (80100d8 <http_recv+0x2e8>)
|
|
|
/* no filename, in this case reload upload page */
|
|
|
fs_open("/upload.html", &file);
|
|
|
- 80100fa: 4825 ldr r0, [pc, #148] ; (8010190 <http_recv+0x318>)
|
|
|
+ 8010072: 4825 ldr r0, [pc, #148] ; (8010108 <http_recv+0x318>)
|
|
|
filename[i] = 0x0;
|
|
|
}
|
|
|
|
|
|
if (i==0)
|
|
|
{
|
|
|
htmlpage = FileUploadPage;
|
|
|
- 80100fc: 2201 movs r2, #1
|
|
|
+ 8010074: 2201 movs r2, #1
|
|
|
/* no filename, in this case reload upload page */
|
|
|
fs_open("/upload.html", &file);
|
|
|
- 80100fe: 4669 mov r1, sp
|
|
|
+ 8010076: 4669 mov r1, sp
|
|
|
filename[i] = 0x0;
|
|
|
}
|
|
|
|
|
|
if (i==0)
|
|
|
{
|
|
|
htmlpage = FileUploadPage;
|
|
|
- 8010100: 701a strb r2, [r3, #0]
|
|
|
+ 8010078: 701a strb r2, [r3, #0]
|
|
|
/* no filename, in this case reload upload page */
|
|
|
fs_open("/upload.html", &file);
|
|
|
- 8010102: f7ff fe55 bl 800fdb0 <fs_open>
|
|
|
+ 801007a: f7ff fe55 bl 800fd28 <fs_open>
|
|
|
hs->file = file.data;
|
|
|
- 8010106: 9b00 ldr r3, [sp, #0]
|
|
|
- 8010108: 6023 str r3, [r4, #0]
|
|
|
+ 801007e: 9b00 ldr r3, [sp, #0]
|
|
|
+ 8010080: 6023 str r3, [r4, #0]
|
|
|
hs->left = file.len;
|
|
|
- 801010a: 9b01 ldr r3, [sp, #4]
|
|
|
+ 8010082: 9b01 ldr r3, [sp, #4]
|
|
|
pbuf_free(p);
|
|
|
- 801010c: 4638 mov r0, r7
|
|
|
+ 8010084: 4638 mov r0, r7
|
|
|
{
|
|
|
htmlpage = FileUploadPage;
|
|
|
/* no filename, in this case reload upload page */
|
|
|
fs_open("/upload.html", &file);
|
|
|
hs->file = file.data;
|
|
|
hs->left = file.len;
|
|
|
- 801010e: 6063 str r3, [r4, #4]
|
|
|
+ 8010086: 6063 str r3, [r4, #4]
|
|
|
pbuf_free(p);
|
|
|
- 8010110: f7fb f9d8 bl 800b4c4 <pbuf_free>
|
|
|
+ 8010088: f7fb fa1c bl 800b4c4 <pbuf_free>
|
|
|
|
|
|
/* send index.html page */
|
|
|
send_data(pcb, hs);
|
|
|
- 8010114: 4628 mov r0, r5
|
|
|
- 8010116: 4621 mov r1, r4
|
|
|
- 8010118: f7ff fe0a bl 800fd30 <send_data>
|
|
|
+ 801008c: 4628 mov r0, r5
|
|
|
+ 801008e: 4621 mov r1, r4
|
|
|
+ 8010090: f7ff fe0a bl 800fca8 <send_data>
|
|
|
|
|
|
/* Tell TCP that we wish be to informed of data that has been
|
|
|
successfully sent by a call to the http_sent() function. */
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
- 801011c: 4628 mov r0, r5
|
|
|
- 801011e: 490a ldr r1, [pc, #40] ; (8010148 <http_recv+0x2d0>)
|
|
|
- 8010120: f7fb fc96 bl 800ba50 <tcp_sent>
|
|
|
+ 8010094: 4628 mov r0, r5
|
|
|
+ 8010096: 490a ldr r1, [pc, #40] ; (80100c0 <http_recv+0x2d0>)
|
|
|
+ 8010098: f7fb fcda bl 800ba50 <tcp_sent>
|
|
|
DataFlag=0;
|
|
|
- 8010124: 4b11 ldr r3, [pc, #68] ; (801016c <http_recv+0x2f4>)
|
|
|
- 8010126: 2200 movs r2, #0
|
|
|
- 8010128: 601a str r2, [r3, #0]
|
|
|
- 801012a: e0bb b.n 80102a4 <http_recv+0x42c>
|
|
|
- 801012c: 20006d80 .word 0x20006d80
|
|
|
- 8010130: 2000869d .word 0x2000869d
|
|
|
- 8010134: 08013564 .word 0x08013564
|
|
|
- 8010138: 0801356a .word 0x0801356a
|
|
|
- 801013c: 0801356e .word 0x0801356e
|
|
|
- 8010140: 0801357a .word 0x0801357a
|
|
|
- 8010144: 0801357e .word 0x0801357e
|
|
|
- 8010148: 080102e5 .word 0x080102e5
|
|
|
- 801014c: 08013589 .word 0x08013589
|
|
|
- 8010150: e000ed00 .word 0xe000ed00
|
|
|
- 8010154: 05fa0004 .word 0x05fa0004
|
|
|
- 8010158: 08013599 .word 0x08013599
|
|
|
- 801015c: 0801359d .word 0x0801359d
|
|
|
- 8010160: 2000869c .word 0x2000869c
|
|
|
- 8010164: 080135aa .word 0x080135aa
|
|
|
- 8010168: 080135b6 .word 0x080135b6
|
|
|
- 801016c: 20006d9c .word 0x20006d9c
|
|
|
- 8010170: 08020000 .word 0x08020000
|
|
|
- 8010174: 20006d98 .word 0x20006d98
|
|
|
- 8010178: 20006da0 .word 0x20006da0
|
|
|
- 801017c: 20006d88 .word 0x20006d88
|
|
|
- 8010180: 08012231 .word 0x08012231
|
|
|
- 8010184: 20006da4 .word 0x20006da4
|
|
|
- 8010188: 080129a8 .word 0x080129a8
|
|
|
- 801018c: 080135c7 .word 0x080135c7
|
|
|
- 8010190: 080135d1 .word 0x080135d1
|
|
|
- 8010194: 20000114 .word 0x20000114
|
|
|
+ 801009c: 4b11 ldr r3, [pc, #68] ; (80100e4 <http_recv+0x2f4>)
|
|
|
+ 801009e: 2200 movs r2, #0
|
|
|
+ 80100a0: 601a str r2, [r3, #0]
|
|
|
+ 80100a2: e0bb b.n 801021c <http_recv+0x42c>
|
|
|
+ 80100a4: 20006d80 .word 0x20006d80
|
|
|
+ 80100a8: 200084d9 .word 0x200084d9
|
|
|
+ 80100ac: 080134c4 .word 0x080134c4
|
|
|
+ 80100b0: 080134ca .word 0x080134ca
|
|
|
+ 80100b4: 080134ce .word 0x080134ce
|
|
|
+ 80100b8: 080134da .word 0x080134da
|
|
|
+ 80100bc: 080134de .word 0x080134de
|
|
|
+ 80100c0: 0801025d .word 0x0801025d
|
|
|
+ 80100c4: 080134e9 .word 0x080134e9
|
|
|
+ 80100c8: e000ed00 .word 0xe000ed00
|
|
|
+ 80100cc: 05fa0004 .word 0x05fa0004
|
|
|
+ 80100d0: 080134f9 .word 0x080134f9
|
|
|
+ 80100d4: 080134fd .word 0x080134fd
|
|
|
+ 80100d8: 200084d8 .word 0x200084d8
|
|
|
+ 80100dc: 0801350a .word 0x0801350a
|
|
|
+ 80100e0: 08013516 .word 0x08013516
|
|
|
+ 80100e4: 20006d9c .word 0x20006d9c
|
|
|
+ 80100e8: 08020000 .word 0x08020000
|
|
|
+ 80100ec: 20006d98 .word 0x20006d98
|
|
|
+ 80100f0: 20006da0 .word 0x20006da0
|
|
|
+ 80100f4: 20006d88 .word 0x20006d88
|
|
|
+ 80100f8: 08012192 .word 0x08012192
|
|
|
+ 80100fc: 20006da4 .word 0x20006da4
|
|
|
+ 8010100: 08012908 .word 0x08012908
|
|
|
+ 8010104: 08013527 .word 0x08013527
|
|
|
+ 8010108: 08013531 .word 0x08013531
|
|
|
+ 801010c: 20000114 .word 0x20000114
|
|
|
i = 0;
|
|
|
if (FilenameOffset)
|
|
|
{
|
|
|
while((*(data+FilenameOffset + i)!=0x22 )&&(i<13))
|
|
|
{
|
|
|
filename[i] = *(data+FilenameOffset + i);
|
|
|
- 8010198: a902 add r1, sp, #8
|
|
|
- 801019a: 545a strb r2, [r3, r1]
|
|
|
+ 8010110: a902 add r1, sp, #8
|
|
|
+ 8010112: 545a strb r2, [r3, r1]
|
|
|
i++;
|
|
|
- 801019c: 3301 adds r3, #1
|
|
|
+ 8010114: 3301 adds r3, #1
|
|
|
* @param err: LwIP error code
|
|
|
* @retval err
|
|
|
*/
|
|
|
/* goback.cgi - возврат в основную прошивку */
|
|
|
/* upload.cgi - загрузка новой прошивки */
|
|
|
static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
|
|
|
- 801019e: eb0b 0203 add.w r2, fp, r3
|
|
|
+ 8010116: eb0b 0203 add.w r2, fp, r3
|
|
|
}
|
|
|
}
|
|
|
i = 0;
|
|
|
if (FilenameOffset)
|
|
|
{
|
|
|
while((*(data+FilenameOffset + i)!=0x22 )&&(i<13))
|
|
|
- 80101a2: 7a92 ldrb r2, [r2, #10]
|
|
|
- 80101a4: 2a22 cmp r2, #34 ; 0x22
|
|
|
- 80101a6: d001 beq.n 80101ac <http_recv+0x334>
|
|
|
- 80101a8: 2b0d cmp r3, #13
|
|
|
- 80101aa: d1f5 bne.n 8010198 <http_recv+0x320>
|
|
|
+ 801011a: 7a92 ldrb r2, [r2, #10]
|
|
|
+ 801011c: 2a22 cmp r2, #34 ; 0x22
|
|
|
+ 801011e: d001 beq.n 8010124 <http_recv+0x334>
|
|
|
+ 8010120: 2b0d cmp r3, #13
|
|
|
+ 8010122: d1f5 bne.n 8010110 <http_recv+0x320>
|
|
|
{
|
|
|
filename[i] = *(data+FilenameOffset + i);
|
|
|
i++;
|
|
|
}
|
|
|
filename[i] = 0x0;
|
|
|
- 80101ac: a906 add r1, sp, #24
|
|
|
- 80101ae: 18ca adds r2, r1, r3
|
|
|
- 80101b0: f04f 0900 mov.w r9, #0
|
|
|
- 80101b4: f802 9c10 strb.w r9, [r2, #-16]
|
|
|
+ 8010124: a906 add r1, sp, #24
|
|
|
+ 8010126: 18ca adds r2, r1, r3
|
|
|
+ 8010128: f04f 0900 mov.w r9, #0
|
|
|
+ 801012c: f802 9c10 strb.w r9, [r2, #-16]
|
|
|
}
|
|
|
|
|
|
if (i==0)
|
|
|
- 80101b8: 2b00 cmp r3, #0
|
|
|
- 80101ba: d09d beq.n 80100f8 <http_recv+0x280>
|
|
|
+ 8010130: 2b00 cmp r3, #0
|
|
|
+ 8010132: d09d beq.n 8010070 <http_recv+0x280>
|
|
|
return ERR_OK;
|
|
|
|
|
|
}
|
|
|
|
|
|
PRINT_USART("\n\r IAP using HTTP \n\r");
|
|
|
sprintf(debugMsg, "File: %s\n\r",filename);
|
|
|
- 80101bc: aa02 add r2, sp, #8
|
|
|
- 80101be: 493b ldr r1, [pc, #236] ; (80102ac <http_recv+0x434>)
|
|
|
- 80101c0: 483b ldr r0, [pc, #236] ; (80102b0 <http_recv+0x438>)
|
|
|
- 80101c2: f001 fa7d bl 80116c0 <tfp_sprintf>
|
|
|
+ 8010134: aa02 add r2, sp, #8
|
|
|
+ 8010136: 493b ldr r1, [pc, #236] ; (8010224 <http_recv+0x434>)
|
|
|
+ 8010138: 483b ldr r0, [pc, #236] ; (8010228 <http_recv+0x438>)
|
|
|
+ 801013a: f001 fa7d bl 8011638 <tfp_sprintf>
|
|
|
PRINT_USART(debugMsg);
|
|
|
PRINT_USART("State: Erasing...\n\r");
|
|
|
|
|
|
TotalData =0 ;
|
|
|
- 80101c6: 4b3b ldr r3, [pc, #236] ; (80102b4 <http_recv+0x43c>)
|
|
|
- 80101c8: f8c3 9000 str.w r9, [r3]
|
|
|
+ 801013e: 4b3b ldr r3, [pc, #236] ; (801022c <http_recv+0x43c>)
|
|
|
+ 8010140: f8c3 9000 str.w r9, [r3]
|
|
|
/* init flash */
|
|
|
FLASH_If_Init();
|
|
|
- 80101cc: f7ff fa3e bl 800f64c <FLASH_If_Init>
|
|
|
+ 8010144: f7ff fa82 bl 800f64c <FLASH_If_Init>
|
|
|
/* erase user flash area */
|
|
|
//FLASH_If_Erase(USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
|
|
|
FlashWriteAddress = USER_FLASH_FIRST_PAGE_ADDRESS;
|
|
|
- 80101d0: 4a39 ldr r2, [pc, #228] ; (80102b8 <http_recv+0x440>)
|
|
|
- 80101d2: 4b3a ldr r3, [pc, #232] ; (80102bc <http_recv+0x444>)
|
|
|
- 80101d4: e002 b.n 80101dc <http_recv+0x364>
|
|
|
+ 8010148: 4a39 ldr r2, [pc, #228] ; (8010230 <http_recv+0x440>)
|
|
|
+ 801014a: 4b3a ldr r3, [pc, #232] ; (8010234 <http_recv+0x444>)
|
|
|
+ 801014c: e002 b.n 8010154 <http_recv+0x364>
|
|
|
PRINT_USART("\n\rState: Programming..\n\r");
|
|
|
}
|
|
|
/* DataFlag >1 => the packet is data only */
|
|
|
else
|
|
|
{
|
|
|
TotalReceived +=len;
|
|
|
- 80101d6: 4b3a ldr r3, [pc, #232] ; (80102c0 <http_recv+0x448>)
|
|
|
- 80101d8: 681a ldr r2, [r3, #0]
|
|
|
- 80101da: 4442 add r2, r8
|
|
|
- 80101dc: 601a str r2, [r3, #0]
|
|
|
+ 801014e: 4b3a ldr r3, [pc, #232] ; (8010238 <http_recv+0x448>)
|
|
|
+ 8010150: 681a ldr r2, [r3, #0]
|
|
|
+ 8010152: 4442 add r2, r8
|
|
|
+ 8010154: 601a str r2, [r3, #0]
|
|
|
|
|
|
ptr = (char*)(data + DataOffset);
|
|
|
len-= DataOffset;
|
|
|
|
|
|
/* update Total data received counter */
|
|
|
TotalData +=len;
|
|
|
- 80101de: 4b35 ldr r3, [pc, #212] ; (80102b4 <http_recv+0x43c>)
|
|
|
- 80101e0: 681a ldr r2, [r3, #0]
|
|
|
+ 8010156: 4b35 ldr r3, [pc, #212] ; (801022c <http_recv+0x43c>)
|
|
|
+ 8010158: 681a ldr r2, [r3, #0]
|
|
|
{
|
|
|
TotalReceived +=len;
|
|
|
}
|
|
|
|
|
|
ptr = (char*)(data + DataOffset);
|
|
|
len-= DataOffset;
|
|
|
- 80101e2: ebca 0108 rsb r1, sl, r8
|
|
|
+ 801015a: ebca 0108 rsb r1, sl, r8
|
|
|
|
|
|
/* update Total data received counter */
|
|
|
TotalData +=len;
|
|
|
- 80101e6: 188a adds r2, r1, r2
|
|
|
- 80101e8: 601a str r2, [r3, #0]
|
|
|
+ 801015e: 188a adds r2, r1, r2
|
|
|
+ 8010160: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* check if last data packet */
|
|
|
if (TotalReceived == size)
|
|
|
- 80101ea: 4b36 ldr r3, [pc, #216] ; (80102c4 <http_recv+0x44c>)
|
|
|
- 80101ec: 4a34 ldr r2, [pc, #208] ; (80102c0 <http_recv+0x448>)
|
|
|
- 80101ee: 681b ldr r3, [r3, #0]
|
|
|
- 80101f0: 6812 ldr r2, [r2, #0]
|
|
|
- 80101f2: 429a cmp r2, r3
|
|
|
+ 8010162: 4b36 ldr r3, [pc, #216] ; (801023c <http_recv+0x44c>)
|
|
|
+ 8010164: 4a34 ldr r2, [pc, #208] ; (8010238 <http_recv+0x448>)
|
|
|
+ 8010166: 681b ldr r3, [r3, #0]
|
|
|
+ 8010168: 6812 ldr r2, [r2, #0]
|
|
|
+ 801016a: 429a cmp r2, r3
|
|
|
else
|
|
|
{
|
|
|
TotalReceived +=len;
|
|
|
}
|
|
|
|
|
|
ptr = (char*)(data + DataOffset);
|
|
|
- 80101f4: eb06 000a add.w r0, r6, sl
|
|
|
+ 801016c: eb06 000a add.w r0, r6, sl
|
|
|
|
|
|
/* update Total data received counter */
|
|
|
TotalData +=len;
|
|
|
|
|
|
/* check if last data packet */
|
|
|
if (TotalReceived == size)
|
|
|
- 80101f8: d13d bne.n 8010276 <http_recv+0x3fe>
|
|
|
+ 8010170: d13d bne.n 80101ee <http_recv+0x3fe>
|
|
|
}
|
|
|
len -= i;
|
|
|
TotalData -= i;
|
|
|
*/
|
|
|
/* write data in Flash */
|
|
|
if (len)
|
|
|
- 80101fa: b109 cbz r1, 8010200 <http_recv+0x388>
|
|
|
+ 8010172: b109 cbz r1, 8010178 <http_recv+0x388>
|
|
|
IAP_HTTP_writedata(ptr,len);
|
|
|
- 80101fc: f7ff fdee bl 800fddc <IAP_HTTP_writedata>
|
|
|
+ 8010174: f7ff fdee bl 800fd54 <IAP_HTTP_writedata>
|
|
|
|
|
|
DataFlag=0;
|
|
|
- 8010200: 4b31 ldr r3, [pc, #196] ; (80102c8 <http_recv+0x450>)
|
|
|
+ 8010178: 4b31 ldr r3, [pc, #196] ; (8010240 <http_recv+0x450>)
|
|
|
htmlpage = UploadDonePage;
|
|
|
- 8010202: 4e32 ldr r6, [pc, #200] ; (80102cc <http_recv+0x454>)
|
|
|
+ 801017a: 4e32 ldr r6, [pc, #200] ; (8010244 <http_recv+0x454>)
|
|
|
|
|
|
PRINT_USART("Tot bytes Received:\n\r");
|
|
|
sprintf(debugMsg, "%d bytes \n\r",TotalData);
|
|
|
- 8010204: 4932 ldr r1, [pc, #200] ; (80102d0 <http_recv+0x458>)
|
|
|
- 8010206: 482a ldr r0, [pc, #168] ; (80102b0 <http_recv+0x438>)
|
|
|
+ 801017c: 4932 ldr r1, [pc, #200] ; (8010248 <http_recv+0x458>)
|
|
|
+ 801017e: 482a ldr r0, [pc, #168] ; (8010228 <http_recv+0x438>)
|
|
|
*/
|
|
|
/* write data in Flash */
|
|
|
if (len)
|
|
|
IAP_HTTP_writedata(ptr,len);
|
|
|
|
|
|
DataFlag=0;
|
|
|
- 8010208: 2200 movs r2, #0
|
|
|
- 801020a: 601a str r2, [r3, #0]
|
|
|
+ 8010180: 2200 movs r2, #0
|
|
|
+ 8010182: 601a str r2, [r3, #0]
|
|
|
htmlpage = UploadDonePage;
|
|
|
|
|
|
PRINT_USART("Tot bytes Received:\n\r");
|
|
|
sprintf(debugMsg, "%d bytes \n\r",TotalData);
|
|
|
- 801020c: 4b29 ldr r3, [pc, #164] ; (80102b4 <http_recv+0x43c>)
|
|
|
+ 8010184: 4b29 ldr r3, [pc, #164] ; (801022c <http_recv+0x43c>)
|
|
|
/* write data in Flash */
|
|
|
if (len)
|
|
|
IAP_HTTP_writedata(ptr,len);
|
|
|
|
|
|
DataFlag=0;
|
|
|
htmlpage = UploadDonePage;
|
|
|
- 801020e: f04f 0802 mov.w r8, #2
|
|
|
+ 8010186: f04f 0802 mov.w r8, #2
|
|
|
|
|
|
PRINT_USART("Tot bytes Received:\n\r");
|
|
|
sprintf(debugMsg, "%d bytes \n\r",TotalData);
|
|
|
- 8010212: 681a ldr r2, [r3, #0]
|
|
|
+ 801018a: 681a ldr r2, [r3, #0]
|
|
|
/* write data in Flash */
|
|
|
if (len)
|
|
|
IAP_HTTP_writedata(ptr,len);
|
|
|
|
|
|
DataFlag=0;
|
|
|
htmlpage = UploadDonePage;
|
|
|
- 8010214: f886 8000 strb.w r8, [r6]
|
|
|
+ 801018c: f886 8000 strb.w r8, [r6]
|
|
|
|
|
|
PRINT_USART("Tot bytes Received:\n\r");
|
|
|
sprintf(debugMsg, "%d bytes \n\r",TotalData);
|
|
|
- 8010218: f001 fa52 bl 80116c0 <tfp_sprintf>
|
|
|
+ 8010190: f001 fa52 bl 8011638 <tfp_sprintf>
|
|
|
PRINT_USART(debugMsg);
|
|
|
PRINT_USART("State: Prog Finished \n\r");
|
|
|
|
|
|
/* Проверяем CRC */
|
|
|
if (CRC_Read() == CRC_Calcucate()) {
|
|
|
- 801021c: f7ff f9fc bl 800f618 <CRC_Read>
|
|
|
- 8010220: 4681 mov r9, r0
|
|
|
- 8010222: f7ff f9ff bl 800f624 <CRC_Calcucate>
|
|
|
- 8010226: 4581 cmp r9, r0
|
|
|
- 8010228: d112 bne.n 8010250 <http_recv+0x3d8>
|
|
|
+ 8010194: f7ff fa40 bl 800f618 <CRC_Read>
|
|
|
+ 8010198: 4681 mov r9, r0
|
|
|
+ 801019a: f7ff fa43 bl 800f624 <CRC_Calcucate>
|
|
|
+ 801019e: 4581 cmp r9, r0
|
|
|
+ 80101a0: d112 bne.n 80101c8 <http_recv+0x3d8>
|
|
|
fs_open("/success.html", &file);
|
|
|
- 801022a: 4669 mov r1, sp
|
|
|
- 801022c: 4829 ldr r0, [pc, #164] ; (80102d4 <http_recv+0x45c>)
|
|
|
- 801022e: f7ff fdbf bl 800fdb0 <fs_open>
|
|
|
+ 80101a2: 4669 mov r1, sp
|
|
|
+ 80101a4: 4829 ldr r0, [pc, #164] ; (801024c <http_recv+0x45c>)
|
|
|
+ 80101a6: f7ff fdbf bl 800fd28 <fs_open>
|
|
|
hs->file = file.data;
|
|
|
- 8010232: 9b00 ldr r3, [sp, #0]
|
|
|
- 8010234: 6023 str r3, [r4, #0]
|
|
|
+ 80101aa: 9b00 ldr r3, [sp, #0]
|
|
|
+ 80101ac: 6023 str r3, [r4, #0]
|
|
|
hs->left = file.len;
|
|
|
- 8010236: 9b01 ldr r3, [sp, #4]
|
|
|
+ 80101ae: 9b01 ldr r3, [sp, #4]
|
|
|
send_data(pcb, hs);
|
|
|
- 8010238: 4628 mov r0, r5
|
|
|
+ 80101b0: 4628 mov r0, r5
|
|
|
|
|
|
/* Проверяем CRC */
|
|
|
if (CRC_Read() == CRC_Calcucate()) {
|
|
|
fs_open("/success.html", &file);
|
|
|
hs->file = file.data;
|
|
|
hs->left = file.len;
|
|
|
- 801023a: 6063 str r3, [r4, #4]
|
|
|
+ 80101b2: 6063 str r3, [r4, #4]
|
|
|
send_data(pcb, hs);
|
|
|
- 801023c: 4621 mov r1, r4
|
|
|
- 801023e: f7ff fd77 bl 800fd30 <send_data>
|
|
|
+ 80101b4: 4621 mov r1, r4
|
|
|
+ 80101b6: f7ff fd77 bl 800fca8 <send_data>
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
- 8010242: 4628 mov r0, r5
|
|
|
- 8010244: 4924 ldr r1, [pc, #144] ; (80102d8 <http_recv+0x460>)
|
|
|
- 8010246: f7fb fc03 bl 800ba50 <tcp_sent>
|
|
|
+ 80101ba: 4628 mov r0, r5
|
|
|
+ 80101bc: 4924 ldr r1, [pc, #144] ; (8010250 <http_recv+0x460>)
|
|
|
+ 80101be: f7fb fc47 bl 800ba50 <tcp_sent>
|
|
|
htmlpage = UploadDonePage;
|
|
|
- 801024a: f886 8000 strb.w r8, [r6]
|
|
|
- 801024e: e022 b.n 8010296 <http_recv+0x41e>
|
|
|
+ 80101c2: f886 8000 strb.w r8, [r6]
|
|
|
+ 80101c6: e022 b.n 801020e <http_recv+0x41e>
|
|
|
}
|
|
|
|
|
|
else
|
|
|
{
|
|
|
fs_open("/error.html", &file);
|
|
|
- 8010250: 4669 mov r1, sp
|
|
|
- 8010252: 4822 ldr r0, [pc, #136] ; (80102dc <http_recv+0x464>)
|
|
|
- 8010254: f7ff fdac bl 800fdb0 <fs_open>
|
|
|
+ 80101c8: 4669 mov r1, sp
|
|
|
+ 80101ca: 4822 ldr r0, [pc, #136] ; (8010254 <http_recv+0x464>)
|
|
|
+ 80101cc: f7ff fdac bl 800fd28 <fs_open>
|
|
|
hs->file = file.data;
|
|
|
- 8010258: 9b00 ldr r3, [sp, #0]
|
|
|
- 801025a: 6023 str r3, [r4, #0]
|
|
|
+ 80101d0: 9b00 ldr r3, [sp, #0]
|
|
|
+ 80101d2: 6023 str r3, [r4, #0]
|
|
|
hs->left = file.len;
|
|
|
- 801025c: 9b01 ldr r3, [sp, #4]
|
|
|
+ 80101d4: 9b01 ldr r3, [sp, #4]
|
|
|
send_data(pcb, hs);
|
|
|
- 801025e: 4628 mov r0, r5
|
|
|
+ 80101d6: 4628 mov r0, r5
|
|
|
|
|
|
else
|
|
|
{
|
|
|
fs_open("/error.html", &file);
|
|
|
hs->file = file.data;
|
|
|
hs->left = file.len;
|
|
|
- 8010260: 6063 str r3, [r4, #4]
|
|
|
+ 80101d8: 6063 str r3, [r4, #4]
|
|
|
send_data(pcb, hs);
|
|
|
- 8010262: 4621 mov r1, r4
|
|
|
- 8010264: f7ff fd64 bl 800fd30 <send_data>
|
|
|
+ 80101da: 4621 mov r1, r4
|
|
|
+ 80101dc: f7ff fd64 bl 800fca8 <send_data>
|
|
|
tcp_sent(pcb, http_sent);
|
|
|
- 8010268: 4628 mov r0, r5
|
|
|
- 801026a: 491b ldr r1, [pc, #108] ; (80102d8 <http_recv+0x460>)
|
|
|
- 801026c: f7fb fbf0 bl 800ba50 <tcp_sent>
|
|
|
+ 80101e0: 4628 mov r0, r5
|
|
|
+ 80101e2: 491b ldr r1, [pc, #108] ; (8010250 <http_recv+0x460>)
|
|
|
+ 80101e4: f7fb fc34 bl 800ba50 <tcp_sent>
|
|
|
htmlpage = UploadErrorPage;
|
|
|
- 8010270: 2303 movs r3, #3
|
|
|
- 8010272: 7033 strb r3, [r6, #0]
|
|
|
- 8010274: e00f b.n 8010296 <http_recv+0x41e>
|
|
|
+ 80101e8: 2303 movs r3, #3
|
|
|
+ 80101ea: 7033 strb r3, [r6, #0]
|
|
|
+ 80101ec: e00f b.n 801020e <http_recv+0x41e>
|
|
|
}
|
|
|
/* not last data packet */
|
|
|
else
|
|
|
{
|
|
|
/* write data in flash */
|
|
|
if(len)
|
|
|
- 8010276: b171 cbz r1, 8010296 <http_recv+0x41e>
|
|
|
+ 80101ee: b171 cbz r1, 801020e <http_recv+0x41e>
|
|
|
IAP_HTTP_writedata(ptr,len);
|
|
|
- 8010278: f7ff fdb0 bl 800fddc <IAP_HTTP_writedata>
|
|
|
- 801027c: e00b b.n 8010296 <http_recv+0x41e>
|
|
|
+ 80101f0: f7ff fdb0 bl 800fd54 <IAP_HTTP_writedata>
|
|
|
+ 80101f4: e00b b.n 801020e <http_recv+0x41e>
|
|
|
else
|
|
|
{
|
|
|
/* Bad HTTP requests */
|
|
|
PRINT_USART("Bad HTTP request\n\r");
|
|
|
|
|
|
pbuf_free(p);
|
|
|
- 801027e: 4638 mov r0, r7
|
|
|
- 8010280: f7fb f920 bl 800b4c4 <pbuf_free>
|
|
|
+ 80101f6: 4638 mov r0, r7
|
|
|
+ 80101f8: f7fb f964 bl 800b4c4 <pbuf_free>
|
|
|
close_conn(pcb, hs);
|
|
|
- 8010284: 4628 mov r0, r5
|
|
|
- 8010286: e00a b.n 801029e <http_recv+0x426>
|
|
|
+ 80101fc: 4628 mov r0, r5
|
|
|
+ 80101fe: e00a b.n 8010216 <http_recv+0x426>
|
|
|
}
|
|
|
}
|
|
|
/* case of MSIE8 : we do not receive data in the POST packet*/
|
|
|
if (DataOffset == 0)
|
|
|
{
|
|
|
DataFlag++;
|
|
|
- 8010288: 4b0f ldr r3, [pc, #60] ; (80102c8 <http_recv+0x450>)
|
|
|
- 801028a: 681a ldr r2, [r3, #0]
|
|
|
- 801028c: 3201 adds r2, #1
|
|
|
- 801028e: 601a str r2, [r3, #0]
|
|
|
+ 8010200: 4b0f ldr r3, [pc, #60] ; (8010240 <http_recv+0x450>)
|
|
|
+ 8010202: 681a ldr r2, [r3, #0]
|
|
|
+ 8010204: 3201 adds r2, #1
|
|
|
+ 8010206: 601a str r2, [r3, #0]
|
|
|
BrowserFlag = 1;
|
|
|
- 8010290: 4b13 ldr r3, [pc, #76] ; (80102e0 <http_recv+0x468>)
|
|
|
- 8010292: 2201 movs r2, #1
|
|
|
- 8010294: 601a str r2, [r3, #0]
|
|
|
+ 8010208: 4b13 ldr r3, [pc, #76] ; (8010258 <http_recv+0x468>)
|
|
|
+ 801020a: 2201 movs r2, #1
|
|
|
+ 801020c: 601a str r2, [r3, #0]
|
|
|
pbuf_free(p);
|
|
|
- 8010296: 4638 mov r0, r7
|
|
|
- 8010298: f7fb f914 bl 800b4c4 <pbuf_free>
|
|
|
- 801029c: e002 b.n 80102a4 <http_recv+0x42c>
|
|
|
+ 801020e: 4638 mov r0, r7
|
|
|
+ 8010210: f7fb f958 bl 800b4c4 <pbuf_free>
|
|
|
+ 8010214: e002 b.n 801021c <http_recv+0x42c>
|
|
|
if (err == ERR_OK && p == NULL)
|
|
|
{
|
|
|
/* received empty frame */
|
|
|
PRINT_USART("Received empty frame\n\r");
|
|
|
|
|
|
close_conn(pcb, hs);
|
|
|
- 801029e: 4621 mov r1, r4
|
|
|
- 80102a0: f7ff fd6a bl 800fd78 <close_conn>
|
|
|
+ 8010216: 4621 mov r1, r4
|
|
|
+ 8010218: f7ff fd6a bl 800fcf0 <close_conn>
|
|
|
}
|
|
|
return ERR_OK;
|
|
|
}
|
|
|
- 80102a4: 2000 movs r0, #0
|
|
|
- 80102a6: b007 add sp, #28
|
|
|
- 80102a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
- 80102ac: 080135de .word 0x080135de
|
|
|
- 80102b0: 20008674 .word 0x20008674
|
|
|
- 80102b4: 20006d8c .word 0x20006d8c
|
|
|
- 80102b8: 08020000 .word 0x08020000
|
|
|
- 80102bc: 20006d90 .word 0x20006d90
|
|
|
- 80102c0: 20006da0 .word 0x20006da0
|
|
|
- 80102c4: 20006da4 .word 0x20006da4
|
|
|
- 80102c8: 20006d9c .word 0x20006d9c
|
|
|
- 80102cc: 2000869c .word 0x2000869c
|
|
|
- 80102d0: 080135e9 .word 0x080135e9
|
|
|
- 80102d4: 080135f5 .word 0x080135f5
|
|
|
- 80102d8: 080102e5 .word 0x080102e5
|
|
|
- 80102dc: 08013603 .word 0x08013603
|
|
|
- 80102e0: 20006d98 .word 0x20006d98
|
|
|
-
|
|
|
-080102e4 <http_sent>:
|
|
|
+ 801021c: 2000 movs r0, #0
|
|
|
+ 801021e: b007 add sp, #28
|
|
|
+ 8010220: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
+ 8010224: 0801353e .word 0x0801353e
|
|
|
+ 8010228: 200084b0 .word 0x200084b0
|
|
|
+ 801022c: 20006d8c .word 0x20006d8c
|
|
|
+ 8010230: 08020000 .word 0x08020000
|
|
|
+ 8010234: 20006d90 .word 0x20006d90
|
|
|
+ 8010238: 20006da0 .word 0x20006da0
|
|
|
+ 801023c: 20006da4 .word 0x20006da4
|
|
|
+ 8010240: 20006d9c .word 0x20006d9c
|
|
|
+ 8010244: 200084d8 .word 0x200084d8
|
|
|
+ 8010248: 08013549 .word 0x08013549
|
|
|
+ 801024c: 08013555 .word 0x08013555
|
|
|
+ 8010250: 0801025d .word 0x0801025d
|
|
|
+ 8010254: 08013563 .word 0x08013563
|
|
|
+ 8010258: 20006d98 .word 0x20006d98
|
|
|
+
|
|
|
+0801025c <http_sent>:
|
|
|
* @param pcb: pointer on tcp_pcb structure
|
|
|
* @param len
|
|
|
* @retval err : LwIP error code
|
|
|
*/
|
|
|
static err_t http_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
|
|
|
{
|
|
|
- 80102e4: b508 push {r3, lr}
|
|
|
- 80102e6: 4603 mov r3, r0
|
|
|
- 80102e8: 4608 mov r0, r1
|
|
|
+ 801025c: b508 push {r3, lr}
|
|
|
+ 801025e: 4603 mov r3, r0
|
|
|
+ 8010260: 4608 mov r0, r1
|
|
|
struct http_state *hs;
|
|
|
hs = arg;
|
|
|
|
|
|
if (hs->left > 0)
|
|
|
- 80102ea: 685a ldr r2, [r3, #4]
|
|
|
+ 8010262: 685a ldr r2, [r3, #4]
|
|
|
send_data(pcb, hs);
|
|
|
- 80102ec: 4619 mov r1, r3
|
|
|
+ 8010264: 4619 mov r1, r3
|
|
|
static err_t http_sent(void *arg, struct tcp_pcb *pcb, u16_t len)
|
|
|
{
|
|
|
struct http_state *hs;
|
|
|
hs = arg;
|
|
|
|
|
|
if (hs->left > 0)
|
|
|
- 80102ee: b112 cbz r2, 80102f6 <http_sent+0x12>
|
|
|
+ 8010266: b112 cbz r2, 801026e <http_sent+0x12>
|
|
|
send_data(pcb, hs);
|
|
|
- 80102f0: f7ff fd1e bl 800fd30 <send_data>
|
|
|
- 80102f4: e00d b.n 8010312 <http_sent+0x2e>
|
|
|
+ 8010268: f7ff fd1e bl 800fca8 <send_data>
|
|
|
+ 801026c: e00d b.n 801028a <http_sent+0x2e>
|
|
|
else
|
|
|
{
|
|
|
close_conn(pcb, hs);
|
|
|
- 80102f6: f7ff fd3f bl 800fd78 <close_conn>
|
|
|
+ 801026e: f7ff fd3f bl 800fcf0 <close_conn>
|
|
|
|
|
|
if (htmlpage == UploadDonePage)
|
|
|
- 80102fa: 4b07 ldr r3, [pc, #28] ; (8010318 <http_sent+0x34>)
|
|
|
- 80102fc: 781b ldrb r3, [r3, #0]
|
|
|
- 80102fe: 2b02 cmp r3, #2
|
|
|
- 8010300: d102 bne.n 8010308 <http_sent+0x24>
|
|
|
+ 8010272: 4b07 ldr r3, [pc, #28] ; (8010290 <http_sent+0x34>)
|
|
|
+ 8010274: 781b ldrb r3, [r3, #0]
|
|
|
+ 8010276: 2b02 cmp r3, #2
|
|
|
+ 8010278: d102 bne.n 8010280 <http_sent+0x24>
|
|
|
fDoneReset = 1;
|
|
|
- 8010302: 2201 movs r2, #1
|
|
|
- 8010304: 4b05 ldr r3, [pc, #20] ; (801031c <http_sent+0x38>)
|
|
|
- 8010306: e003 b.n 8010310 <http_sent+0x2c>
|
|
|
+ 801027a: 2201 movs r2, #1
|
|
|
+ 801027c: 4b05 ldr r3, [pc, #20] ; (8010294 <http_sent+0x38>)
|
|
|
+ 801027e: e003 b.n 8010288 <http_sent+0x2c>
|
|
|
else if (htmlpage == UploadErrorPage)
|
|
|
- 8010308: 2b03 cmp r3, #3
|
|
|
- 801030a: d102 bne.n 8010312 <http_sent+0x2e>
|
|
|
+ 8010280: 2b03 cmp r3, #3
|
|
|
+ 8010282: d102 bne.n 801028a <http_sent+0x2e>
|
|
|
fErrorReset = 1;
|
|
|
- 801030c: 4b04 ldr r3, [pc, #16] ; (8010320 <http_sent+0x3c>)
|
|
|
- 801030e: 2201 movs r2, #1
|
|
|
- 8010310: 701a strb r2, [r3, #0]
|
|
|
+ 8010284: 4b04 ldr r3, [pc, #16] ; (8010298 <http_sent+0x3c>)
|
|
|
+ 8010286: 2201 movs r2, #1
|
|
|
+ 8010288: 701a strb r2, [r3, #0]
|
|
|
}
|
|
|
return ERR_OK;
|
|
|
}
|
|
|
- 8010312: 2000 movs r0, #0
|
|
|
- 8010314: bd08 pop {r3, pc}
|
|
|
- 8010316: bf00 nop
|
|
|
- 8010318: 2000869c .word 0x2000869c
|
|
|
- 801031c: 20006dbc .word 0x20006dbc
|
|
|
- 8010320: 20006dbb .word 0x20006dbb
|
|
|
-
|
|
|
-08010324 <IAP_httpd_init>:
|
|
|
+ 801028a: 2000 movs r0, #0
|
|
|
+ 801028c: bd08 pop {r3, pc}
|
|
|
+ 801028e: bf00 nop
|
|
|
+ 8010290: 200084d8 .word 0x200084d8
|
|
|
+ 8010294: 20006dbc .word 0x20006dbc
|
|
|
+ 8010298: 20006db8 .word 0x20006db8
|
|
|
+
|
|
|
+0801029c <IAP_httpd_init>:
|
|
|
* @brief intialize HTTP webserver
|
|
|
* @param none
|
|
|
* @retval none
|
|
|
*/
|
|
|
void IAP_httpd_init(void)
|
|
|
{
|
|
|
- 8010324: b510 push {r4, lr}
|
|
|
+ 801029c: b510 push {r4, lr}
|
|
|
struct tcp_pcb *pcb;
|
|
|
/*create new pcb*/
|
|
|
pcb = tcp_new();
|
|
|
- 8010326: f7fb fe47 bl 800bfb8 <tcp_new>
|
|
|
+ 801029e: f7fb fe8b bl 800bfb8 <tcp_new>
|
|
|
/* bind HTTP traffic to pcb */
|
|
|
tcp_bind(pcb, IP_ADDR_ANY, 80);
|
|
|
- 801032a: 2250 movs r2, #80 ; 0x50
|
|
|
+ 80102a2: 2250 movs r2, #80 ; 0x50
|
|
|
*/
|
|
|
void IAP_httpd_init(void)
|
|
|
{
|
|
|
struct tcp_pcb *pcb;
|
|
|
/*create new pcb*/
|
|
|
pcb = tcp_new();
|
|
|
- 801032c: 4604 mov r4, r0
|
|
|
+ 80102a4: 4604 mov r4, r0
|
|
|
/* bind HTTP traffic to pcb */
|
|
|
tcp_bind(pcb, IP_ADDR_ANY, 80);
|
|
|
- 801032e: 4906 ldr r1, [pc, #24] ; (8010348 <IAP_httpd_init+0x24>)
|
|
|
- 8010330: f7fb fab6 bl 800b8a0 <tcp_bind>
|
|
|
+ 80102a6: 4906 ldr r1, [pc, #24] ; (80102c0 <IAP_httpd_init+0x24>)
|
|
|
+ 80102a8: f7fb fafa bl 800b8a0 <tcp_bind>
|
|
|
/* start listening on port 80 */
|
|
|
pcb = tcp_listen(pcb);
|
|
|
- 8010334: 21ff movs r1, #255 ; 0xff
|
|
|
- 8010336: 4620 mov r0, r4
|
|
|
- 8010338: f7fb faea bl 800b910 <tcp_listen_with_backlog>
|
|
|
+ 80102ac: 21ff movs r1, #255 ; 0xff
|
|
|
+ 80102ae: 4620 mov r0, r4
|
|
|
+ 80102b0: f7fb fb2e bl 800b910 <tcp_listen_with_backlog>
|
|
|
/* define callback function for TCP connection setup */
|
|
|
tcp_accept(pcb, http_accept);
|
|
|
- 801033c: 4903 ldr r1, [pc, #12] ; (801034c <IAP_httpd_init+0x28>)
|
|
|
+ 80102b4: 4903 ldr r1, [pc, #12] ; (80102c4 <IAP_httpd_init+0x28>)
|
|
|
}
|
|
|
- 801033e: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
+ 80102b6: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
|
/* bind HTTP traffic to pcb */
|
|
|
tcp_bind(pcb, IP_ADDR_ANY, 80);
|
|
|
/* start listening on port 80 */
|
|
|
pcb = tcp_listen(pcb);
|
|
|
/* define callback function for TCP connection setup */
|
|
|
tcp_accept(pcb, http_accept);
|
|
|
- 8010342: f7fb bb8a b.w 800ba5a <tcp_accept>
|
|
|
- 8010346: bf00 nop
|
|
|
- 8010348: 08011880 .word 0x08011880
|
|
|
- 801034c: 0800fce5 .word 0x0800fce5
|
|
|
+ 80102ba: f7fb bbce b.w 800ba5a <tcp_accept>
|
|
|
+ 80102be: bf00 nop
|
|
|
+ 80102c0: 080117f8 .word 0x080117f8
|
|
|
+ 80102c4: 0800fc5d .word 0x0800fc5d
|
|
|
|
|
|
-08010350 <LwIP_Init>:
|
|
|
+080102c8 <LwIP_Init>:
|
|
|
* @brief Initializes the lwIP stack
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_Init(void)
|
|
|
{
|
|
|
- 8010350: b510 push {r4, lr}
|
|
|
+ 80102c8: b510 push {r4, lr}
|
|
|
// mem_init();
|
|
|
//
|
|
|
// /* Initializes the memory pools defined by MEMP_NUM_x.*/
|
|
|
// memp_init();
|
|
|
|
|
|
if (sSettings.sWebParams.dhcpEnable)
|
|
|
- 8010352: 4c1a ldr r4, [pc, #104] ; (80103bc <LwIP_Init+0x6c>)
|
|
|
+ 80102ca: 4c1a ldr r4, [pc, #104] ; (8010334 <LwIP_Init+0x6c>)
|
|
|
* @brief Initializes the lwIP stack
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_Init(void)
|
|
|
{
|
|
|
- 8010354: b08c sub sp, #48 ; 0x30
|
|
|
+ 80102cc: b08c sub sp, #48 ; 0x30
|
|
|
struct ip_addr ipaddr;
|
|
|
struct ip_addr netmask;
|
|
|
struct ip_addr gw;
|
|
|
char str[20];
|
|
|
|
|
|
lwip_init();
|
|
|
- 8010356: f7fa fddf bl 800af18 <lwip_init>
|
|
|
+ 80102ce: f7fa fe23 bl 800af18 <lwip_init>
|
|
|
// mem_init();
|
|
|
//
|
|
|
// /* Initializes the memory pools defined by MEMP_NUM_x.*/
|
|
|
// memp_init();
|
|
|
|
|
|
if (sSettings.sWebParams.dhcpEnable)
|
|
|
- 801035a: f894 302f ldrb.w r3, [r4, #47] ; 0x2f
|
|
|
- 801035e: b123 cbz r3, 801036a <LwIP_Init+0x1a>
|
|
|
+ 80102d2: f894 3032 ldrb.w r3, [r4, #50] ; 0x32
|
|
|
+ 80102d6: b123 cbz r3, 80102e2 <LwIP_Init+0x1a>
|
|
|
{
|
|
|
ipaddr.addr = 0;
|
|
|
- 8010360: 2300 movs r3, #0
|
|
|
- 8010362: 9304 str r3, [sp, #16]
|
|
|
+ 80102d8: 2300 movs r3, #0
|
|
|
+ 80102da: 9304 str r3, [sp, #16]
|
|
|
netmask.addr = 0;
|
|
|
- 8010364: 9305 str r3, [sp, #20]
|
|
|
+ 80102dc: 9305 str r3, [sp, #20]
|
|
|
gw.addr = 0;
|
|
|
- 8010366: 9306 str r3, [sp, #24]
|
|
|
- 8010368: e013 b.n 8010392 <LwIP_Init+0x42>
|
|
|
+ 80102de: 9306 str r3, [sp, #24]
|
|
|
+ 80102e0: e013 b.n 801030a <LwIP_Init+0x42>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
sprintf(str, " %s\n\r", sSettings.sWebTempParams.ip);
|
|
|
- 801036a: 4915 ldr r1, [pc, #84] ; (80103c0 <LwIP_Init+0x70>)
|
|
|
- 801036c: f104 0230 add.w r2, r4, #48 ; 0x30
|
|
|
- 8010370: a807 add r0, sp, #28
|
|
|
- 8010372: f001 f9a5 bl 80116c0 <tfp_sprintf>
|
|
|
+ 80102e2: 4915 ldr r1, [pc, #84] ; (8010338 <LwIP_Init+0x70>)
|
|
|
+ 80102e4: f104 0233 add.w r2, r4, #51 ; 0x33
|
|
|
+ 80102e8: a807 add r0, sp, #28
|
|
|
+ 80102ea: f001 f9a5 bl 8011638 <tfp_sprintf>
|
|
|
PRINT_USART("\n\rStatic IP address \n\r");
|
|
|
PRINT_USART(str);
|
|
|
|
|
|
ipaddr.addr = ipaddr_addr(sSettings.sWebParams.ip);
|
|
|
- 8010376: 1ca0 adds r0, r4, #2
|
|
|
- 8010378: f7fe f89a bl 800e4b0 <ipaddr_addr>
|
|
|
- 801037c: 9004 str r0, [sp, #16]
|
|
|
+ 80102ee: 1ca0 adds r0, r4, #2
|
|
|
+ 80102f0: f7fe f8de bl 800e4b0 <ipaddr_addr>
|
|
|
+ 80102f4: 9004 str r0, [sp, #16]
|
|
|
netmask.addr = ipaddr_addr(sSettings.sWebParams.mask);
|
|
|
- 801037e: f104 0020 add.w r0, r4, #32
|
|
|
- 8010382: f7fe f895 bl 800e4b0 <ipaddr_addr>
|
|
|
- 8010386: 9005 str r0, [sp, #20]
|
|
|
+ 80102f6: f104 0022 add.w r0, r4, #34 ; 0x22
|
|
|
+ 80102fa: f7fe f8d9 bl 800e4b0 <ipaddr_addr>
|
|
|
+ 80102fe: 9005 str r0, [sp, #20]
|
|
|
gw.addr = ipaddr_addr(sSettings.sWebParams.gate);
|
|
|
- 8010388: f104 0011 add.w r0, r4, #17
|
|
|
- 801038c: f7fe f890 bl 800e4b0 <ipaddr_addr>
|
|
|
- 8010390: 9006 str r0, [sp, #24]
|
|
|
+ 8010300: f104 0012 add.w r0, r4, #18
|
|
|
+ 8010304: f7fe f8d4 bl 800e4b0 <ipaddr_addr>
|
|
|
+ 8010308: 9006 str r0, [sp, #24]
|
|
|
}
|
|
|
|
|
|
netif_add(&netif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input);
|
|
|
- 8010392: 2300 movs r3, #0
|
|
|
- 8010394: 9300 str r3, [sp, #0]
|
|
|
- 8010396: 4b0b ldr r3, [pc, #44] ; (80103c4 <LwIP_Init+0x74>)
|
|
|
- 8010398: 480b ldr r0, [pc, #44] ; (80103c8 <LwIP_Init+0x78>)
|
|
|
- 801039a: 9301 str r3, [sp, #4]
|
|
|
- 801039c: 4b0b ldr r3, [pc, #44] ; (80103cc <LwIP_Init+0x7c>)
|
|
|
- 801039e: a904 add r1, sp, #16
|
|
|
- 80103a0: 9302 str r3, [sp, #8]
|
|
|
- 80103a2: aa05 add r2, sp, #20
|
|
|
- 80103a4: ab06 add r3, sp, #24
|
|
|
- 80103a6: f7fa ffe7 bl 800b378 <netif_add>
|
|
|
+ 801030a: 2300 movs r3, #0
|
|
|
+ 801030c: 9300 str r3, [sp, #0]
|
|
|
+ 801030e: 4b0b ldr r3, [pc, #44] ; (801033c <LwIP_Init+0x74>)
|
|
|
+ 8010310: 480b ldr r0, [pc, #44] ; (8010340 <LwIP_Init+0x78>)
|
|
|
+ 8010312: 9301 str r3, [sp, #4]
|
|
|
+ 8010314: 4b0b ldr r3, [pc, #44] ; (8010344 <LwIP_Init+0x7c>)
|
|
|
+ 8010316: a904 add r1, sp, #16
|
|
|
+ 8010318: 9302 str r3, [sp, #8]
|
|
|
+ 801031a: aa05 add r2, sp, #20
|
|
|
+ 801031c: ab06 add r3, sp, #24
|
|
|
+ 801031e: f7fb f82b bl 800b378 <netif_add>
|
|
|
netif_set_default(&netif);
|
|
|
- 80103aa: 4807 ldr r0, [pc, #28] ; (80103c8 <LwIP_Init+0x78>)
|
|
|
- 80103ac: f7fb f812 bl 800b3d4 <netif_set_default>
|
|
|
+ 8010322: 4807 ldr r0, [pc, #28] ; (8010340 <LwIP_Init+0x78>)
|
|
|
+ 8010324: f7fb f856 bl 800b3d4 <netif_set_default>
|
|
|
netif_set_up(&netif);
|
|
|
- 80103b0: 4805 ldr r0, [pc, #20] ; (80103c8 <LwIP_Init+0x78>)
|
|
|
- 80103b2: f7fb f815 bl 800b3e0 <netif_set_up>
|
|
|
+ 8010328: 4805 ldr r0, [pc, #20] ; (8010340 <LwIP_Init+0x78>)
|
|
|
+ 801032a: f7fb f859 bl 800b3e0 <netif_set_up>
|
|
|
}
|
|
|
- 80103b6: b00c add sp, #48 ; 0x30
|
|
|
- 80103b8: bd10 pop {r4, pc}
|
|
|
- 80103ba: bf00 nop
|
|
|
- 80103bc: 2000838c .word 0x2000838c
|
|
|
- 80103c0: 080135e3 .word 0x080135e3
|
|
|
- 80103c4: 0800f549 .word 0x0800f549
|
|
|
- 80103c8: 20008c7c .word 0x20008c7c
|
|
|
- 80103cc: 0800f255 .word 0x0800f255
|
|
|
-
|
|
|
-080103d0 <LwIP_Pkt_Handle>:
|
|
|
+ 801032e: b00c add sp, #48 ; 0x30
|
|
|
+ 8010330: bd10 pop {r4, pc}
|
|
|
+ 8010332: bf00 nop
|
|
|
+ 8010334: 2000838c .word 0x2000838c
|
|
|
+ 8010338: 08013543 .word 0x08013543
|
|
|
+ 801033c: 0800f549 .word 0x0800f549
|
|
|
+ 8010340: 20008ab8 .word 0x20008ab8
|
|
|
+ 8010344: 0800f255 .word 0x0800f255
|
|
|
+
|
|
|
+08010348 <LwIP_Pkt_Handle>:
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_Pkt_Handle(void)
|
|
|
{
|
|
|
/* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */
|
|
|
ethernetif_input(&netif);
|
|
|
- 80103d0: 4801 ldr r0, [pc, #4] ; (80103d8 <LwIP_Pkt_Handle+0x8>)
|
|
|
- 80103d2: f7ff b86b b.w 800f4ac <ethernetif_input>
|
|
|
- 80103d6: bf00 nop
|
|
|
- 80103d8: 20008c7c .word 0x20008c7c
|
|
|
+ 8010348: 4801 ldr r0, [pc, #4] ; (8010350 <LwIP_Pkt_Handle+0x8>)
|
|
|
+ 801034a: f7ff b8af b.w 800f4ac <ethernetif_input>
|
|
|
+ 801034e: bf00 nop
|
|
|
+ 8010350: 20008ab8 .word 0x20008ab8
|
|
|
|
|
|
-080103dc <LwIP_DHCP_Process_Handle>:
|
|
|
+08010354 <LwIP_DHCP_Process_Handle>:
|
|
|
* @brief LwIP_DHCP_Process_Handle
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_DHCP_Process_Handle()
|
|
|
{
|
|
|
- 80103dc: b530 push {r4, r5, lr}
|
|
|
+ 8010354: b530 push {r4, r5, lr}
|
|
|
struct ip_addr ipaddr;
|
|
|
struct ip_addr netmask;
|
|
|
struct ip_addr gw;
|
|
|
|
|
|
switch (DHCP_state)
|
|
|
- 80103de: 4d1c ldr r5, [pc, #112] ; (8010450 <LwIP_DHCP_Process_Handle+0x74>)
|
|
|
- 80103e0: 782b ldrb r3, [r5, #0]
|
|
|
+ 8010356: 4d1c ldr r5, [pc, #112] ; (80103c8 <LwIP_DHCP_Process_Handle+0x74>)
|
|
|
+ 8010358: 782b ldrb r3, [r5, #0]
|
|
|
* @brief LwIP_DHCP_Process_Handle
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_DHCP_Process_Handle()
|
|
|
{
|
|
|
- 80103e2: b085 sub sp, #20
|
|
|
+ 801035a: b085 sub sp, #20
|
|
|
struct ip_addr ipaddr;
|
|
|
struct ip_addr netmask;
|
|
|
struct ip_addr gw;
|
|
|
|
|
|
switch (DHCP_state)
|
|
|
- 80103e4: b113 cbz r3, 80103ec <LwIP_DHCP_Process_Handle+0x10>
|
|
|
- 80103e6: 2b01 cmp r3, #1
|
|
|
- 80103e8: d12f bne.n 801044a <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
- 80103ea: e005 b.n 80103f8 <LwIP_DHCP_Process_Handle+0x1c>
|
|
|
+ 801035c: b113 cbz r3, 8010364 <LwIP_DHCP_Process_Handle+0x10>
|
|
|
+ 801035e: 2b01 cmp r3, #1
|
|
|
+ 8010360: d12f bne.n 80103c2 <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
+ 8010362: e005 b.n 8010370 <LwIP_DHCP_Process_Handle+0x1c>
|
|
|
{
|
|
|
case DHCP_START:
|
|
|
{
|
|
|
dhcp_start(&netif);
|
|
|
- 80103ec: 4819 ldr r0, [pc, #100] ; (8010454 <LwIP_DHCP_Process_Handle+0x78>)
|
|
|
- 80103ee: f7fa fd3f bl 800ae70 <dhcp_start>
|
|
|
+ 8010364: 4819 ldr r0, [pc, #100] ; (80103cc <LwIP_DHCP_Process_Handle+0x78>)
|
|
|
+ 8010366: f7fa fd83 bl 800ae70 <dhcp_start>
|
|
|
DHCP_state = DHCP_WAIT_ADDRESS;
|
|
|
- 80103f2: 2301 movs r3, #1
|
|
|
- 80103f4: 702b strb r3, [r5, #0]
|
|
|
+ 801036a: 2301 movs r3, #1
|
|
|
+ 801036c: 702b strb r3, [r5, #0]
|
|
|
PRINT_USART("\n\rLooking for DHCP server please wait...\n\r");
|
|
|
}
|
|
|
break;
|
|
|
- 80103f6: e028 b.n 801044a <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
+ 801036e: e028 b.n 80103c2 <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
|
|
|
case DHCP_WAIT_ADDRESS:
|
|
|
{
|
|
|
ipaddr = netif.ip_addr;
|
|
|
- 80103f8: 4c16 ldr r4, [pc, #88] ; (8010454 <LwIP_DHCP_Process_Handle+0x78>)
|
|
|
+ 8010370: 4c16 ldr r4, [pc, #88] ; (80103cc <LwIP_DHCP_Process_Handle+0x78>)
|
|
|
netmask = netif.netmask;
|
|
|
- 80103fa: 68a2 ldr r2, [r4, #8]
|
|
|
+ 8010372: 68a2 ldr r2, [r4, #8]
|
|
|
}
|
|
|
break;
|
|
|
|
|
|
case DHCP_WAIT_ADDRESS:
|
|
|
{
|
|
|
ipaddr = netif.ip_addr;
|
|
|
- 80103fc: 6863 ldr r3, [r4, #4]
|
|
|
+ 8010374: 6863 ldr r3, [r4, #4]
|
|
|
netmask = netif.netmask;
|
|
|
- 80103fe: 9202 str r2, [sp, #8]
|
|
|
+ 8010376: 9202 str r2, [sp, #8]
|
|
|
gw = netif.gw;
|
|
|
- 8010400: 68e2 ldr r2, [r4, #12]
|
|
|
+ 8010378: 68e2 ldr r2, [r4, #12]
|
|
|
}
|
|
|
break;
|
|
|
|
|
|
case DHCP_WAIT_ADDRESS:
|
|
|
{
|
|
|
ipaddr = netif.ip_addr;
|
|
|
- 8010402: 9301 str r3, [sp, #4]
|
|
|
+ 801037a: 9301 str r3, [sp, #4]
|
|
|
netmask = netif.netmask;
|
|
|
gw = netif.gw;
|
|
|
- 8010404: 9203 str r2, [sp, #12]
|
|
|
+ 801037c: 9203 str r2, [sp, #12]
|
|
|
|
|
|
if (ipaddr.addr != 0)
|
|
|
- 8010406: b12b cbz r3, 8010414 <LwIP_DHCP_Process_Handle+0x38>
|
|
|
+ 801037e: b12b cbz r3, 801038c <LwIP_DHCP_Process_Handle+0x38>
|
|
|
{
|
|
|
DHCP_state = DHCP_ADDRESS_ASSIGNED;
|
|
|
- 8010408: 2302 movs r3, #2
|
|
|
+ 8010380: 2302 movs r3, #2
|
|
|
|
|
|
/* Stop DHCP */
|
|
|
dhcp_stop(&netif);
|
|
|
- 801040a: 4620 mov r0, r4
|
|
|
+ 8010382: 4620 mov r0, r4
|
|
|
netmask = netif.netmask;
|
|
|
gw = netif.gw;
|
|
|
|
|
|
if (ipaddr.addr != 0)
|
|
|
{
|
|
|
DHCP_state = DHCP_ADDRESS_ASSIGNED;
|
|
|
- 801040c: 702b strb r3, [r5, #0]
|
|
|
+ 8010384: 702b strb r3, [r5, #0]
|
|
|
|
|
|
/* Stop DHCP */
|
|
|
dhcp_stop(&netif);
|
|
|
- 801040e: f7fa fd17 bl 800ae40 <dhcp_stop>
|
|
|
- 8010412: e01a b.n 801044a <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
+ 8010386: f7fa fd5b bl 800ae40 <dhcp_stop>
|
|
|
+ 801038a: e01a b.n 80103c2 <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
PRINT_USART(ipaddr_ntoa(&gw));
|
|
|
PRINT_USART("\n\r");
|
|
|
|
|
|
} else {
|
|
|
/* DHCP timeout */
|
|
|
if (netif.dhcp->tries > MAX_DHCP_TRIES)
|
|
|
- 8010414: 6a23 ldr r3, [r4, #32]
|
|
|
- 8010416: 7b5b ldrb r3, [r3, #13]
|
|
|
- 8010418: 2b04 cmp r3, #4
|
|
|
- 801041a: d916 bls.n 801044a <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
+ 801038c: 6a23 ldr r3, [r4, #32]
|
|
|
+ 801038e: 7b5b ldrb r3, [r3, #13]
|
|
|
+ 8010390: 2b04 cmp r3, #4
|
|
|
+ 8010392: d916 bls.n 80103c2 <LwIP_DHCP_Process_Handle+0x6e>
|
|
|
{
|
|
|
DHCP_state = DHCP_TIMEOUT;
|
|
|
- 801041c: 2303 movs r3, #3
|
|
|
+ 8010394: 2303 movs r3, #3
|
|
|
|
|
|
/* Stop DHCP */
|
|
|
dhcp_stop(&netif);
|
|
|
- 801041e: 4620 mov r0, r4
|
|
|
+ 8010396: 4620 mov r0, r4
|
|
|
|
|
|
} else {
|
|
|
/* DHCP timeout */
|
|
|
if (netif.dhcp->tries > MAX_DHCP_TRIES)
|
|
|
{
|
|
|
DHCP_state = DHCP_TIMEOUT;
|
|
|
- 8010420: 702b strb r3, [r5, #0]
|
|
|
+ 8010398: 702b strb r3, [r5, #0]
|
|
|
|
|
|
/* Stop DHCP */
|
|
|
dhcp_stop(&netif);
|
|
|
- 8010422: f7fa fd0d bl 800ae40 <dhcp_stop>
|
|
|
+ 801039a: f7fa fd51 bl 800ae40 <dhcp_stop>
|
|
|
|
|
|
// ipaddr.addr = ipaddr_addr(sSettings.sWebTempParams.ip);
|
|
|
// netmask.addr = ipaddr_addr(sSettings.sWebTempParams.mask);
|
|
|
// gw.addr = ipaddr_addr(sSettings.sWebTempParams.gate);
|
|
|
|
|
|
ipaddr.addr = ipaddr_addr("192.168.14.48");
|
|
|
- 8010426: 480c ldr r0, [pc, #48] ; (8010458 <LwIP_DHCP_Process_Handle+0x7c>)
|
|
|
- 8010428: f7fe f842 bl 800e4b0 <ipaddr_addr>
|
|
|
- 801042c: 9001 str r0, [sp, #4]
|
|
|
+ 801039e: 480c ldr r0, [pc, #48] ; (80103d0 <LwIP_DHCP_Process_Handle+0x7c>)
|
|
|
+ 80103a0: f7fe f886 bl 800e4b0 <ipaddr_addr>
|
|
|
+ 80103a4: 9001 str r0, [sp, #4]
|
|
|
netmask.addr = ipaddr_addr("255.255.255.0");
|
|
|
- 801042e: 480b ldr r0, [pc, #44] ; (801045c <LwIP_DHCP_Process_Handle+0x80>)
|
|
|
- 8010430: f7fe f83e bl 800e4b0 <ipaddr_addr>
|
|
|
- 8010434: 9002 str r0, [sp, #8]
|
|
|
+ 80103a6: 480b ldr r0, [pc, #44] ; (80103d4 <LwIP_DHCP_Process_Handle+0x80>)
|
|
|
+ 80103a8: f7fe f882 bl 800e4b0 <ipaddr_addr>
|
|
|
+ 80103ac: 9002 str r0, [sp, #8]
|
|
|
gw.addr = ipaddr_addr("192.168.14.1");
|
|
|
- 8010436: 480a ldr r0, [pc, #40] ; (8010460 <LwIP_DHCP_Process_Handle+0x84>)
|
|
|
- 8010438: f7fe f83a bl 800e4b0 <ipaddr_addr>
|
|
|
+ 80103ae: 480a ldr r0, [pc, #40] ; (80103d8 <LwIP_DHCP_Process_Handle+0x84>)
|
|
|
+ 80103b0: f7fe f87e bl 800e4b0 <ipaddr_addr>
|
|
|
|
|
|
netif_set_addr(&netif, &ipaddr , &netmask, &gw);
|
|
|
- 801043c: a901 add r1, sp, #4
|
|
|
+ 80103b4: a901 add r1, sp, #4
|
|
|
// netmask.addr = ipaddr_addr(sSettings.sWebTempParams.mask);
|
|
|
// gw.addr = ipaddr_addr(sSettings.sWebTempParams.gate);
|
|
|
|
|
|
ipaddr.addr = ipaddr_addr("192.168.14.48");
|
|
|
netmask.addr = ipaddr_addr("255.255.255.0");
|
|
|
gw.addr = ipaddr_addr("192.168.14.1");
|
|
|
- 801043e: 9003 str r0, [sp, #12]
|
|
|
+ 80103b6: 9003 str r0, [sp, #12]
|
|
|
|
|
|
netif_set_addr(&netif, &ipaddr , &netmask, &gw);
|
|
|
- 8010440: aa02 add r2, sp, #8
|
|
|
- 8010442: 4620 mov r0, r4
|
|
|
- 8010444: ab03 add r3, sp, #12
|
|
|
- 8010446: f7fa ff89 bl 800b35c <netif_set_addr>
|
|
|
+ 80103b8: aa02 add r2, sp, #8
|
|
|
+ 80103ba: 4620 mov r0, r4
|
|
|
+ 80103bc: ab03 add r3, sp, #12
|
|
|
+ 80103be: f7fa ffcd bl 800b35c <netif_set_addr>
|
|
|
}
|
|
|
}
|
|
|
break;
|
|
|
default: break;
|
|
|
}
|
|
|
}
|
|
|
- 801044a: b005 add sp, #20
|
|
|
- 801044c: bd30 pop {r4, r5, pc}
|
|
|
- 801044e: bf00 nop
|
|
|
- 8010450: 20006da8 .word 0x20006da8
|
|
|
- 8010454: 20008c7c .word 0x20008c7c
|
|
|
- 8010458: 08013624 .word 0x08013624
|
|
|
- 801045c: 080118a8 .word 0x080118a8
|
|
|
- 8010460: 08013632 .word 0x08013632
|
|
|
-
|
|
|
-08010464 <LwIP_Periodic_Handle>:
|
|
|
+ 80103c2: b005 add sp, #20
|
|
|
+ 80103c4: bd30 pop {r4, r5, pc}
|
|
|
+ 80103c6: bf00 nop
|
|
|
+ 80103c8: 20006da8 .word 0x20006da8
|
|
|
+ 80103cc: 20008ab8 .word 0x20008ab8
|
|
|
+ 80103d0: 08013584 .word 0x08013584
|
|
|
+ 80103d4: 08011820 .word 0x08011820
|
|
|
+ 80103d8: 08013592 .word 0x08013592
|
|
|
+
|
|
|
+080103dc <LwIP_Periodic_Handle>:
|
|
|
* @brief LwIP periodic tasks
|
|
|
* @param localtime the current LocalTime value
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_Periodic_Handle(__IO uint32_t localtime)
|
|
|
{
|
|
|
- 8010464: b507 push {r0, r1, r2, lr}
|
|
|
+ 80103dc: b507 push {r0, r1, r2, lr}
|
|
|
if (sSettings.sWebParams.dhcpEnable)
|
|
|
- 8010466: 4b08 ldr r3, [pc, #32] ; (8010488 <LwIP_Periodic_Handle+0x24>)
|
|
|
+ 80103de: 4b08 ldr r3, [pc, #32] ; (8010400 <LwIP_Periodic_Handle+0x24>)
|
|
|
* @brief LwIP periodic tasks
|
|
|
* @param localtime the current LocalTime value
|
|
|
* @retval None
|
|
|
*/
|
|
|
void LwIP_Periodic_Handle(__IO uint32_t localtime)
|
|
|
{
|
|
|
- 8010468: 9001 str r0, [sp, #4]
|
|
|
+ 80103e0: 9001 str r0, [sp, #4]
|
|
|
if (sSettings.sWebParams.dhcpEnable)
|
|
|
- 801046a: f893 302f ldrb.w r3, [r3, #47] ; 0x2f
|
|
|
- 801046e: b133 cbz r3, 801047e <LwIP_Periodic_Handle+0x1a>
|
|
|
+ 80103e2: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
|
|
|
+ 80103e6: b133 cbz r3, 80103f6 <LwIP_Periodic_Handle+0x1a>
|
|
|
{
|
|
|
/* Fine DHCP periodic process every 500ms */
|
|
|
|
|
|
if ((DHCP_state != DHCP_ADDRESS_ASSIGNED)&&(DHCP_state != DHCP_TIMEOUT)) {
|
|
|
- 8010470: 4b06 ldr r3, [pc, #24] ; (801048c <LwIP_Periodic_Handle+0x28>)
|
|
|
- 8010472: 781b ldrb r3, [r3, #0]
|
|
|
- 8010474: 3b02 subs r3, #2
|
|
|
- 8010476: 2b01 cmp r3, #1
|
|
|
- 8010478: d901 bls.n 801047e <LwIP_Periodic_Handle+0x1a>
|
|
|
+ 80103e8: 4b06 ldr r3, [pc, #24] ; (8010404 <LwIP_Periodic_Handle+0x28>)
|
|
|
+ 80103ea: 781b ldrb r3, [r3, #0]
|
|
|
+ 80103ec: 3b02 subs r3, #2
|
|
|
+ 80103ee: 2b01 cmp r3, #1
|
|
|
+ 80103f0: d901 bls.n 80103f6 <LwIP_Periodic_Handle+0x1a>
|
|
|
/* process DHCP state machine */
|
|
|
LwIP_DHCP_Process_Handle();
|
|
|
- 801047a: f7ff ffaf bl 80103dc <LwIP_DHCP_Process_Handle>
|
|
|
+ 80103f2: f7ff ffaf bl 8010354 <LwIP_DHCP_Process_Handle>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
sys_check_timeouts();
|
|
|
}
|
|
|
- 801047e: b003 add sp, #12
|
|
|
- 8010480: f85d eb04 ldr.w lr, [sp], #4
|
|
|
+ 80103f6: b003 add sp, #12
|
|
|
+ 80103f8: f85d eb04 ldr.w lr, [sp], #4
|
|
|
/* process DHCP state machine */
|
|
|
LwIP_DHCP_Process_Handle();
|
|
|
}
|
|
|
}
|
|
|
|
|
|
sys_check_timeouts();
|
|
|
- 8010484: f7fd bc0e b.w 800dca4 <sys_check_timeouts>
|
|
|
- 8010488: 2000838c .word 0x2000838c
|
|
|
- 801048c: 20006da8 .word 0x20006da8
|
|
|
+ 80103fc: f7fd bc52 b.w 800dca4 <sys_check_timeouts>
|
|
|
+ 8010400: 2000838c .word 0x2000838c
|
|
|
+ 8010404: 20006da8 .word 0x20006da8
|
|
|
|
|
|
-08010490 <ETH_BSP_Config>:
|
|
|
+08010408 <ETH_BSP_Config>:
|
|
|
* @brief ETH_BSP_Config
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_BSP_Config(void)
|
|
|
{
|
|
|
- 8010490: b570 push {r4, r5, r6, lr}
|
|
|
+ 8010408: b570 push {r4, r5, r6, lr}
|
|
|
{
|
|
|
volatile uint32_t i;
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
|
|
|
/* Enable GPIOs clocks */
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB
|
|
|
- 8010492: 2007 movs r0, #7
|
|
|
+ 801040a: 2007 movs r0, #7
|
|
|
* @brief ETH_BSP_Config
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_BSP_Config(void)
|
|
|
{
|
|
|
- 8010494: b0b2 sub sp, #200 ; 0xc8
|
|
|
+ 801040c: b0b2 sub sp, #200 ; 0xc8
|
|
|
{
|
|
|
volatile uint32_t i;
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
|
|
|
/* Enable GPIOs clocks */
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB
|
|
|
- 8010496: 2101 movs r1, #1
|
|
|
- 8010498: f7f9 fd7c bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
+ 801040e: 2101 movs r1, #1
|
|
|
+ 8010410: f7f9 fdc0 bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
| RCC_AHB1Periph_GPIOC, ENABLE);
|
|
|
|
|
|
/* Enable SYSCFG clock */
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
|
|
- 801049c: 2101 movs r1, #1
|
|
|
- 801049e: f44f 4080 mov.w r0, #16384 ; 0x4000
|
|
|
- 80104a2: f7f9 fd8f bl 8009fc4 <RCC_APB2PeriphClockCmd>
|
|
|
+ 8010414: 2101 movs r1, #1
|
|
|
+ 8010416: f44f 4080 mov.w r0, #16384 ; 0x4000
|
|
|
+ 801041a: f7f9 fdd3 bl 8009fc4 <RCC_APB2PeriphClockCmd>
|
|
|
|
|
|
/* MII/RMII Media interface selection --------------------------------------*/
|
|
|
SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
|
|
|
- 80104a6: 2001 movs r0, #1
|
|
|
- 80104a8: f7f9 fdc4 bl 800a034 <SYSCFG_ETH_MediaInterfaceConfig>
|
|
|
+ 801041e: 2001 movs r0, #1
|
|
|
+ 8010420: f7f9 fe08 bl 800a034 <SYSCFG_ETH_MediaInterfaceConfig>
|
|
|
ETH_RST_PIN -------> PE2 - замена на PE13
|
|
|
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
- 80104ac: 2386 movs r3, #134 ; 0x86
|
|
|
+ 8010424: 2386 movs r3, #134 ; 0x86
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 80104ae: 2400 movs r4, #0
|
|
|
+ 8010426: 2400 movs r4, #0
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
- 80104b0: 2502 movs r5, #2
|
|
|
+ 8010428: 2502 movs r5, #2
|
|
|
ETH_RST_PIN -------> PE2 - замена на PE13
|
|
|
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
- 80104b2: 9301 str r3, [sp, #4]
|
|
|
+ 801042a: 9301 str r3, [sp, #4]
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
|
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
|
|
- 80104b4: 485c ldr r0, [pc, #368] ; (8010628 <ETH_BSP_Config+0x198>)
|
|
|
+ 801042c: 485c ldr r0, [pc, #368] ; (80105a0 <ETH_BSP_Config+0x198>)
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
- 80104b6: f88d 5008 strb.w r5, [sp, #8]
|
|
|
+ 801042e: f88d 5008 strb.w r5, [sp, #8]
|
|
|
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
- 80104ba: 2303 movs r3, #3
|
|
|
+ 8010432: 2303 movs r3, #3
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
|
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
|
|
- 80104bc: a901 add r1, sp, #4
|
|
|
+ 8010434: a901 add r1, sp, #4
|
|
|
|
|
|
*/
|
|
|
|
|
|
/* Configure PA1,PA2 and PA7 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
|
|
- 80104be: f88d 3009 strb.w r3, [sp, #9]
|
|
|
+ 8010436: f88d 3009 strb.w r3, [sp, #9]
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 80104c2: f88d 400a strb.w r4, [sp, #10]
|
|
|
+ 801043a: f88d 400a strb.w r4, [sp, #10]
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
|
|
|
- 80104c6: f88d 400b strb.w r4, [sp, #11]
|
|
|
+ 801043e: f88d 400b strb.w r4, [sp, #11]
|
|
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
|
|
- 80104ca: f7f9 fcb1 bl 8009e30 <GPIO_Init>
|
|
|
+ 8010442: f7f9 fcf5 bl 8009e30 <GPIO_Init>
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
|
|
|
- 80104ce: 2101 movs r1, #1
|
|
|
- 80104d0: 220b movs r2, #11
|
|
|
- 80104d2: 4855 ldr r0, [pc, #340] ; (8010628 <ETH_BSP_Config+0x198>)
|
|
|
- 80104d4: f7f9 fcfb bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 8010446: 2101 movs r1, #1
|
|
|
+ 8010448: 220b movs r2, #11
|
|
|
+ 801044a: 4855 ldr r0, [pc, #340] ; (80105a0 <ETH_BSP_Config+0x198>)
|
|
|
+ 801044c: f7f9 fd3f bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
|
|
|
- 80104d8: 220b movs r2, #11
|
|
|
- 80104da: 4853 ldr r0, [pc, #332] ; (8010628 <ETH_BSP_Config+0x198>)
|
|
|
- 80104dc: 4629 mov r1, r5
|
|
|
- 80104de: f7f9 fcf6 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 8010450: 220b movs r2, #11
|
|
|
+ 8010452: 4853 ldr r0, [pc, #332] ; (80105a0 <ETH_BSP_Config+0x198>)
|
|
|
+ 8010454: 4629 mov r1, r5
|
|
|
+ 8010456: f7f9 fd3a bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
|
|
|
- 80104e2: 220b movs r2, #11
|
|
|
- 80104e4: 2107 movs r1, #7
|
|
|
- 80104e6: 4850 ldr r0, [pc, #320] ; (8010628 <ETH_BSP_Config+0x198>)
|
|
|
- 80104e8: f7f9 fcf1 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 801045a: 220b movs r2, #11
|
|
|
+ 801045c: 2107 movs r1, #7
|
|
|
+ 801045e: 4850 ldr r0, [pc, #320] ; (80105a0 <ETH_BSP_Config+0x198>)
|
|
|
+ 8010460: f7f9 fd35 bl 8009ece <GPIO_PinAFConfig>
|
|
|
|
|
|
/* Configure PB10,PB11,PB12 and PB13 */
|
|
|
GPIO_InitStructure.GPIO_Pin = /* GPIO_Pin_10 | */ GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
|
|
- 80104ec: f44f 5360 mov.w r3, #14336 ; 0x3800
|
|
|
+ 8010464: f44f 5360 mov.w r3, #14336 ; 0x3800
|
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
|
|
- 80104f0: 484e ldr r0, [pc, #312] ; (801062c <ETH_BSP_Config+0x19c>)
|
|
|
+ 8010468: 484e ldr r0, [pc, #312] ; (80105a4 <ETH_BSP_Config+0x19c>)
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
|
|
|
|
|
|
/* Configure PB10,PB11,PB12 and PB13 */
|
|
|
GPIO_InitStructure.GPIO_Pin = /* GPIO_Pin_10 | */ GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
|
|
|
- 80104f2: 9301 str r3, [sp, #4]
|
|
|
+ 801046a: 9301 str r3, [sp, #4]
|
|
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
|
|
- 80104f4: a901 add r1, sp, #4
|
|
|
- 80104f6: f7f9 fc9b bl 8009e30 <GPIO_Init>
|
|
|
+ 801046c: a901 add r1, sp, #4
|
|
|
+ 801046e: f7f9 fcdf bl 8009e30 <GPIO_Init>
|
|
|
//GPIO_PinAFConfig(GPIOB, GPIO_PinSource10, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
|
|
|
- 80104fa: 210b movs r1, #11
|
|
|
- 80104fc: 460a mov r2, r1
|
|
|
- 80104fe: 484b ldr r0, [pc, #300] ; (801062c <ETH_BSP_Config+0x19c>)
|
|
|
- 8010500: f7f9 fce5 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 8010472: 210b movs r1, #11
|
|
|
+ 8010474: 460a mov r2, r1
|
|
|
+ 8010476: 484b ldr r0, [pc, #300] ; (80105a4 <ETH_BSP_Config+0x19c>)
|
|
|
+ 8010478: f7f9 fd29 bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
|
|
|
- 8010504: 210c movs r1, #12
|
|
|
- 8010506: 220b movs r2, #11
|
|
|
- 8010508: 4848 ldr r0, [pc, #288] ; (801062c <ETH_BSP_Config+0x19c>)
|
|
|
- 801050a: f7f9 fce0 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 801047c: 210c movs r1, #12
|
|
|
+ 801047e: 220b movs r2, #11
|
|
|
+ 8010480: 4848 ldr r0, [pc, #288] ; (80105a4 <ETH_BSP_Config+0x19c>)
|
|
|
+ 8010482: f7f9 fd24 bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
|
|
|
- 801050e: 220b movs r2, #11
|
|
|
- 8010510: 210d movs r1, #13
|
|
|
- 8010512: 4846 ldr r0, [pc, #280] ; (801062c <ETH_BSP_Config+0x19c>)
|
|
|
- 8010514: f7f9 fcdb bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 8010486: 220b movs r2, #11
|
|
|
+ 8010488: 210d movs r1, #13
|
|
|
+ 801048a: 4846 ldr r0, [pc, #280] ; (80105a4 <ETH_BSP_Config+0x19c>)
|
|
|
+ 801048c: f7f9 fd1f bl 8009ece <GPIO_PinAFConfig>
|
|
|
|
|
|
/* Configure PC1, PC4 and PC5 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
|
|
|
- 8010518: 2332 movs r3, #50 ; 0x32
|
|
|
+ 8010490: 2332 movs r3, #50 ; 0x32
|
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
|
|
- 801051a: 4845 ldr r0, [pc, #276] ; (8010630 <ETH_BSP_Config+0x1a0>)
|
|
|
+ 8010492: 4845 ldr r0, [pc, #276] ; (80105a8 <ETH_BSP_Config+0x1a0>)
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
|
|
|
|
|
|
/* Configure PC1, PC4 and PC5 */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
|
|
|
- 801051c: 9301 str r3, [sp, #4]
|
|
|
+ 8010494: 9301 str r3, [sp, #4]
|
|
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
|
|
- 801051e: a901 add r1, sp, #4
|
|
|
- 8010520: f7f9 fc86 bl 8009e30 <GPIO_Init>
|
|
|
+ 8010496: a901 add r1, sp, #4
|
|
|
+ 8010498: f7f9 fcca bl 8009e30 <GPIO_Init>
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
|
|
|
- 8010524: 4842 ldr r0, [pc, #264] ; (8010630 <ETH_BSP_Config+0x1a0>)
|
|
|
- 8010526: 2101 movs r1, #1
|
|
|
- 8010528: 220b movs r2, #11
|
|
|
- 801052a: f7f9 fcd0 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 801049c: 4842 ldr r0, [pc, #264] ; (80105a8 <ETH_BSP_Config+0x1a0>)
|
|
|
+ 801049e: 2101 movs r1, #1
|
|
|
+ 80104a0: 220b movs r2, #11
|
|
|
+ 80104a2: f7f9 fd14 bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
|
|
|
- 801052e: 4840 ldr r0, [pc, #256] ; (8010630 <ETH_BSP_Config+0x1a0>)
|
|
|
- 8010530: 2104 movs r1, #4
|
|
|
- 8010532: 220b movs r2, #11
|
|
|
- 8010534: f7f9 fccb bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 80104a6: 4840 ldr r0, [pc, #256] ; (80105a8 <ETH_BSP_Config+0x1a0>)
|
|
|
+ 80104a8: 2104 movs r1, #4
|
|
|
+ 80104aa: 220b movs r2, #11
|
|
|
+ 80104ac: f7f9 fd0f bl 8009ece <GPIO_PinAFConfig>
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
|
|
|
- 8010538: 220b movs r2, #11
|
|
|
- 801053a: 483d ldr r0, [pc, #244] ; (8010630 <ETH_BSP_Config+0x1a0>)
|
|
|
- 801053c: 2105 movs r1, #5
|
|
|
- 801053e: f7f9 fcc6 bl 8009ece <GPIO_PinAFConfig>
|
|
|
+ 80104b0: 220b movs r2, #11
|
|
|
+ 80104b2: 483d ldr r0, [pc, #244] ; (80105a8 <ETH_BSP_Config+0x1a0>)
|
|
|
+ 80104b4: 2105 movs r1, #5
|
|
|
+ 80104b6: f7f9 fd0a bl 8009ece <GPIO_PinAFConfig>
|
|
|
|
|
|
/* Configure the PHY RST pin */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
|
|
- 8010542: f44f 5600 mov.w r6, #8192 ; 0x2000
|
|
|
+ 80104ba: f44f 5600 mov.w r6, #8192 ; 0x2000
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
- 8010546: 2301 movs r3, #1
|
|
|
+ 80104be: 2301 movs r3, #1
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
|
|
- 8010548: 483a ldr r0, [pc, #232] ; (8010634 <ETH_BSP_Config+0x1a4>)
|
|
|
+ 80104c0: 483a ldr r0, [pc, #232] ; (80105ac <ETH_BSP_Config+0x1a4>)
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
|
|
|
|
|
|
/* Configure the PHY RST pin */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
- 801054a: f88d 3008 strb.w r3, [sp, #8]
|
|
|
+ 80104c2: f88d 3008 strb.w r3, [sp, #8]
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
|
|
- 801054e: a901 add r1, sp, #4
|
|
|
+ 80104c6: a901 add r1, sp, #4
|
|
|
|
|
|
/* Configure the PHY RST pin */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
- 8010550: f88d 300b strb.w r3, [sp, #11]
|
|
|
+ 80104c8: f88d 300b strb.w r3, [sp, #11]
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
|
|
|
GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
|
|
|
|
|
|
/* Configure the PHY RST pin */
|
|
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
|
|
- 8010554: 9601 str r6, [sp, #4]
|
|
|
+ 80104cc: 9601 str r6, [sp, #4]
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
|
|
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
|
|
- 8010556: f88d 400a strb.w r4, [sp, #10]
|
|
|
+ 80104ce: f88d 400a strb.w r4, [sp, #10]
|
|
|
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
- 801055a: f88d 5009 strb.w r5, [sp, #9]
|
|
|
+ 80104d2: f88d 5009 strb.w r5, [sp, #9]
|
|
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
|
|
- 801055e: f7f9 fc67 bl 8009e30 <GPIO_Init>
|
|
|
+ 80104d6: f7f9 fcab bl 8009e30 <GPIO_Init>
|
|
|
|
|
|
GPIO_ResetBits(GPIOE, GPIO_Pin_13);
|
|
|
- 8010562: 4834 ldr r0, [pc, #208] ; (8010634 <ETH_BSP_Config+0x1a4>)
|
|
|
- 8010564: 4631 mov r1, r6
|
|
|
- 8010566: f7f9 fcb0 bl 8009eca <GPIO_ResetBits>
|
|
|
+ 80104da: 4834 ldr r0, [pc, #208] ; (80105ac <ETH_BSP_Config+0x1a4>)
|
|
|
+ 80104dc: 4631 mov r1, r6
|
|
|
+ 80104de: f7f9 fcf4 bl 8009eca <GPIO_ResetBits>
|
|
|
for (i = 0; i < 20000; i++);
|
|
|
- 801056a: 9400 str r4, [sp, #0]
|
|
|
- 801056c: f644 631f movw r3, #19999 ; 0x4e1f
|
|
|
- 8010570: e002 b.n 8010578 <ETH_BSP_Config+0xe8>
|
|
|
- 8010572: 9a00 ldr r2, [sp, #0]
|
|
|
- 8010574: 3201 adds r2, #1
|
|
|
- 8010576: 9200 str r2, [sp, #0]
|
|
|
- 8010578: 9a00 ldr r2, [sp, #0]
|
|
|
- 801057a: 429a cmp r2, r3
|
|
|
- 801057c: d9f9 bls.n 8010572 <ETH_BSP_Config+0xe2>
|
|
|
+ 80104e2: 9400 str r4, [sp, #0]
|
|
|
+ 80104e4: f644 631f movw r3, #19999 ; 0x4e1f
|
|
|
+ 80104e8: e002 b.n 80104f0 <ETH_BSP_Config+0xe8>
|
|
|
+ 80104ea: 9a00 ldr r2, [sp, #0]
|
|
|
+ 80104ec: 3201 adds r2, #1
|
|
|
+ 80104ee: 9200 str r2, [sp, #0]
|
|
|
+ 80104f0: 9a00 ldr r2, [sp, #0]
|
|
|
+ 80104f2: 429a cmp r2, r3
|
|
|
+ 80104f4: d9f9 bls.n 80104ea <ETH_BSP_Config+0xe2>
|
|
|
GPIO_SetBits(GPIOE, GPIO_Pin_13);
|
|
|
- 801057e: 482d ldr r0, [pc, #180] ; (8010634 <ETH_BSP_Config+0x1a4>)
|
|
|
- 8010580: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
|
- 8010584: f7f9 fc9f bl 8009ec6 <GPIO_SetBits>
|
|
|
+ 80104f6: 482d ldr r0, [pc, #180] ; (80105ac <ETH_BSP_Config+0x1a4>)
|
|
|
+ 80104f8: f44f 5100 mov.w r1, #8192 ; 0x2000
|
|
|
+ 80104fc: f7f9 fce3 bl 8009ec6 <GPIO_SetBits>
|
|
|
for (i = 0; i < 20000; i++);
|
|
|
- 8010588: 2300 movs r3, #0
|
|
|
- 801058a: 9300 str r3, [sp, #0]
|
|
|
- 801058c: f644 631f movw r3, #19999 ; 0x4e1f
|
|
|
- 8010590: e002 b.n 8010598 <ETH_BSP_Config+0x108>
|
|
|
- 8010592: 9a00 ldr r2, [sp, #0]
|
|
|
- 8010594: 3201 adds r2, #1
|
|
|
- 8010596: 9200 str r2, [sp, #0]
|
|
|
- 8010598: 9a00 ldr r2, [sp, #0]
|
|
|
- 801059a: 429a cmp r2, r3
|
|
|
- 801059c: d9f9 bls.n 8010592 <ETH_BSP_Config+0x102>
|
|
|
+ 8010500: 2300 movs r3, #0
|
|
|
+ 8010502: 9300 str r3, [sp, #0]
|
|
|
+ 8010504: f644 631f movw r3, #19999 ; 0x4e1f
|
|
|
+ 8010508: e002 b.n 8010510 <ETH_BSP_Config+0x108>
|
|
|
+ 801050a: 9a00 ldr r2, [sp, #0]
|
|
|
+ 801050c: 3201 adds r2, #1
|
|
|
+ 801050e: 9200 str r2, [sp, #0]
|
|
|
+ 8010510: 9a00 ldr r2, [sp, #0]
|
|
|
+ 8010512: 429a cmp r2, r3
|
|
|
+ 8010514: d9f9 bls.n 801050a <ETH_BSP_Config+0x102>
|
|
|
static void ETH_MACDMA_Config(void)
|
|
|
{
|
|
|
ETH_InitTypeDef ETH_InitStructure;
|
|
|
|
|
|
/* Enable ETHERNET clock */
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
|
|
|
- 801059e: f04f 6060 mov.w r0, #234881024 ; 0xe000000
|
|
|
- 80105a2: 2101 movs r1, #1
|
|
|
- 80105a4: f7f9 fcf6 bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
+ 8010516: f04f 6060 mov.w r0, #234881024 ; 0xe000000
|
|
|
+ 801051a: 2101 movs r1, #1
|
|
|
+ 801051c: f7f9 fd3a bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
|
|
|
|
|
|
/* Reset ETHERNET on AHB Bus */
|
|
|
ETH_DeInit();
|
|
|
- 80105a8: f000 f858 bl 801065c <ETH_DeInit>
|
|
|
+ 8010520: f000 f858 bl 80105d4 <ETH_DeInit>
|
|
|
|
|
|
/* Software reset */
|
|
|
ETH_SoftwareReset();
|
|
|
- 80105ac: f000 f9ec bl 8010988 <ETH_SoftwareReset>
|
|
|
+ 8010524: f000 f9ec bl 8010900 <ETH_SoftwareReset>
|
|
|
|
|
|
/* Wait for software reset */
|
|
|
while (ETH_GetSoftwareResetStatus() == SET);
|
|
|
- 80105b0: f000 f9f2 bl 8010998 <ETH_GetSoftwareResetStatus>
|
|
|
- 80105b4: 2801 cmp r0, #1
|
|
|
- 80105b6: d0fb beq.n 80105b0 <ETH_BSP_Config+0x120>
|
|
|
+ 8010528: f000 f9f2 bl 8010910 <ETH_GetSoftwareResetStatus>
|
|
|
+ 801052c: 2801 cmp r0, #1
|
|
|
+ 801052e: d0fb beq.n 8010528 <ETH_BSP_Config+0x120>
|
|
|
|
|
|
/* ETHERNET Configuration --------------------------------------------------*/
|
|
|
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
|
|
|
ETH_StructInit(Ð_InitStructure);
|
|
|
- 80105b8: a803 add r0, sp, #12
|
|
|
- 80105ba: f000 f85c bl 8010676 <ETH_StructInit>
|
|
|
+ 8010530: a803 add r0, sp, #12
|
|
|
+ 8010532: f000 f85c bl 80105ee <ETH_StructInit>
|
|
|
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
//ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
|
|
|
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
|
|
|
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
|
|
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
|
|
- 80105be: 2300 movs r3, #0
|
|
|
- 80105c0: 930a str r3, [sp, #40] ; 0x28
|
|
|
+ 8010536: 2300 movs r3, #0
|
|
|
+ 8010538: 930a str r3, [sp, #40] ; 0x28
|
|
|
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
|
|
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
|
|
- 80105c2: 930e str r3, [sp, #56] ; 0x38
|
|
|
+ 801053a: 930e str r3, [sp, #56] ; 0x38
|
|
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
|
|
- 80105c4: 9311 str r3, [sp, #68] ; 0x44
|
|
|
+ 801053c: 9311 str r3, [sp, #68] ; 0x44
|
|
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
|
|
- 80105c6: 9314 str r3, [sp, #80] ; 0x50
|
|
|
+ 801053e: 9314 str r3, [sp, #80] ; 0x50
|
|
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
|
|
- 80105c8: 9316 str r3, [sp, #88] ; 0x58
|
|
|
+ 8010540: 9316 str r3, [sp, #88] ; 0x58
|
|
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
|
|
- 80105ca: 9317 str r3, [sp, #92] ; 0x5c
|
|
|
+ 8010542: 9317 str r3, [sp, #92] ; 0x5c
|
|
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
|
|
- 80105cc: 9318 str r3, [sp, #96] ; 0x60
|
|
|
+ 8010544: 9318 str r3, [sp, #96] ; 0x60
|
|
|
/*------------------------ DMA -----------------------------------*/
|
|
|
|
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
|
|
- 80105ce: 9323 str r3, [sp, #140] ; 0x8c
|
|
|
+ 8010546: 9323 str r3, [sp, #140] ; 0x8c
|
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
|
|
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
|
|
|
- 80105d0: 9328 str r3, [sp, #160] ; 0xa0
|
|
|
+ 8010548: 9328 str r3, [sp, #160] ; 0xa0
|
|
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
|
|
- 80105d2: 9329 str r3, [sp, #164] ; 0xa4
|
|
|
+ 801054a: 9329 str r3, [sp, #164] ; 0xa4
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
- 80105d4: 2304 movs r3, #4
|
|
|
- 80105d6: 932b str r3, [sp, #172] ; 0xac
|
|
|
+ 801054c: 2304 movs r3, #4
|
|
|
+ 801054e: 932b str r3, [sp, #172] ; 0xac
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
- 80105d8: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
|
- 80105dc: 932d str r3, [sp, #180] ; 0xb4
|
|
|
+ 8010550: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
|
+ 8010554: 932d str r3, [sp, #180] ; 0xb4
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
- 80105de: f44f 0380 mov.w r3, #4194304 ; 0x400000
|
|
|
+ 8010556: f44f 0380 mov.w r3, #4194304 ; 0x400000
|
|
|
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
|
|
|
ETH_StructInit(Ð_InitStructure);
|
|
|
|
|
|
/* Fill ETH_InitStructure parametrs */
|
|
|
/*------------------------ MAC -----------------------------------*/
|
|
|
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
- 80105e2: 2401 movs r4, #1
|
|
|
+ 801055a: 2401 movs r4, #1
|
|
|
//ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
|
|
|
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
|
|
|
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
|
|
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
|
|
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
|
|
|
- 80105e4: f44f 7200 mov.w r2, #512 ; 0x200
|
|
|
+ 801055c: f44f 7200 mov.w r2, #512 ; 0x200
|
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
- 80105e8: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
|
+ 8010560: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
|
|
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
- 80105ec: 932e str r3, [sp, #184] ; 0xb8
|
|
|
+ 8010564: 932e str r3, [sp, #184] ; 0xb8
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
- 80105ee: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
|
+ 8010566: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
|
//ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
|
|
|
// ETH_InitStructure.ETH_Speed = ETH_Speed_10M;
|
|
|
// ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
|
|
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
|
|
ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
|
|
|
- 80105f2: 920d str r2, [sp, #52] ; 0x34
|
|
|
+ 801056a: 920d str r2, [sp, #52] ; 0x34
|
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
- 80105f4: 9126 str r1, [sp, #152] ; 0x98
|
|
|
+ 801056c: 9126 str r1, [sp, #152] ; 0x98
|
|
|
|
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
- 80105f6: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
|
+ 801056e: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
- 80105fa: 932f str r3, [sp, #188] ; 0xbc
|
|
|
+ 8010572: 932f str r3, [sp, #188] ; 0xbc
|
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
|
|
|
|
|
/* Configure Ethernet */
|
|
|
EthInitStatus = ETH_Init(Ð_InitStructure, LAN8720_PHY_ADDRESS);
|
|
|
- 80105fc: 4621 mov r1, r4
|
|
|
+ 8010574: 4621 mov r1, r4
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
|
|
- 80105fe: f44f 4380 mov.w r3, #16384 ; 0x4000
|
|
|
+ 8010576: f44f 4380 mov.w r3, #16384 ; 0x4000
|
|
|
|
|
|
/* Configure Ethernet */
|
|
|
EthInitStatus = ETH_Init(Ð_InitStructure, LAN8720_PHY_ADDRESS);
|
|
|
- 8010602: a803 add r0, sp, #12
|
|
|
+ 801057a: a803 add r0, sp, #12
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
|
|
- 8010604: 9331 str r3, [sp, #196] ; 0xc4
|
|
|
+ 801057c: 9331 str r3, [sp, #196] ; 0xc4
|
|
|
|
|
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
|
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
|
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
|
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
|
|
ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
- 8010606: 9224 str r2, [sp, #144] ; 0x90
|
|
|
+ 801057e: 9224 str r2, [sp, #144] ; 0x90
|
|
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
|
|
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
|
|
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
|
|
ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
|
|
|
ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
- 8010608: 922c str r2, [sp, #176] ; 0xb0
|
|
|
+ 8010580: 922c str r2, [sp, #176] ; 0xb0
|
|
|
/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
|
|
|
ETH_StructInit(Ð_InitStructure);
|
|
|
|
|
|
/* Fill ETH_InitStructure parametrs */
|
|
|
/*------------------------ MAC -----------------------------------*/
|
|
|
ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
- 801060a: 9403 str r4, [sp, #12]
|
|
|
+ 8010582: 9403 str r4, [sp, #12]
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
|
|
|
|
|
/* Configure Ethernet */
|
|
|
EthInitStatus = ETH_Init(Ð_InitStructure, LAN8720_PHY_ADDRESS);
|
|
|
- 801060c: f000 fa5e bl 8010acc <ETH_Init>
|
|
|
- 8010610: 4d09 ldr r5, [pc, #36] ; (8010638 <ETH_BSP_Config+0x1a8>)
|
|
|
+ 8010584: f000 fa5e bl 8010a44 <ETH_Init>
|
|
|
+ 8010588: 4d09 ldr r5, [pc, #36] ; (80105b0 <ETH_BSP_Config+0x1a8>)
|
|
|
|
|
|
/* Enable the Ethernet Rx Interrupt */
|
|
|
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
|
|
|
- 8010612: 4621 mov r1, r4
|
|
|
+ 801058a: 4621 mov r1, r4
|
|
|
ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
|
|
|
|
|
|
/* Configure Ethernet */
|
|
|
EthInitStatus = ETH_Init(Ð_InitStructure, LAN8720_PHY_ADDRESS);
|
|
|
- 8010614: 6028 str r0, [r5, #0]
|
|
|
+ 801058c: 6028 str r0, [r5, #0]
|
|
|
|
|
|
/* Enable the Ethernet Rx Interrupt */
|
|
|
ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
|
|
|
- 8010616: 4809 ldr r0, [pc, #36] ; (801063c <ETH_BSP_Config+0x1ac>)
|
|
|
- 8010618: f000 f9c6 bl 80109a8 <ETH_DMAITConfig>
|
|
|
+ 801058e: 4809 ldr r0, [pc, #36] ; (80105b4 <ETH_BSP_Config+0x1ac>)
|
|
|
+ 8010590: f000 f9c6 bl 8010920 <ETH_DMAITConfig>
|
|
|
//ETH_NVIC_Config();
|
|
|
|
|
|
/* Configure the Ethernet MAC/DMA */
|
|
|
ETH_MACDMA_Config();
|
|
|
|
|
|
if (EthInitStatus == 0) {
|
|
|
- 801061c: 682b ldr r3, [r5, #0]
|
|
|
- 801061e: b903 cbnz r3, 8010622 <ETH_BSP_Config+0x192>
|
|
|
- 8010620: e7fe b.n 8010620 <ETH_BSP_Config+0x190>
|
|
|
+ 8010594: 682b ldr r3, [r5, #0]
|
|
|
+ 8010596: b903 cbnz r3, 801059a <ETH_BSP_Config+0x192>
|
|
|
+ 8010598: e7fe b.n 8010598 <ETH_BSP_Config+0x190>
|
|
|
// LCD_DisplayStringLine(Line5, (uint8_t*)" Ethernet Init ");
|
|
|
// LCD_DisplayStringLine(Line6, (uint8_t*)" failed ");
|
|
|
// STM_EVAL_LEDOn(LED5);
|
|
|
while(1);
|
|
|
}
|
|
|
}
|
|
|
- 8010622: b032 add sp, #200 ; 0xc8
|
|
|
- 8010624: bd70 pop {r4, r5, r6, pc}
|
|
|
- 8010626: bf00 nop
|
|
|
- 8010628: 40020000 .word 0x40020000
|
|
|
- 801062c: 40020400 .word 0x40020400
|
|
|
- 8010630: 40020800 .word 0x40020800
|
|
|
- 8010634: 40021000 .word 0x40021000
|
|
|
- 8010638: 20006dac .word 0x20006dac
|
|
|
- 801063c: 00010040 .word 0x00010040
|
|
|
-
|
|
|
-08010640 <ETH_Delay>:
|
|
|
+ 801059a: b032 add sp, #200 ; 0xc8
|
|
|
+ 801059c: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 801059e: bf00 nop
|
|
|
+ 80105a0: 40020000 .word 0x40020000
|
|
|
+ 80105a4: 40020400 .word 0x40020400
|
|
|
+ 80105a8: 40020800 .word 0x40020800
|
|
|
+ 80105ac: 40021000 .word 0x40021000
|
|
|
+ 80105b0: 20006dac .word 0x20006dac
|
|
|
+ 80105b4: 00010040 .word 0x00010040
|
|
|
+
|
|
|
+080105b8 <ETH_Delay>:
|
|
|
* @brief Inserts a delay time.
|
|
|
* @param nCount: specifies the delay time length.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void ETH_Delay(__IO uint32_t nCount)
|
|
|
{
|
|
|
- 8010640: b084 sub sp, #16
|
|
|
+ 80105b8: b084 sub sp, #16
|
|
|
__IO uint32_t index = 0;
|
|
|
- 8010642: 2300 movs r3, #0
|
|
|
+ 80105ba: 2300 movs r3, #0
|
|
|
* @brief Inserts a delay time.
|
|
|
* @param nCount: specifies the delay time length.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void ETH_Delay(__IO uint32_t nCount)
|
|
|
{
|
|
|
- 8010644: 9001 str r0, [sp, #4]
|
|
|
+ 80105bc: 9001 str r0, [sp, #4]
|
|
|
__IO uint32_t index = 0;
|
|
|
- 8010646: 9303 str r3, [sp, #12]
|
|
|
+ 80105be: 9303 str r3, [sp, #12]
|
|
|
for(index = nCount; index != 0; index--)
|
|
|
- 8010648: 9b01 ldr r3, [sp, #4]
|
|
|
- 801064a: e001 b.n 8010650 <ETH_Delay+0x10>
|
|
|
- 801064c: 9b03 ldr r3, [sp, #12]
|
|
|
- 801064e: 3b01 subs r3, #1
|
|
|
- 8010650: 9303 str r3, [sp, #12]
|
|
|
- 8010652: 9b03 ldr r3, [sp, #12]
|
|
|
- 8010654: 2b00 cmp r3, #0
|
|
|
- 8010656: d1f9 bne.n 801064c <ETH_Delay+0xc>
|
|
|
+ 80105c0: 9b01 ldr r3, [sp, #4]
|
|
|
+ 80105c2: e001 b.n 80105c8 <ETH_Delay+0x10>
|
|
|
+ 80105c4: 9b03 ldr r3, [sp, #12]
|
|
|
+ 80105c6: 3b01 subs r3, #1
|
|
|
+ 80105c8: 9303 str r3, [sp, #12]
|
|
|
+ 80105ca: 9b03 ldr r3, [sp, #12]
|
|
|
+ 80105cc: 2b00 cmp r3, #0
|
|
|
+ 80105ce: d1f9 bne.n 80105c4 <ETH_Delay+0xc>
|
|
|
{
|
|
|
}
|
|
|
}
|
|
|
- 8010658: b004 add sp, #16
|
|
|
- 801065a: 4770 bx lr
|
|
|
+ 80105d0: b004 add sp, #16
|
|
|
+ 80105d2: 4770 bx lr
|
|
|
|
|
|
-0801065c <ETH_DeInit>:
|
|
|
+080105d4 <ETH_DeInit>:
|
|
|
* @brief Deinitializes the ETHERNET peripheral registers to their default reset values.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DeInit(void)
|
|
|
{
|
|
|
- 801065c: b508 push {r3, lr}
|
|
|
+ 80105d4: b508 push {r3, lr}
|
|
|
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
|
|
|
- 801065e: 2101 movs r1, #1
|
|
|
- 8010660: f04f 7000 mov.w r0, #33554432 ; 0x2000000
|
|
|
- 8010664: f7f9 fcba bl 8009fdc <RCC_AHB1PeriphResetCmd>
|
|
|
+ 80105d6: 2101 movs r1, #1
|
|
|
+ 80105d8: f04f 7000 mov.w r0, #33554432 ; 0x2000000
|
|
|
+ 80105dc: f7f9 fcfe bl 8009fdc <RCC_AHB1PeriphResetCmd>
|
|
|
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
|
|
|
- 8010668: f04f 7000 mov.w r0, #33554432 ; 0x2000000
|
|
|
- 801066c: 2100 movs r1, #0
|
|
|
+ 80105e0: f04f 7000 mov.w r0, #33554432 ; 0x2000000
|
|
|
+ 80105e4: 2100 movs r1, #0
|
|
|
}
|
|
|
- 801066e: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
+ 80105e6: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DeInit(void)
|
|
|
{
|
|
|
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
|
|
|
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
|
|
|
- 8010672: f7f9 bcb3 b.w 8009fdc <RCC_AHB1PeriphResetCmd>
|
|
|
+ 80105ea: f7f9 bcf7 b.w 8009fdc <RCC_AHB1PeriphResetCmd>
|
|
|
|
|
|
-08010676 <ETH_StructInit>:
|
|
|
+080105ee <ETH_StructInit>:
|
|
|
/* Ethernet interframe gap set to 96 bits */
|
|
|
ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
|
|
/* Carrier Sense Enabled in Half-Duplex mode */
|
|
|
ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
|
|
|
/* PHY speed configured to 100Mbit/s */
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
|
|
|
- 8010676: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
|
- 801067a: 6142 str r2, [r0, #20]
|
|
|
+ 80105ee: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
|
+ 80105f2: 6142 str r2, [r0, #20]
|
|
|
/* Receive own Frames in Half-Duplex mode enabled */
|
|
|
ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
|
|
|
/* MAC MII loopback disabled */
|
|
|
ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
|
|
/* Full-Duplex mode selected */
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
- 801067c: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
|
- 8010680: 6202 str r2, [r0, #32]
|
|
|
+ 80105f4: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
|
+ 80105f8: 6202 str r2, [r0, #32]
|
|
|
/* Receive all frames disabled */
|
|
|
ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
|
|
/* Source address filtering (on the optional MAC addresses) disabled */
|
|
|
ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
|
|
/* Do not forward control frames that do not pass the address filtering */
|
|
|
ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
|
|
- 8010682: 2240 movs r2, #64 ; 0x40
|
|
|
- 8010684: 6402 str r2, [r0, #64] ; 0x40
|
|
|
+ 80105fa: 2240 movs r2, #64 ; 0x40
|
|
|
+ 80105fc: 6402 str r2, [r0, #64] ; 0x40
|
|
|
/* Disable reception of Broadcast frames */
|
|
|
ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
|
|
|
- 8010686: 2220 movs r2, #32
|
|
|
- 8010688: 6442 str r2, [r0, #68] ; 0x44
|
|
|
+ 80105fe: 2220 movs r2, #32
|
|
|
+ 8010600: 6442 str r2, [r0, #68] ; 0x44
|
|
|
/* Initialize hash table high and low regs */
|
|
|
ETH_InitStruct->ETH_HashTableHigh = 0x0;
|
|
|
ETH_InitStruct->ETH_HashTableLow = 0x0;
|
|
|
/* Flow control config (flow control disabled)*/
|
|
|
ETH_InitStruct->ETH_PauseTime = 0x0;
|
|
|
ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
|
|
|
- 801068a: 2280 movs r2, #128 ; 0x80
|
|
|
+ 8010602: 2280 movs r2, #128 ; 0x80
|
|
|
{
|
|
|
/* ETH_InitStruct members default value */
|
|
|
/*------------------------ MAC Configuration ---------------------------*/
|
|
|
|
|
|
/* PHY Auto-negotiation enabled */
|
|
|
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
- 801068c: 2301 movs r3, #1
|
|
|
+ 8010604: 2301 movs r3, #1
|
|
|
/* Initialize hash table high and low regs */
|
|
|
ETH_InitStruct->ETH_HashTableHigh = 0x0;
|
|
|
ETH_InitStruct->ETH_HashTableLow = 0x0;
|
|
|
/* Flow control config (flow control disabled)*/
|
|
|
ETH_InitStruct->ETH_PauseTime = 0x0;
|
|
|
ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
|
|
|
- 801068e: 6642 str r2, [r0, #100] ; 0x64
|
|
|
+ 8010606: 6642 str r2, [r0, #100] ; 0x64
|
|
|
ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
|
|
|
|
|
|
/*---------------------- DMA Configuration -------------------------------*/
|
|
|
|
|
|
/* Drops frames with with TCP/IP checksum errors */
|
|
|
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
|
|
|
- 8010690: f04f 6280 mov.w r2, #67108864 ; 0x4000000
|
|
|
+ 8010608: f04f 6280 mov.w r2, #67108864 ; 0x4000000
|
|
|
{
|
|
|
/* ETH_InitStruct members default value */
|
|
|
/*------------------------ MAC Configuration ---------------------------*/
|
|
|
|
|
|
/* PHY Auto-negotiation enabled */
|
|
|
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
- 8010694: 6003 str r3, [r0, #0]
|
|
|
+ 801060c: 6003 str r3, [r0, #0]
|
|
|
ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
|
|
|
|
|
|
/*---------------------- DMA Configuration -------------------------------*/
|
|
|
|
|
|
/* Drops frames with with TCP/IP checksum errors */
|
|
|
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
|
|
|
- 8010696: f8c0 2080 str.w r2, [r0, #128] ; 0x80
|
|
|
+ 801060e: f8c0 2080 str.w r2, [r0, #128] ; 0x80
|
|
|
/*------------------------ MAC Configuration ---------------------------*/
|
|
|
|
|
|
/* PHY Auto-negotiation enabled */
|
|
|
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
/* MAC watchdog enabled: cuts-off long frame */
|
|
|
ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
|
|
|
- 801069a: 2300 movs r3, #0
|
|
|
+ 8010612: 2300 movs r3, #0
|
|
|
/*---------------------- DMA Configuration -------------------------------*/
|
|
|
|
|
|
/* Drops frames with with TCP/IP checksum errors */
|
|
|
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
|
|
|
/* Store and forward mode enabled for receive */
|
|
|
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
- 801069c: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
|
+ 8010614: f04f 7200 mov.w r2, #33554432 ; 0x2000000
|
|
|
/*------------------------ MAC Configuration ---------------------------*/
|
|
|
|
|
|
/* PHY Auto-negotiation enabled */
|
|
|
ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
|
|
|
/* MAC watchdog enabled: cuts-off long frame */
|
|
|
ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
|
|
|
- 80106a0: 6043 str r3, [r0, #4]
|
|
|
+ 8010618: 6043 str r3, [r0, #4]
|
|
|
/* MAC Jabber enabled in Half-duplex mode */
|
|
|
ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
|
|
|
- 80106a2: 6083 str r3, [r0, #8]
|
|
|
+ 801061a: 6083 str r3, [r0, #8]
|
|
|
/* Ethernet interframe gap set to 96 bits */
|
|
|
ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
|
|
- 80106a4: 60c3 str r3, [r0, #12]
|
|
|
+ 801061c: 60c3 str r3, [r0, #12]
|
|
|
/* Carrier Sense Enabled in Half-Duplex mode */
|
|
|
ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
|
|
|
- 80106a6: 6103 str r3, [r0, #16]
|
|
|
+ 801061e: 6103 str r3, [r0, #16]
|
|
|
/* PHY speed configured to 100Mbit/s */
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
|
|
|
/* Receive own Frames in Half-Duplex mode enabled */
|
|
|
ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
|
|
|
- 80106a8: 6183 str r3, [r0, #24]
|
|
|
+ 8010620: 6183 str r3, [r0, #24]
|
|
|
/* MAC MII loopback disabled */
|
|
|
ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
|
|
- 80106aa: 61c3 str r3, [r0, #28]
|
|
|
+ 8010622: 61c3 str r3, [r0, #28]
|
|
|
/* Full-Duplex mode selected */
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
/* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */
|
|
|
ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
|
|
|
- 80106ac: 6243 str r3, [r0, #36] ; 0x24
|
|
|
+ 8010624: 6243 str r3, [r0, #36] ; 0x24
|
|
|
/* Retry Transmission enabled for half-duplex mode */
|
|
|
ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
|
|
|
- 80106ae: 6283 str r3, [r0, #40] ; 0x28
|
|
|
+ 8010626: 6283 str r3, [r0, #40] ; 0x28
|
|
|
/* Automatic PAD/CRC strip disabled*/
|
|
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
|
|
- 80106b0: 62c3 str r3, [r0, #44] ; 0x2c
|
|
|
+ 8010628: 62c3 str r3, [r0, #44] ; 0x2c
|
|
|
/* half-duplex mode retransmission Backoff time_limit = 10 slot times*/
|
|
|
ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
|
|
|
- 80106b2: 6303 str r3, [r0, #48] ; 0x30
|
|
|
+ 801062a: 6303 str r3, [r0, #48] ; 0x30
|
|
|
/* half-duplex mode Deferral check disabled */
|
|
|
ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
|
|
|
- 80106b4: 6343 str r3, [r0, #52] ; 0x34
|
|
|
+ 801062c: 6343 str r3, [r0, #52] ; 0x34
|
|
|
/* Receive all frames disabled */
|
|
|
ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
|
|
- 80106b6: 6383 str r3, [r0, #56] ; 0x38
|
|
|
+ 801062e: 6383 str r3, [r0, #56] ; 0x38
|
|
|
/* Source address filtering (on the optional MAC addresses) disabled */
|
|
|
ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
|
|
- 80106b8: 63c3 str r3, [r0, #60] ; 0x3c
|
|
|
+ 8010630: 63c3 str r3, [r0, #60] ; 0x3c
|
|
|
/* Do not forward control frames that do not pass the address filtering */
|
|
|
ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
|
|
/* Disable reception of Broadcast frames */
|
|
|
ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
|
|
|
/* Normal Destination address filtering (not reverse addressing) */
|
|
|
ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
|
|
|
- 80106ba: 6483 str r3, [r0, #72] ; 0x48
|
|
|
+ 8010632: 6483 str r3, [r0, #72] ; 0x48
|
|
|
/* Promiscuous address filtering mode disabled */
|
|
|
ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
|
|
- 80106bc: 64c3 str r3, [r0, #76] ; 0x4c
|
|
|
+ 8010634: 64c3 str r3, [r0, #76] ; 0x4c
|
|
|
/* Perfect address filtering for multicast addresses */
|
|
|
ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
|
|
- 80106be: 6503 str r3, [r0, #80] ; 0x50
|
|
|
+ 8010636: 6503 str r3, [r0, #80] ; 0x50
|
|
|
/* Perfect address filtering for unicast addresses */
|
|
|
ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
|
|
- 80106c0: 6543 str r3, [r0, #84] ; 0x54
|
|
|
+ 8010638: 6543 str r3, [r0, #84] ; 0x54
|
|
|
/* Initialize hash table high and low regs */
|
|
|
ETH_InitStruct->ETH_HashTableHigh = 0x0;
|
|
|
- 80106c2: 6583 str r3, [r0, #88] ; 0x58
|
|
|
+ 801063a: 6583 str r3, [r0, #88] ; 0x58
|
|
|
ETH_InitStruct->ETH_HashTableLow = 0x0;
|
|
|
- 80106c4: 65c3 str r3, [r0, #92] ; 0x5c
|
|
|
+ 801063c: 65c3 str r3, [r0, #92] ; 0x5c
|
|
|
/* Flow control config (flow control disabled)*/
|
|
|
ETH_InitStruct->ETH_PauseTime = 0x0;
|
|
|
- 80106c6: 6603 str r3, [r0, #96] ; 0x60
|
|
|
+ 801063e: 6603 str r3, [r0, #96] ; 0x60
|
|
|
ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
|
|
|
ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
|
|
|
- 80106c8: 6683 str r3, [r0, #104] ; 0x68
|
|
|
+ 8010640: 6683 str r3, [r0, #104] ; 0x68
|
|
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
|
|
- 80106ca: 66c3 str r3, [r0, #108] ; 0x6c
|
|
|
+ 8010642: 66c3 str r3, [r0, #108] ; 0x6c
|
|
|
ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
|
|
- 80106cc: 6703 str r3, [r0, #112] ; 0x70
|
|
|
+ 8010644: 6703 str r3, [r0, #112] ; 0x70
|
|
|
ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
|
|
- 80106ce: 6743 str r3, [r0, #116] ; 0x74
|
|
|
+ 8010646: 6743 str r3, [r0, #116] ; 0x74
|
|
|
/* VLANtag config (VLAN field not checked) */
|
|
|
ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
|
|
|
- 80106d0: 6783 str r3, [r0, #120] ; 0x78
|
|
|
+ 8010648: 6783 str r3, [r0, #120] ; 0x78
|
|
|
ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
|
|
|
- 80106d2: 67c3 str r3, [r0, #124] ; 0x7c
|
|
|
+ 801064a: 67c3 str r3, [r0, #124] ; 0x7c
|
|
|
/*---------------------- DMA Configuration -------------------------------*/
|
|
|
|
|
|
/* Drops frames with with TCP/IP checksum errors */
|
|
|
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
|
|
|
/* Store and forward mode enabled for receive */
|
|
|
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
- 80106d4: f8c0 2084 str.w r2, [r0, #132] ; 0x84
|
|
|
+ 801064c: f8c0 2084 str.w r2, [r0, #132] ; 0x84
|
|
|
ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
|
|
|
/* Disable Operate on second frame (transmit a second frame to FIFO without
|
|
|
waiting status of previous frame*/
|
|
|
ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
|
|
|
/* DMA works on 32-bit aligned start source and destinations addresses */
|
|
|
ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
- 80106d8: f8c0 20a4 str.w r2, [r0, #164] ; 0xa4
|
|
|
+ 8010650: f8c0 20a4 str.w r2, [r0, #164] ; 0xa4
|
|
|
/* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
|
|
|
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
- 80106dc: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
|
- 80106e0: f8c0 20a8 str.w r2, [r0, #168] ; 0xa8
|
|
|
+ 8010654: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
|
+ 8010658: f8c0 20a8 str.w r2, [r0, #168] ; 0xa8
|
|
|
/* DMA transfer max burst length = 32 beats = 32 x 32bits */
|
|
|
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
- 80106e4: f44f 0280 mov.w r2, #4194304 ; 0x400000
|
|
|
+ 801065c: f44f 0280 mov.w r2, #4194304 ; 0x400000
|
|
|
/* Store and forward mode enabled for receive */
|
|
|
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
/* Flush received frame that created FIFO overflow */
|
|
|
ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
|
|
|
/* Store and forward mode enabled for transmit */
|
|
|
ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
- 80106e8: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
|
+ 8010660: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
|
/* DMA works on 32-bit aligned start source and destinations addresses */
|
|
|
ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
/* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
|
|
|
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
/* DMA transfer max burst length = 32 beats = 32 x 32bits */
|
|
|
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
- 80106ec: f8c0 20ac str.w r2, [r0, #172] ; 0xac
|
|
|
+ 8010664: f8c0 20ac str.w r2, [r0, #172] ; 0xac
|
|
|
ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
- 80106f0: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
|
+ 8010668: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
|
/* Drops frames with with TCP/IP checksum errors */
|
|
|
ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
|
|
|
/* Store and forward mode enabled for receive */
|
|
|
ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
|
|
|
/* Flush received frame that created FIFO overflow */
|
|
|
ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
|
|
|
- 80106f4: f8c0 3088 str.w r3, [r0, #136] ; 0x88
|
|
|
+ 801066c: f8c0 3088 str.w r3, [r0, #136] ; 0x88
|
|
|
/* Store and forward mode enabled for transmit */
|
|
|
ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
|
|
- 80106f8: f8c0 108c str.w r1, [r0, #140] ; 0x8c
|
|
|
+ 8010670: f8c0 108c str.w r1, [r0, #140] ; 0x8c
|
|
|
/* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */
|
|
|
ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
|
|
|
- 80106fc: f8c0 3090 str.w r3, [r0, #144] ; 0x90
|
|
|
+ 8010674: f8c0 3090 str.w r3, [r0, #144] ; 0x90
|
|
|
/* Disable forwarding frames with errors (short frames, CRC,...)*/
|
|
|
ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
|
|
|
- 8010700: f8c0 3094 str.w r3, [r0, #148] ; 0x94
|
|
|
+ 8010678: f8c0 3094 str.w r3, [r0, #148] ; 0x94
|
|
|
/* Disable undersized good frames */
|
|
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
|
|
|
- 8010704: f8c0 3098 str.w r3, [r0, #152] ; 0x98
|
|
|
+ 801067c: f8c0 3098 str.w r3, [r0, #152] ; 0x98
|
|
|
/* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */
|
|
|
ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
|
|
|
- 8010708: f8c0 309c str.w r3, [r0, #156] ; 0x9c
|
|
|
+ 8010680: f8c0 309c str.w r3, [r0, #156] ; 0x9c
|
|
|
/* Disable Operate on second frame (transmit a second frame to FIFO without
|
|
|
waiting status of previous frame*/
|
|
|
ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
|
|
|
- 801070c: f8c0 30a0 str.w r3, [r0, #160] ; 0xa0
|
|
|
+ 8010684: f8c0 30a0 str.w r3, [r0, #160] ; 0xa0
|
|
|
ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
|
|
|
/* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */
|
|
|
ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable;
|
|
|
/* DMA transfer max burst length = 32 beats = 32 x 32bits */
|
|
|
ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
|
|
|
ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
|
|
|
- 8010710: f8c0 20b0 str.w r2, [r0, #176] ; 0xb0
|
|
|
+ 8010688: f8c0 20b0 str.w r2, [r0, #176] ; 0xb0
|
|
|
/* DMA Ring mode skip length = 0 */
|
|
|
ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
|
|
|
- 8010714: f8c0 30b4 str.w r3, [r0, #180] ; 0xb4
|
|
|
+ 801068c: f8c0 30b4 str.w r3, [r0, #180] ; 0xb4
|
|
|
/* Equal priority (round-robin) between transmit and receive DMA engines */
|
|
|
ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
|
|
|
- 8010718: f8c0 30b8 str.w r3, [r0, #184] ; 0xb8
|
|
|
- 801071c: 4770 bx lr
|
|
|
- 801071e: 0000 movs r0, r0
|
|
|
+ 8010690: f8c0 30b8 str.w r3, [r0, #184] ; 0xb8
|
|
|
+ 8010694: 4770 bx lr
|
|
|
+ 8010696: 0000 movs r0, r0
|
|
|
|
|
|
-08010720 <ETH_MACTransmissionCmd>:
|
|
|
+08010698 <ETH_MACTransmissionCmd>:
|
|
|
* @param NewState: new state of the MAC transmission.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_MACTransmissionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
- 8010720: 4b04 ldr r3, [pc, #16] ; (8010734 <ETH_MACTransmissionCmd+0x14>)
|
|
|
+ 8010698: 4b04 ldr r3, [pc, #16] ; (80106ac <ETH_MACTransmissionCmd+0x14>)
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the MAC transmission */
|
|
|
ETH->MACCR |= ETH_MACCR_TE;
|
|
|
- 8010722: 681a ldr r2, [r3, #0]
|
|
|
+ 801069a: 681a ldr r2, [r3, #0]
|
|
|
void ETH_MACTransmissionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
- 8010724: b110 cbz r0, 801072c <ETH_MACTransmissionCmd+0xc>
|
|
|
+ 801069c: b110 cbz r0, 80106a4 <ETH_MACTransmissionCmd+0xc>
|
|
|
{
|
|
|
/* Enable the MAC transmission */
|
|
|
ETH->MACCR |= ETH_MACCR_TE;
|
|
|
- 8010726: f042 0208 orr.w r2, r2, #8
|
|
|
- 801072a: e001 b.n 8010730 <ETH_MACTransmissionCmd+0x10>
|
|
|
+ 801069e: f042 0208 orr.w r2, r2, #8
|
|
|
+ 80106a2: e001 b.n 80106a8 <ETH_MACTransmissionCmd+0x10>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the MAC transmission */
|
|
|
ETH->MACCR &= ~ETH_MACCR_TE;
|
|
|
- 801072c: f022 0208 bic.w r2, r2, #8
|
|
|
- 8010730: 601a str r2, [r3, #0]
|
|
|
- 8010732: 4770 bx lr
|
|
|
- 8010734: 40028000 .word 0x40028000
|
|
|
+ 80106a4: f022 0208 bic.w r2, r2, #8
|
|
|
+ 80106a8: 601a str r2, [r3, #0]
|
|
|
+ 80106aa: 4770 bx lr
|
|
|
+ 80106ac: 40028000 .word 0x40028000
|
|
|
|
|
|
-08010738 <ETH_MACReceptionCmd>:
|
|
|
+080106b0 <ETH_MACReceptionCmd>:
|
|
|
* @param NewState: new state of the MAC reception.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_MACReceptionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
- 8010738: 4b04 ldr r3, [pc, #16] ; (801074c <ETH_MACReceptionCmd+0x14>)
|
|
|
+ 80106b0: 4b04 ldr r3, [pc, #16] ; (80106c4 <ETH_MACReceptionCmd+0x14>)
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the MAC reception */
|
|
|
ETH->MACCR |= ETH_MACCR_RE;
|
|
|
- 801073a: 681a ldr r2, [r3, #0]
|
|
|
+ 80106b2: 681a ldr r2, [r3, #0]
|
|
|
void ETH_MACReceptionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
- 801073c: b110 cbz r0, 8010744 <ETH_MACReceptionCmd+0xc>
|
|
|
+ 80106b4: b110 cbz r0, 80106bc <ETH_MACReceptionCmd+0xc>
|
|
|
{
|
|
|
/* Enable the MAC reception */
|
|
|
ETH->MACCR |= ETH_MACCR_RE;
|
|
|
- 801073e: f042 0204 orr.w r2, r2, #4
|
|
|
- 8010742: e001 b.n 8010748 <ETH_MACReceptionCmd+0x10>
|
|
|
+ 80106b6: f042 0204 orr.w r2, r2, #4
|
|
|
+ 80106ba: e001 b.n 80106c0 <ETH_MACReceptionCmd+0x10>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the MAC reception */
|
|
|
ETH->MACCR &= ~ETH_MACCR_RE;
|
|
|
- 8010744: f022 0204 bic.w r2, r2, #4
|
|
|
- 8010748: 601a str r2, [r3, #0]
|
|
|
- 801074a: 4770 bx lr
|
|
|
- 801074c: 40028000 .word 0x40028000
|
|
|
+ 80106bc: f022 0204 bic.w r2, r2, #4
|
|
|
+ 80106c0: 601a str r2, [r3, #0]
|
|
|
+ 80106c2: 4770 bx lr
|
|
|
+ 80106c4: 40028000 .word 0x40028000
|
|
|
|
|
|
-08010750 <ETH_MACAddressConfig>:
|
|
|
+080106c8 <ETH_MACAddressConfig>:
|
|
|
uint32_t tmpreg;
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
|
|
|
|
|
|
/* Calculate the selected MAC address high register */
|
|
|
tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
|
|
|
- 8010750: 790b ldrb r3, [r1, #4]
|
|
|
- 8010752: 794a ldrb r2, [r1, #5]
|
|
|
- 8010754: ea43 2202 orr.w r2, r3, r2, lsl #8
|
|
|
+ 80106c8: 790b ldrb r3, [r1, #4]
|
|
|
+ 80106ca: 794a ldrb r2, [r1, #5]
|
|
|
+ 80106cc: ea43 2202 orr.w r2, r3, r2, lsl #8
|
|
|
/* Load the selected MAC address high register */
|
|
|
(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
|
|
|
- 8010758: 4b07 ldr r3, [pc, #28] ; (8010778 <ETH_MACAddressConfig+0x28>)
|
|
|
- 801075a: 50c2 str r2, [r0, r3]
|
|
|
+ 80106d0: 4b07 ldr r3, [pc, #28] ; (80106f0 <ETH_MACAddressConfig+0x28>)
|
|
|
+ 80106d2: 50c2 str r2, [r0, r3]
|
|
|
/* Calculate the selected MAC address low register */
|
|
|
tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
|
|
|
- 801075c: 788a ldrb r2, [r1, #2]
|
|
|
- 801075e: 78cb ldrb r3, [r1, #3]
|
|
|
- 8010760: 0412 lsls r2, r2, #16
|
|
|
- 8010762: ea42 6203 orr.w r2, r2, r3, lsl #24
|
|
|
- 8010766: 780b ldrb r3, [r1, #0]
|
|
|
- 8010768: 431a orrs r2, r3
|
|
|
- 801076a: 784b ldrb r3, [r1, #1]
|
|
|
- 801076c: ea42 2203 orr.w r2, r2, r3, lsl #8
|
|
|
+ 80106d4: 788a ldrb r2, [r1, #2]
|
|
|
+ 80106d6: 78cb ldrb r3, [r1, #3]
|
|
|
+ 80106d8: 0412 lsls r2, r2, #16
|
|
|
+ 80106da: ea42 6203 orr.w r2, r2, r3, lsl #24
|
|
|
+ 80106de: 780b ldrb r3, [r1, #0]
|
|
|
+ 80106e0: 431a orrs r2, r3
|
|
|
+ 80106e2: 784b ldrb r3, [r1, #1]
|
|
|
+ 80106e4: ea42 2203 orr.w r2, r2, r3, lsl #8
|
|
|
|
|
|
/* Load the selected MAC address low register */
|
|
|
(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
|
|
|
- 8010770: 4b02 ldr r3, [pc, #8] ; (801077c <ETH_MACAddressConfig+0x2c>)
|
|
|
- 8010772: 50c2 str r2, [r0, r3]
|
|
|
- 8010774: 4770 bx lr
|
|
|
- 8010776: bf00 nop
|
|
|
- 8010778: 40028040 .word 0x40028040
|
|
|
- 801077c: 40028044 .word 0x40028044
|
|
|
-
|
|
|
-08010780 <ETH_Get_Received_Frame>:
|
|
|
+ 80106e8: 4b02 ldr r3, [pc, #8] ; (80106f4 <ETH_MACAddressConfig+0x2c>)
|
|
|
+ 80106ea: 50c2 str r2, [r0, r3]
|
|
|
+ 80106ec: 4770 bx lr
|
|
|
+ 80106ee: bf00 nop
|
|
|
+ 80106f0: 40028040 .word 0x40028040
|
|
|
+ 80106f4: 40028044 .word 0x40028044
|
|
|
+
|
|
|
+080106f8 <ETH_Get_Received_Frame>:
|
|
|
{
|
|
|
uint32_t framelength = 0;
|
|
|
FrameTypeDef frame = {0,0,0};
|
|
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
|
|
framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
|
|
- 8010780: 490a ldr r1, [pc, #40] ; (80107ac <ETH_Get_Received_Frame+0x2c>)
|
|
|
+ 80106f8: 490a ldr r1, [pc, #40] ; (8010724 <ETH_Get_Received_Frame+0x2c>)
|
|
|
frame.length = framelength;
|
|
|
|
|
|
/* Get the address of the buffer start address */
|
|
|
/* Check if more than one segment in the frame */
|
|
|
if (DMA_RX_FRAME_infos->Seg_Count >1)
|
|
|
- 8010782: 4a0b ldr r2, [pc, #44] ; (80107b0 <ETH_Get_Received_Frame+0x30>)
|
|
|
+ 80106fa: 4a0b ldr r2, [pc, #44] ; (8010728 <ETH_Get_Received_Frame+0x30>)
|
|
|
{
|
|
|
uint32_t framelength = 0;
|
|
|
FrameTypeDef frame = {0,0,0};
|
|
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
|
|
framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
|
|
- 8010784: 680b ldr r3, [r1, #0]
|
|
|
+ 80106fc: 680b ldr r3, [r1, #0]
|
|
|
frame.length = framelength;
|
|
|
|
|
|
/* Get the address of the buffer start address */
|
|
|
/* Check if more than one segment in the frame */
|
|
|
if (DMA_RX_FRAME_infos->Seg_Count >1)
|
|
|
- 8010786: 6812 ldr r2, [r2, #0]
|
|
|
+ 80106fe: 6812 ldr r2, [r2, #0]
|
|
|
/* Chained Mode */
|
|
|
/* Selects the next DMA Rx descriptor list for next buffer to read */
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
|
|
|
/* Return Frame */
|
|
|
return (frame);
|
|
|
- 8010788: 6083 str r3, [r0, #8]
|
|
|
+ 8010700: 6083 str r3, [r0, #8]
|
|
|
* with polling method only).
|
|
|
* @param none
|
|
|
* @retval Structure of type FrameTypeDef
|
|
|
*/
|
|
|
FrameTypeDef ETH_Get_Received_Frame(void)
|
|
|
{
|
|
|
- 801078a: b530 push {r4, r5, lr}
|
|
|
+ 8010702: b530 push {r4, r5, lr}
|
|
|
uint32_t framelength = 0;
|
|
|
FrameTypeDef frame = {0,0,0};
|
|
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
|
|
framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
|
|
- 801078c: 681d ldr r5, [r3, #0]
|
|
|
+ 8010704: 681d ldr r5, [r3, #0]
|
|
|
frame.length = framelength;
|
|
|
|
|
|
/* Get the address of the buffer start address */
|
|
|
/* Check if more than one segment in the frame */
|
|
|
if (DMA_RX_FRAME_infos->Seg_Count >1)
|
|
|
- 801078e: 6894 ldr r4, [r2, #8]
|
|
|
+ 8010706: 6894 ldr r4, [r2, #8]
|
|
|
{
|
|
|
uint32_t framelength = 0;
|
|
|
FrameTypeDef frame = {0,0,0};
|
|
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
|
|
framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
|
|
|
- 8010790: f3c5 450d ubfx r5, r5, #16, #14
|
|
|
- 8010794: 3d04 subs r5, #4
|
|
|
+ 8010708: f3c5 450d ubfx r5, r5, #16, #14
|
|
|
+ 801070c: 3d04 subs r5, #4
|
|
|
frame.length = framelength;
|
|
|
|
|
|
/* Get the address of the buffer start address */
|
|
|
/* Check if more than one segment in the frame */
|
|
|
if (DMA_RX_FRAME_infos->Seg_Count >1)
|
|
|
- 8010796: 2c01 cmp r4, #1
|
|
|
+ 801070e: 2c01 cmp r4, #1
|
|
|
{
|
|
|
frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
|
|
|
- 8010798: bf8a itet hi
|
|
|
- 801079a: 6812 ldrhi r2, [r2, #0]
|
|
|
+ 8010710: bf8a itet hi
|
|
|
+ 8010712: 6812 ldrhi r2, [r2, #0]
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
frame.buffer = DMARxDescToGet->Buffer1Addr;
|
|
|
- 801079c: 689a ldrls r2, [r3, #8]
|
|
|
+ 8010714: 689a ldrls r2, [r3, #8]
|
|
|
|
|
|
/* Get the address of the buffer start address */
|
|
|
/* Check if more than one segment in the frame */
|
|
|
if (DMA_RX_FRAME_infos->Seg_Count >1)
|
|
|
{
|
|
|
frame.buffer =(DMA_RX_FRAME_infos->FS_Rx_Desc)->Buffer1Addr;
|
|
|
- 801079e: 6892 ldrhi r2, [r2, #8]
|
|
|
+ 8010716: 6892 ldrhi r2, [r2, #8]
|
|
|
frame.descriptor = DMARxDescToGet;
|
|
|
|
|
|
/* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
|
|
/* Chained Mode */
|
|
|
/* Selects the next DMA Rx descriptor list for next buffer to read */
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
- 80107a0: 68dc ldr r4, [r3, #12]
|
|
|
+ 8010718: 68dc ldr r4, [r3, #12]
|
|
|
|
|
|
/* Return Frame */
|
|
|
return (frame);
|
|
|
- 80107a2: 6005 str r5, [r0, #0]
|
|
|
+ 801071a: 6005 str r5, [r0, #0]
|
|
|
frame.descriptor = DMARxDescToGet;
|
|
|
|
|
|
/* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
|
|
|
/* Chained Mode */
|
|
|
/* Selects the next DMA Rx descriptor list for next buffer to read */
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
- 80107a4: 600c str r4, [r1, #0]
|
|
|
+ 801071c: 600c str r4, [r1, #0]
|
|
|
|
|
|
/* Return Frame */
|
|
|
return (frame);
|
|
|
- 80107a6: 6042 str r2, [r0, #4]
|
|
|
+ 801071e: 6042 str r2, [r0, #4]
|
|
|
}
|
|
|
- 80107a8: bd30 pop {r4, r5, pc}
|
|
|
- 80107aa: bf00 nop
|
|
|
- 80107ac: 20008cbc .word 0x20008cbc
|
|
|
- 80107b0: 2000ab2c .word 0x2000ab2c
|
|
|
+ 8010720: bd30 pop {r4, r5, pc}
|
|
|
+ 8010722: bf00 nop
|
|
|
+ 8010724: 20008af8 .word 0x20008af8
|
|
|
+ 8010728: 2000a968 .word 0x2000a968
|
|
|
|
|
|
-080107b4 <ETH_Prepare_Transmit_Descriptors>:
|
|
|
+0801072c <ETH_Prepare_Transmit_Descriptors>:
|
|
|
{
|
|
|
uint32_t buf_count =0, size=0,i=0;
|
|
|
__IO ETH_DMADESCTypeDef *DMATxNextDesc;
|
|
|
|
|
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
|
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
|
|
- 80107b4: 4b29 ldr r3, [pc, #164] ; (801085c <ETH_Prepare_Transmit_Descriptors+0xa8>)
|
|
|
- 80107b6: 681b ldr r3, [r3, #0]
|
|
|
- 80107b8: 681a ldr r2, [r3, #0]
|
|
|
- 80107ba: 2a00 cmp r2, #0
|
|
|
+ 801072c: 4b29 ldr r3, [pc, #164] ; (80107d4 <ETH_Prepare_Transmit_Descriptors+0xa8>)
|
|
|
+ 801072e: 681b ldr r3, [r3, #0]
|
|
|
+ 8010730: 681a ldr r2, [r3, #0]
|
|
|
+ 8010732: 2a00 cmp r2, #0
|
|
|
* @brief Prepares DMA Tx descriptors to transmit an ethernet frame
|
|
|
* @param FrameLength : length of the frame to send
|
|
|
* @retval error status
|
|
|
*/
|
|
|
uint32_t ETH_Prepare_Transmit_Descriptors(u16 FrameLength)
|
|
|
{
|
|
|
- 80107bc: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
+ 8010734: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
uint32_t buf_count =0, size=0,i=0;
|
|
|
__IO ETH_DMADESCTypeDef *DMATxNextDesc;
|
|
|
|
|
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
|
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
|
|
- 80107be: db48 blt.n 8010852 <ETH_Prepare_Transmit_Descriptors+0x9e>
|
|
|
+ 8010736: db48 blt.n 80107ca <ETH_Prepare_Transmit_Descriptors+0x9e>
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
DMATxNextDesc = DMATxDescToSet;
|
|
|
|
|
|
if (FrameLength > ETH_TX_BUF_SIZE)
|
|
|
- 80107c0: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
|
- 80107c4: 4290 cmp r0, r2
|
|
|
- 80107c6: d917 bls.n 80107f8 <ETH_Prepare_Transmit_Descriptors+0x44>
|
|
|
+ 8010738: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
|
+ 801073c: 4290 cmp r0, r2
|
|
|
+ 801073e: d917 bls.n 8010770 <ETH_Prepare_Transmit_Descriptors+0x44>
|
|
|
{
|
|
|
buf_count = FrameLength/ETH_TX_BUF_SIZE;
|
|
|
- 80107c8: fbb0 f4f2 udiv r4, r0, r2
|
|
|
+ 8010740: fbb0 f4f2 udiv r4, r0, r2
|
|
|
if (FrameLength%ETH_TX_BUF_SIZE) buf_count++;
|
|
|
- 80107cc: fb02 0214 mls r2, r2, r4, r0
|
|
|
- 80107d0: b292 uxth r2, r2
|
|
|
+ 8010744: fb02 0214 mls r2, r2, r4, r0
|
|
|
+ 8010748: b292 uxth r2, r2
|
|
|
|
|
|
DMATxNextDesc = DMATxDescToSet;
|
|
|
|
|
|
if (FrameLength > ETH_TX_BUF_SIZE)
|
|
|
{
|
|
|
buf_count = FrameLength/ETH_TX_BUF_SIZE;
|
|
|
- 80107d2: b2a1 uxth r1, r4
|
|
|
+ 801074a: b2a1 uxth r1, r4
|
|
|
if (FrameLength%ETH_TX_BUF_SIZE) buf_count++;
|
|
|
- 80107d4: b10a cbz r2, 80107da <ETH_Prepare_Transmit_Descriptors+0x26>
|
|
|
- 80107d6: 3101 adds r1, #1
|
|
|
- 80107d8: e001 b.n 80107de <ETH_Prepare_Transmit_Descriptors+0x2a>
|
|
|
+ 801074c: b10a cbz r2, 8010752 <ETH_Prepare_Transmit_Descriptors+0x26>
|
|
|
+ 801074e: 3101 adds r1, #1
|
|
|
+ 8010750: e001 b.n 8010756 <ETH_Prepare_Transmit_Descriptors+0x2a>
|
|
|
}
|
|
|
else buf_count =1;
|
|
|
|
|
|
if (buf_count ==1)
|
|
|
- 80107da: 2901 cmp r1, #1
|
|
|
- 80107dc: d00c beq.n 80107f8 <ETH_Prepare_Transmit_Descriptors+0x44>
|
|
|
+ 8010752: 2901 cmp r1, #1
|
|
|
+ 8010754: d00c beq.n 8010770 <ETH_Prepare_Transmit_Descriptors+0x44>
|
|
|
|
|
|
if (i== (buf_count-1))
|
|
|
{
|
|
|
/* Setting the last segment bit */
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_LS;
|
|
|
size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE;
|
|
|
- 80107de: 4d20 ldr r5, [pc, #128] ; (8010860 <ETH_Prepare_Transmit_Descriptors+0xac>)
|
|
|
- 80107e0: f200 50f4 addw r0, r0, #1524 ; 0x5f4
|
|
|
- 80107e4: fb05 0501 mla r5, r5, r1, r0
|
|
|
+ 8010756: 4d20 ldr r5, [pc, #128] ; (80107d8 <ETH_Prepare_Transmit_Descriptors+0xac>)
|
|
|
+ 8010758: f200 50f4 addw r0, r0, #1524 ; 0x5f4
|
|
|
+ 801075c: fb05 0501 mla r5, r5, r1, r0
|
|
|
DMATxNextDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1);
|
|
|
- 80107e8: 04ed lsls r5, r5, #19
|
|
|
- 80107ea: 0ced lsrs r5, r5, #19
|
|
|
- 80107ec: 461a mov r2, r3
|
|
|
- 80107ee: 2000 movs r0, #0
|
|
|
+ 8010760: 04ed lsls r5, r5, #19
|
|
|
+ 8010762: 0ced lsrs r5, r5, #19
|
|
|
+ 8010764: 461a mov r2, r3
|
|
|
+ 8010766: 2000 movs r0, #0
|
|
|
/* Setting the first segment bit */
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_FS;
|
|
|
}
|
|
|
|
|
|
/* Program size */
|
|
|
DMATxNextDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1);
|
|
|
- 80107f0: f240 56f4 movw r6, #1524 ; 0x5f4
|
|
|
+ 8010768: f240 56f4 movw r6, #1524 ; 0x5f4
|
|
|
|
|
|
if (i== (buf_count-1))
|
|
|
- 80107f4: 1e4f subs r7, r1, #1
|
|
|
- 80107f6: e00c b.n 8010812 <ETH_Prepare_Transmit_Descriptors+0x5e>
|
|
|
+ 801076c: 1e4f subs r7, r1, #1
|
|
|
+ 801076e: e00c b.n 801078a <ETH_Prepare_Transmit_Descriptors+0x5e>
|
|
|
else buf_count =1;
|
|
|
|
|
|
if (buf_count ==1)
|
|
|
{
|
|
|
/*set LAST and FIRST segment */
|
|
|
DMATxDescToSet->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS;
|
|
|
- 80107f8: 681a ldr r2, [r3, #0]
|
|
|
+ 8010770: 681a ldr r2, [r3, #0]
|
|
|
/* Set frame size */
|
|
|
DMATxDescToSet->ControlBufferSize = (FrameLength& ETH_DMATxDesc_TBS1);
|
|
|
- 80107fa: 04c0 lsls r0, r0, #19
|
|
|
+ 8010772: 04c0 lsls r0, r0, #19
|
|
|
else buf_count =1;
|
|
|
|
|
|
if (buf_count ==1)
|
|
|
{
|
|
|
/*set LAST and FIRST segment */
|
|
|
DMATxDescToSet->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS;
|
|
|
- 80107fc: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
|
|
|
+ 8010774: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
|
|
|
/* Set frame size */
|
|
|
DMATxDescToSet->ControlBufferSize = (FrameLength& ETH_DMATxDesc_TBS1);
|
|
|
- 8010800: 0cc0 lsrs r0, r0, #19
|
|
|
+ 8010778: 0cc0 lsrs r0, r0, #19
|
|
|
else buf_count =1;
|
|
|
|
|
|
if (buf_count ==1)
|
|
|
{
|
|
|
/*set LAST and FIRST segment */
|
|
|
DMATxDescToSet->Status |=ETH_DMATxDesc_FS|ETH_DMATxDesc_LS;
|
|
|
- 8010802: 601a str r2, [r3, #0]
|
|
|
+ 801077a: 601a str r2, [r3, #0]
|
|
|
/* Set frame size */
|
|
|
DMATxDescToSet->ControlBufferSize = (FrameLength& ETH_DMATxDesc_TBS1);
|
|
|
- 8010804: 6058 str r0, [r3, #4]
|
|
|
+ 801077c: 6058 str r0, [r3, #4]
|
|
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
|
|
- 8010806: 681a ldr r2, [r3, #0]
|
|
|
- 8010808: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
|
|
- 801080c: 601a str r2, [r3, #0]
|
|
|
+ 801077e: 681a ldr r2, [r3, #0]
|
|
|
+ 8010780: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
|
|
+ 8010784: 601a str r2, [r3, #0]
|
|
|
DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
|
|
|
- 801080e: 68da ldr r2, [r3, #12]
|
|
|
- 8010810: e014 b.n 801083c <ETH_Prepare_Transmit_Descriptors+0x88>
|
|
|
+ 8010786: 68da ldr r2, [r3, #12]
|
|
|
+ 8010788: e014 b.n 80107b4 <ETH_Prepare_Transmit_Descriptors+0x88>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
for (i=0; i< buf_count; i++)
|
|
|
{
|
|
|
if (i==0)
|
|
|
- 8010812: b918 cbnz r0, 801081c <ETH_Prepare_Transmit_Descriptors+0x68>
|
|
|
+ 801078a: b918 cbnz r0, 8010794 <ETH_Prepare_Transmit_Descriptors+0x68>
|
|
|
{
|
|
|
/* Setting the first segment bit */
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_FS;
|
|
|
- 8010814: 681c ldr r4, [r3, #0]
|
|
|
- 8010816: f044 5480 orr.w r4, r4, #268435456 ; 0x10000000
|
|
|
- 801081a: 601c str r4, [r3, #0]
|
|
|
+ 801078c: 681c ldr r4, [r3, #0]
|
|
|
+ 801078e: f044 5480 orr.w r4, r4, #268435456 ; 0x10000000
|
|
|
+ 8010792: 601c str r4, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Program size */
|
|
|
DMATxNextDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1);
|
|
|
|
|
|
if (i== (buf_count-1))
|
|
|
- 801081c: 42b8 cmp r0, r7
|
|
|
+ 8010794: 42b8 cmp r0, r7
|
|
|
/* Setting the first segment bit */
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_FS;
|
|
|
}
|
|
|
|
|
|
/* Program size */
|
|
|
DMATxNextDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATxDesc_TBS1);
|
|
|
- 801081e: 6056 str r6, [r2, #4]
|
|
|
+ 8010796: 6056 str r6, [r2, #4]
|
|
|
|
|
|
if (i== (buf_count-1))
|
|
|
- 8010820: d104 bne.n 801082c <ETH_Prepare_Transmit_Descriptors+0x78>
|
|
|
+ 8010798: d104 bne.n 80107a4 <ETH_Prepare_Transmit_Descriptors+0x78>
|
|
|
{
|
|
|
/* Setting the last segment bit */
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_LS;
|
|
|
- 8010822: 6814 ldr r4, [r2, #0]
|
|
|
- 8010824: f044 5400 orr.w r4, r4, #536870912 ; 0x20000000
|
|
|
- 8010828: 6014 str r4, [r2, #0]
|
|
|
+ 801079a: 6814 ldr r4, [r2, #0]
|
|
|
+ 801079c: f044 5400 orr.w r4, r4, #536870912 ; 0x20000000
|
|
|
+ 80107a0: 6014 str r4, [r2, #0]
|
|
|
size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE;
|
|
|
DMATxNextDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1);
|
|
|
- 801082a: 6055 str r5, [r2, #4]
|
|
|
+ 80107a2: 6055 str r5, [r2, #4]
|
|
|
}
|
|
|
|
|
|
/*give back descriptor to DMA */
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
|
|
|
- 801082c: 6814 ldr r4, [r2, #0]
|
|
|
+ 80107a4: 6814 ldr r4, [r2, #0]
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
|
|
DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
for (i=0; i< buf_count; i++)
|
|
|
- 801082e: 3001 adds r0, #1
|
|
|
+ 80107a6: 3001 adds r0, #1
|
|
|
size = FrameLength - (buf_count-1)*ETH_TX_BUF_SIZE;
|
|
|
DMATxNextDesc->ControlBufferSize = (size & ETH_DMATxDesc_TBS1);
|
|
|
}
|
|
|
|
|
|
/*give back descriptor to DMA */
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
|
|
|
- 8010830: f044 4400 orr.w r4, r4, #2147483648 ; 0x80000000
|
|
|
- 8010834: 6014 str r4, [r2, #0]
|
|
|
+ 80107a8: f044 4400 orr.w r4, r4, #2147483648 ; 0x80000000
|
|
|
+ 80107ac: 6014 str r4, [r2, #0]
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
|
|
DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
for (i=0; i< buf_count; i++)
|
|
|
- 8010836: 4288 cmp r0, r1
|
|
|
+ 80107ae: 4288 cmp r0, r1
|
|
|
}
|
|
|
|
|
|
/*give back descriptor to DMA */
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
|
|
|
|
|
|
DMATxNextDesc = (ETH_DMADESCTypeDef *)(DMATxNextDesc->Buffer2NextDescAddr);
|
|
|
- 8010838: 68d2 ldr r2, [r2, #12]
|
|
|
+ 80107b0: 68d2 ldr r2, [r2, #12]
|
|
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
|
|
DMATxDescToSet= (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
for (i=0; i< buf_count; i++)
|
|
|
- 801083a: d3ea bcc.n 8010812 <ETH_Prepare_Transmit_Descriptors+0x5e>
|
|
|
+ 80107b2: d3ea bcc.n 801078a <ETH_Prepare_Transmit_Descriptors+0x5e>
|
|
|
DMATxNextDesc->Status |= ETH_DMATxDesc_OWN;
|
|
|
|
|
|
DMATxNextDesc = (ETH_DMADESCTypeDef *)(DMATxNextDesc->Buffer2NextDescAddr);
|
|
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
|
|
}
|
|
|
DMATxDescToSet = DMATxNextDesc ;
|
|
|
- 801083c: 4b07 ldr r3, [pc, #28] ; (801085c <ETH_Prepare_Transmit_Descriptors+0xa8>)
|
|
|
- 801083e: 601a str r2, [r3, #0]
|
|
|
+ 80107b4: 4b07 ldr r3, [pc, #28] ; (80107d4 <ETH_Prepare_Transmit_Descriptors+0xa8>)
|
|
|
+ 80107b6: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
|
|
|
if ((ETH->DMASR & ETH_DMASR_TBUS) != (u32)RESET)
|
|
|
- 8010840: 4b08 ldr r3, [pc, #32] ; (8010864 <ETH_Prepare_Transmit_Descriptors+0xb0>)
|
|
|
- 8010842: 695a ldr r2, [r3, #20]
|
|
|
- 8010844: 0750 lsls r0, r2, #29
|
|
|
- 8010846: d506 bpl.n 8010856 <ETH_Prepare_Transmit_Descriptors+0xa2>
|
|
|
+ 80107b8: 4b08 ldr r3, [pc, #32] ; (80107dc <ETH_Prepare_Transmit_Descriptors+0xb0>)
|
|
|
+ 80107ba: 695a ldr r2, [r3, #20]
|
|
|
+ 80107bc: 0750 lsls r0, r2, #29
|
|
|
+ 80107be: d506 bpl.n 80107ce <ETH_Prepare_Transmit_Descriptors+0xa2>
|
|
|
{
|
|
|
/* Clear TBUS ETHERNET DMA flag */
|
|
|
ETH->DMASR = ETH_DMASR_TBUS;
|
|
|
- 8010848: 2204 movs r2, #4
|
|
|
- 801084a: 615a str r2, [r3, #20]
|
|
|
+ 80107c0: 2204 movs r2, #4
|
|
|
+ 80107c2: 615a str r2, [r3, #20]
|
|
|
/* Resume DMA transmission*/
|
|
|
ETH->DMATPDR = 0;
|
|
|
- 801084c: 2200 movs r2, #0
|
|
|
- 801084e: 605a str r2, [r3, #4]
|
|
|
- 8010850: e001 b.n 8010856 <ETH_Prepare_Transmit_Descriptors+0xa2>
|
|
|
+ 80107c4: 2200 movs r2, #0
|
|
|
+ 80107c6: 605a str r2, [r3, #4]
|
|
|
+ 80107c8: e001 b.n 80107ce <ETH_Prepare_Transmit_Descriptors+0xa2>
|
|
|
|
|
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
|
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
|
|
{
|
|
|
/* Return ERROR: OWN bit set */
|
|
|
return ETH_ERROR;
|
|
|
- 8010852: 2000 movs r0, #0
|
|
|
- 8010854: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 80107ca: 2000 movs r0, #0
|
|
|
+ 80107cc: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
/* Resume DMA transmission*/
|
|
|
ETH->DMATPDR = 0;
|
|
|
}
|
|
|
|
|
|
/* Return SUCCESS */
|
|
|
return ETH_SUCCESS;
|
|
|
- 8010856: 2001 movs r0, #1
|
|
|
+ 80107ce: 2001 movs r0, #1
|
|
|
}
|
|
|
- 8010858: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
- 801085a: bf00 nop
|
|
|
- 801085c: 20008cc0 .word 0x20008cc0
|
|
|
- 8010860: fffffa0c .word 0xfffffa0c
|
|
|
- 8010864: 40029000 .word 0x40029000
|
|
|
+ 80107d0: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 80107d2: bf00 nop
|
|
|
+ 80107d4: 20008afc .word 0x20008afc
|
|
|
+ 80107d8: fffffa0c .word 0xfffffa0c
|
|
|
+ 80107dc: 40029000 .word 0x40029000
|
|
|
|
|
|
-08010868 <ETH_DMARxDescChainInit>:
|
|
|
+080107e0 <ETH_DMARxDescChainInit>:
|
|
|
{
|
|
|
uint32_t i = 0;
|
|
|
ETH_DMADESCTypeDef *DMARxDesc;
|
|
|
|
|
|
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
|
|
|
DMARxDescToGet = DMARxDescTab;
|
|
|
- 8010868: 4b11 ldr r3, [pc, #68] ; (80108b0 <ETH_DMARxDescChainInit+0x48>)
|
|
|
+ 80107e0: 4b11 ldr r3, [pc, #68] ; (8010828 <ETH_DMARxDescChainInit+0x48>)
|
|
|
* @param RxBuff: Pointer on the first RxBuffer list
|
|
|
* @param RxBuffCount: Number of the used Rx desc in the list
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
|
|
{
|
|
|
- 801086a: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
+ 80107e2: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
uint32_t i = 0;
|
|
|
ETH_DMADESCTypeDef *DMARxDesc;
|
|
|
|
|
|
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
|
|
|
DMARxDescToGet = DMARxDescTab;
|
|
|
- 801086c: 6018 str r0, [r3, #0]
|
|
|
+ 80107e4: 6018 str r0, [r3, #0]
|
|
|
/* Fill each DMARxDesc descriptor with the right values */
|
|
|
for(i=0; i < RxBuffCount; i++)
|
|
|
- 801086e: 2400 movs r4, #0
|
|
|
+ 80107e6: 2400 movs r4, #0
|
|
|
* @param DMARxDescTab: Pointer on the first Rx desc list
|
|
|
* @param RxBuff: Pointer on the first RxBuffer list
|
|
|
* @param RxBuffCount: Number of the used Rx desc in the list
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
|
|
- 8010870: f100 0320 add.w r3, r0, #32
|
|
|
+ 80107e8: f100 0320 add.w r3, r0, #32
|
|
|
for(i=0; i < RxBuffCount; i++)
|
|
|
{
|
|
|
/* Get the pointer on the ith member of the Rx Desc list */
|
|
|
DMARxDesc = DMARxDescTab+i;
|
|
|
/* Set Own bit of the Rx descriptor Status */
|
|
|
DMARxDesc->Status = ETH_DMARxDesc_OWN;
|
|
|
- 8010874: f04f 4500 mov.w r5, #2147483648 ; 0x80000000
|
|
|
+ 80107ec: f04f 4500 mov.w r5, #2147483648 ; 0x80000000
|
|
|
|
|
|
/* Set Buffer1 size and Second Address Chained bit */
|
|
|
DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE;
|
|
|
- 8010878: f244 56f4 movw r6, #17908 ; 0x45f4
|
|
|
+ 80107f0: f244 56f4 movw r6, #17908 ; 0x45f4
|
|
|
/* Set Buffer1 address pointer */
|
|
|
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (RxBuffCount-1))
|
|
|
- 801087c: 1e57 subs r7, r2, #1
|
|
|
+ 80107f4: 1e57 subs r7, r2, #1
|
|
|
ETH_DMADESCTypeDef *DMARxDesc;
|
|
|
|
|
|
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
|
|
|
DMARxDescToGet = DMARxDescTab;
|
|
|
/* Fill each DMARxDesc descriptor with the right values */
|
|
|
for(i=0; i < RxBuffCount; i++)
|
|
|
- 801087e: e00f b.n 80108a0 <ETH_DMARxDescChainInit+0x38>
|
|
|
+ 80107f6: e00f b.n 8010818 <ETH_DMARxDescChainInit+0x38>
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (RxBuffCount-1))
|
|
|
{
|
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
|
|
|
- 8010880: 42bc cmp r4, r7
|
|
|
- 8010882: bf2c ite cs
|
|
|
- 8010884: 4684 movcs ip, r0
|
|
|
- 8010886: 469c movcc ip, r3
|
|
|
+ 80107f8: 42bc cmp r4, r7
|
|
|
+ 80107fa: bf2c ite cs
|
|
|
+ 80107fc: 4684 movcs ip, r0
|
|
|
+ 80107fe: 469c movcc ip, r3
|
|
|
DMARxDesc->Status = ETH_DMARxDesc_OWN;
|
|
|
|
|
|
/* Set Buffer1 size and Second Address Chained bit */
|
|
|
DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE;
|
|
|
/* Set Buffer1 address pointer */
|
|
|
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
|
|
|
- 8010888: f843 1c18 str.w r1, [r3, #-24]
|
|
|
+ 8010800: f843 1c18 str.w r1, [r3, #-24]
|
|
|
for(i=0; i < RxBuffCount; i++)
|
|
|
{
|
|
|
/* Get the pointer on the ith member of the Rx Desc list */
|
|
|
DMARxDesc = DMARxDescTab+i;
|
|
|
/* Set Own bit of the Rx descriptor Status */
|
|
|
DMARxDesc->Status = ETH_DMARxDesc_OWN;
|
|
|
- 801088c: f843 5c20 str.w r5, [r3, #-32]
|
|
|
+ 8010804: f843 5c20 str.w r5, [r3, #-32]
|
|
|
|
|
|
/* Set Buffer1 size and Second Address Chained bit */
|
|
|
DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_RX_BUF_SIZE;
|
|
|
- 8010890: f843 6c1c str.w r6, [r3, #-28]
|
|
|
+ 8010808: f843 6c1c str.w r6, [r3, #-28]
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (RxBuffCount-1))
|
|
|
{
|
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
|
|
|
- 8010894: f843 cc14 str.w ip, [r3, #-20]
|
|
|
+ 801080c: f843 cc14 str.w ip, [r3, #-20]
|
|
|
ETH_DMADESCTypeDef *DMARxDesc;
|
|
|
|
|
|
/* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
|
|
|
DMARxDescToGet = DMARxDescTab;
|
|
|
/* Fill each DMARxDesc descriptor with the right values */
|
|
|
for(i=0; i < RxBuffCount; i++)
|
|
|
- 8010898: 3401 adds r4, #1
|
|
|
- 801089a: 3320 adds r3, #32
|
|
|
- 801089c: f201 51f4 addw r1, r1, #1524 ; 0x5f4
|
|
|
- 80108a0: 4294 cmp r4, r2
|
|
|
- 80108a2: d1ed bne.n 8010880 <ETH_DMARxDescChainInit+0x18>
|
|
|
+ 8010810: 3401 adds r4, #1
|
|
|
+ 8010812: 3320 adds r3, #32
|
|
|
+ 8010814: f201 51f4 addw r1, r1, #1524 ; 0x5f4
|
|
|
+ 8010818: 4294 cmp r4, r2
|
|
|
+ 801081a: d1ed bne.n 80107f8 <ETH_DMARxDescChainInit+0x18>
|
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Set Receive Descriptor List Address Register */
|
|
|
ETH->DMARDLAR = (uint32_t) DMARxDescTab;
|
|
|
- 80108a4: 4b03 ldr r3, [pc, #12] ; (80108b4 <ETH_DMARxDescChainInit+0x4c>)
|
|
|
+ 801081c: 4b03 ldr r3, [pc, #12] ; (801082c <ETH_DMARxDescChainInit+0x4c>)
|
|
|
|
|
|
|
|
|
DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
|
|
|
- 80108a6: 4a04 ldr r2, [pc, #16] ; (80108b8 <ETH_DMARxDescChainInit+0x50>)
|
|
|
+ 801081e: 4a04 ldr r2, [pc, #16] ; (8010830 <ETH_DMARxDescChainInit+0x50>)
|
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Set Receive Descriptor List Address Register */
|
|
|
ETH->DMARDLAR = (uint32_t) DMARxDescTab;
|
|
|
- 80108a8: 60d8 str r0, [r3, #12]
|
|
|
+ 8010820: 60d8 str r0, [r3, #12]
|
|
|
|
|
|
|
|
|
DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
|
|
|
- 80108aa: 4b04 ldr r3, [pc, #16] ; (80108bc <ETH_DMARxDescChainInit+0x54>)
|
|
|
- 80108ac: 601a str r2, [r3, #0]
|
|
|
- 80108ae: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
- 80108b0: 20008cbc .word 0x20008cbc
|
|
|
- 80108b4: 40029000 .word 0x40029000
|
|
|
- 80108b8: 20008cb0 .word 0x20008cb0
|
|
|
- 80108bc: 2000ab2c .word 0x2000ab2c
|
|
|
-
|
|
|
-080108c0 <ETH_CheckFrameReceived>:
|
|
|
+ 8010822: 4b04 ldr r3, [pc, #16] ; (8010834 <ETH_DMARxDescChainInit+0x54>)
|
|
|
+ 8010824: 601a str r2, [r3, #0]
|
|
|
+ 8010826: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 8010828: 20008af8 .word 0x20008af8
|
|
|
+ 801082c: 40029000 .word 0x40029000
|
|
|
+ 8010830: 20008aec .word 0x20008aec
|
|
|
+ 8010834: 2000a968 .word 0x2000a968
|
|
|
+
|
|
|
+08010838 <ETH_CheckFrameReceived>:
|
|
|
* @retval Returns 1 when a frame is received, 0 if none.
|
|
|
*/
|
|
|
uint32_t ETH_CheckFrameReceived(void)
|
|
|
{
|
|
|
/* check if last segment */
|
|
|
if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 80108c0: 4b1c ldr r3, [pc, #112] ; (8010934 <ETH_CheckFrameReceived+0x74>)
|
|
|
- 80108c2: 681b ldr r3, [r3, #0]
|
|
|
- 80108c4: 681a ldr r2, [r3, #0]
|
|
|
- 80108c6: 2a00 cmp r2, #0
|
|
|
- 80108c8: db0a blt.n 80108e0 <ETH_CheckFrameReceived+0x20>
|
|
|
+ 8010838: 4b1c ldr r3, [pc, #112] ; (80108ac <ETH_CheckFrameReceived+0x74>)
|
|
|
+ 801083a: 681b ldr r3, [r3, #0]
|
|
|
+ 801083c: 681a ldr r2, [r3, #0]
|
|
|
+ 801083e: 2a00 cmp r2, #0
|
|
|
+ 8010840: db0a blt.n 8010858 <ETH_CheckFrameReceived+0x20>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET))
|
|
|
- 80108ca: 681a ldr r2, [r3, #0]
|
|
|
+ 8010842: 681a ldr r2, [r3, #0]
|
|
|
* @retval Returns 1 when a frame is received, 0 if none.
|
|
|
*/
|
|
|
uint32_t ETH_CheckFrameReceived(void)
|
|
|
{
|
|
|
/* check if last segment */
|
|
|
if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 80108cc: 05d1 lsls r1, r2, #23
|
|
|
- 80108ce: d507 bpl.n 80108e0 <ETH_CheckFrameReceived+0x20>
|
|
|
+ 8010844: 05d1 lsls r1, r2, #23
|
|
|
+ 8010846: d507 bpl.n 8010858 <ETH_CheckFrameReceived+0x20>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET))
|
|
|
{
|
|
|
DMA_RX_FRAME_infos->LS_Rx_Desc = DMARxDescToGet;
|
|
|
- 80108d0: 4a19 ldr r2, [pc, #100] ; (8010938 <ETH_CheckFrameReceived+0x78>)
|
|
|
- 80108d2: 6812 ldr r2, [r2, #0]
|
|
|
- 80108d4: 6053 str r3, [r2, #4]
|
|
|
+ 8010848: 4a19 ldr r2, [pc, #100] ; (80108b0 <ETH_CheckFrameReceived+0x78>)
|
|
|
+ 801084a: 6812 ldr r2, [r2, #0]
|
|
|
+ 801084c: 6053 str r3, [r2, #4]
|
|
|
DMA_RX_FRAME_infos->Seg_Count++;
|
|
|
- 80108d6: 6893 ldr r3, [r2, #8]
|
|
|
- 80108d8: 3301 adds r3, #1
|
|
|
- 80108da: 6093 str r3, [r2, #8]
|
|
|
+ 801084e: 6893 ldr r3, [r2, #8]
|
|
|
+ 8010850: 3301 adds r3, #1
|
|
|
+ 8010852: 6093 str r3, [r2, #8]
|
|
|
return 1;
|
|
|
- 80108dc: 2001 movs r0, #1
|
|
|
- 80108de: 4770 bx lr
|
|
|
+ 8010854: 2001 movs r0, #1
|
|
|
+ 8010856: 4770 bx lr
|
|
|
}
|
|
|
|
|
|
/* check if first segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 80108e0: 681a ldr r2, [r3, #0]
|
|
|
- 80108e2: 2a00 cmp r2, #0
|
|
|
- 80108e4: db10 blt.n 8010908 <ETH_CheckFrameReceived+0x48>
|
|
|
+ 8010858: 681a ldr r2, [r3, #0]
|
|
|
+ 801085a: 2a00 cmp r2, #0
|
|
|
+ 801085c: db10 blt.n 8010880 <ETH_CheckFrameReceived+0x48>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
|
|
- 80108e6: 681a ldr r2, [r3, #0]
|
|
|
+ 801085e: 681a ldr r2, [r3, #0]
|
|
|
DMA_RX_FRAME_infos->Seg_Count++;
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
/* check if first segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 80108e8: 0592 lsls r2, r2, #22
|
|
|
- 80108ea: d50d bpl.n 8010908 <ETH_CheckFrameReceived+0x48>
|
|
|
+ 8010860: 0592 lsls r2, r2, #22
|
|
|
+ 8010862: d50d bpl.n 8010880 <ETH_CheckFrameReceived+0x48>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
|
|
- 80108ec: 6818 ldr r0, [r3, #0]
|
|
|
+ 8010864: 6818 ldr r0, [r3, #0]
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
/* check if first segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
|
|
- 80108ee: f410 7080 ands.w r0, r0, #256 ; 0x100
|
|
|
- 80108f2: d109 bne.n 8010908 <ETH_CheckFrameReceived+0x48>
|
|
|
+ 8010866: f410 7080 ands.w r0, r0, #256 ; 0x100
|
|
|
+ 801086a: d109 bne.n 8010880 <ETH_CheckFrameReceived+0x48>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
|
|
{
|
|
|
DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
|
|
|
- 80108f4: 4a10 ldr r2, [pc, #64] ; (8010938 <ETH_CheckFrameReceived+0x78>)
|
|
|
- 80108f6: 6812 ldr r2, [r2, #0]
|
|
|
+ 801086c: 4a10 ldr r2, [pc, #64] ; (80108b0 <ETH_CheckFrameReceived+0x78>)
|
|
|
+ 801086e: 6812 ldr r2, [r2, #0]
|
|
|
DMA_RX_FRAME_infos->LS_Rx_Desc = NULL;
|
|
|
DMA_RX_FRAME_infos->Seg_Count = 1;
|
|
|
- 80108f8: 2101 movs r1, #1
|
|
|
+ 8010870: 2101 movs r1, #1
|
|
|
/* check if first segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)&&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
|
|
{
|
|
|
DMA_RX_FRAME_infos->FS_Rx_Desc = DMARxDescToGet;
|
|
|
- 80108fa: 6013 str r3, [r2, #0]
|
|
|
+ 8010872: 6013 str r3, [r2, #0]
|
|
|
DMA_RX_FRAME_infos->LS_Rx_Desc = NULL;
|
|
|
- 80108fc: 6050 str r0, [r2, #4]
|
|
|
+ 8010874: 6050 str r0, [r2, #4]
|
|
|
DMA_RX_FRAME_infos->Seg_Count = 1;
|
|
|
- 80108fe: 6091 str r1, [r2, #8]
|
|
|
+ 8010876: 6091 str r1, [r2, #8]
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
- 8010900: 68da ldr r2, [r3, #12]
|
|
|
- 8010902: 4b0c ldr r3, [pc, #48] ; (8010934 <ETH_CheckFrameReceived+0x74>)
|
|
|
- 8010904: 601a str r2, [r3, #0]
|
|
|
- 8010906: 4770 bx lr
|
|
|
+ 8010878: 68da ldr r2, [r3, #12]
|
|
|
+ 801087a: 4b0c ldr r3, [pc, #48] ; (80108ac <ETH_CheckFrameReceived+0x74>)
|
|
|
+ 801087c: 601a str r2, [r3, #0]
|
|
|
+ 801087e: 4770 bx lr
|
|
|
}
|
|
|
|
|
|
/* check if intermediate segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 8010908: 681a ldr r2, [r3, #0]
|
|
|
- 801090a: 2a00 cmp r2, #0
|
|
|
- 801090c: db0f blt.n 801092e <ETH_CheckFrameReceived+0x6e>
|
|
|
+ 8010880: 681a ldr r2, [r3, #0]
|
|
|
+ 8010882: 2a00 cmp r2, #0
|
|
|
+ 8010884: db0f blt.n 80108a6 <ETH_CheckFrameReceived+0x6e>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&&
|
|
|
- 801090e: 6818 ldr r0, [r3, #0]
|
|
|
+ 8010886: 6818 ldr r0, [r3, #0]
|
|
|
DMA_RX_FRAME_infos->Seg_Count = 1;
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
}
|
|
|
|
|
|
/* check if intermediate segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
- 8010910: f410 7000 ands.w r0, r0, #512 ; 0x200
|
|
|
- 8010914: d10b bne.n 801092e <ETH_CheckFrameReceived+0x6e>
|
|
|
+ 8010888: f410 7000 ands.w r0, r0, #512 ; 0x200
|
|
|
+ 801088c: d10b bne.n 80108a6 <ETH_CheckFrameReceived+0x6e>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
|
|
- 8010916: 681a ldr r2, [r3, #0]
|
|
|
+ 801088e: 681a ldr r2, [r3, #0]
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
}
|
|
|
|
|
|
/* check if intermediate segment */
|
|
|
else if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_FS) == (uint32_t)RESET)&&
|
|
|
- 8010918: f412 7180 ands.w r1, r2, #256 ; 0x100
|
|
|
- 801091c: d108 bne.n 8010930 <ETH_CheckFrameReceived+0x70>
|
|
|
+ 8010890: f412 7180 ands.w r1, r2, #256 ; 0x100
|
|
|
+ 8010894: d108 bne.n 80108a8 <ETH_CheckFrameReceived+0x70>
|
|
|
((DMARxDescToGet->Status & ETH_DMARxDesc_LS) == (uint32_t)RESET))
|
|
|
{
|
|
|
(DMA_RX_FRAME_infos->Seg_Count) ++;
|
|
|
- 801091e: 4a06 ldr r2, [pc, #24] ; (8010938 <ETH_CheckFrameReceived+0x78>)
|
|
|
- 8010920: 6812 ldr r2, [r2, #0]
|
|
|
- 8010922: 6890 ldr r0, [r2, #8]
|
|
|
- 8010924: 3001 adds r0, #1
|
|
|
- 8010926: 6090 str r0, [r2, #8]
|
|
|
+ 8010896: 4a06 ldr r2, [pc, #24] ; (80108b0 <ETH_CheckFrameReceived+0x78>)
|
|
|
+ 8010898: 6812 ldr r2, [r2, #0]
|
|
|
+ 801089a: 6890 ldr r0, [r2, #8]
|
|
|
+ 801089c: 3001 adds r0, #1
|
|
|
+ 801089e: 6090 str r0, [r2, #8]
|
|
|
DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
|
|
|
- 8010928: 68da ldr r2, [r3, #12]
|
|
|
- 801092a: 4b02 ldr r3, [pc, #8] ; (8010934 <ETH_CheckFrameReceived+0x74>)
|
|
|
- 801092c: 601a str r2, [r3, #0]
|
|
|
+ 80108a0: 68da ldr r2, [r3, #12]
|
|
|
+ 80108a2: 4b02 ldr r3, [pc, #8] ; (80108ac <ETH_CheckFrameReceived+0x74>)
|
|
|
+ 80108a4: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
return 0;
|
|
|
- 801092e: 2000 movs r0, #0
|
|
|
+ 80108a6: 2000 movs r0, #0
|
|
|
}
|
|
|
- 8010930: 4770 bx lr
|
|
|
- 8010932: bf00 nop
|
|
|
- 8010934: 20008cbc .word 0x20008cbc
|
|
|
- 8010938: 2000ab2c .word 0x2000ab2c
|
|
|
+ 80108a8: 4770 bx lr
|
|
|
+ 80108aa: bf00 nop
|
|
|
+ 80108ac: 20008af8 .word 0x20008af8
|
|
|
+ 80108b0: 2000a968 .word 0x2000a968
|
|
|
|
|
|
-0801093c <ETH_DMATxDescChainInit>:
|
|
|
+080108b4 <ETH_DMATxDescChainInit>:
|
|
|
{
|
|
|
uint32_t i = 0;
|
|
|
ETH_DMADESCTypeDef *DMATxDesc;
|
|
|
|
|
|
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
|
|
DMATxDescToSet = DMATxDescTab;
|
|
|
- 801093c: 4b0e ldr r3, [pc, #56] ; (8010978 <ETH_DMATxDescChainInit+0x3c>)
|
|
|
+ 80108b4: 4b0e ldr r3, [pc, #56] ; (80108f0 <ETH_DMATxDescChainInit+0x3c>)
|
|
|
* @param TxBuff: Pointer on the first TxBuffer list
|
|
|
* @param TxBuffCount: Number of the used Tx desc in the list
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
|
|
|
{
|
|
|
- 801093e: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
+ 80108b6: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
uint32_t i = 0;
|
|
|
ETH_DMADESCTypeDef *DMATxDesc;
|
|
|
|
|
|
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
|
|
DMATxDescToSet = DMATxDescTab;
|
|
|
- 8010940: 6018 str r0, [r3, #0]
|
|
|
+ 80108b8: 6018 str r0, [r3, #0]
|
|
|
/* Fill each DMATxDesc descriptor with the right values */
|
|
|
for(i=0; i < TxBuffCount; i++)
|
|
|
- 8010942: 2400 movs r4, #0
|
|
|
+ 80108ba: 2400 movs r4, #0
|
|
|
* @param DMATxDescTab: Pointer on the first Tx desc list
|
|
|
* @param TxBuff: Pointer on the first TxBuffer list
|
|
|
* @param TxBuffCount: Number of the used Tx desc in the list
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
|
|
|
- 8010944: f100 0320 add.w r3, r0, #32
|
|
|
+ 80108bc: f100 0320 add.w r3, r0, #32
|
|
|
for(i=0; i < TxBuffCount; i++)
|
|
|
{
|
|
|
/* Get the pointer on the ith member of the Tx Desc list */
|
|
|
DMATxDesc = DMATxDescTab + i;
|
|
|
/* Set Second Address Chained bit */
|
|
|
DMATxDesc->Status = ETH_DMATxDesc_TCH;
|
|
|
- 8010948: f44f 1580 mov.w r5, #1048576 ; 0x100000
|
|
|
+ 80108c0: f44f 1580 mov.w r5, #1048576 ; 0x100000
|
|
|
|
|
|
/* Set Buffer1 address pointer */
|
|
|
DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (TxBuffCount-1))
|
|
|
- 801094c: 1e56 subs r6, r2, #1
|
|
|
+ 80108c4: 1e56 subs r6, r2, #1
|
|
|
ETH_DMADESCTypeDef *DMATxDesc;
|
|
|
|
|
|
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
|
|
DMATxDescToSet = DMATxDescTab;
|
|
|
/* Fill each DMATxDesc descriptor with the right values */
|
|
|
for(i=0; i < TxBuffCount; i++)
|
|
|
- 801094e: e00d b.n 801096c <ETH_DMATxDescChainInit+0x30>
|
|
|
+ 80108c6: e00d b.n 80108e4 <ETH_DMATxDescChainInit+0x30>
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (TxBuffCount-1))
|
|
|
{
|
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
|
DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
|
|
|
- 8010950: 42b4 cmp r4, r6
|
|
|
- 8010952: bf2c ite cs
|
|
|
- 8010954: 4607 movcs r7, r0
|
|
|
- 8010956: 461f movcc r7, r3
|
|
|
+ 80108c8: 42b4 cmp r4, r6
|
|
|
+ 80108ca: bf2c ite cs
|
|
|
+ 80108cc: 4607 movcs r7, r0
|
|
|
+ 80108ce: 461f movcc r7, r3
|
|
|
DMATxDesc = DMATxDescTab + i;
|
|
|
/* Set Second Address Chained bit */
|
|
|
DMATxDesc->Status = ETH_DMATxDesc_TCH;
|
|
|
|
|
|
/* Set Buffer1 address pointer */
|
|
|
DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
|
|
|
- 8010958: f843 1c18 str.w r1, [r3, #-24]
|
|
|
+ 80108d0: f843 1c18 str.w r1, [r3, #-24]
|
|
|
for(i=0; i < TxBuffCount; i++)
|
|
|
{
|
|
|
/* Get the pointer on the ith member of the Tx Desc list */
|
|
|
DMATxDesc = DMATxDescTab + i;
|
|
|
/* Set Second Address Chained bit */
|
|
|
DMATxDesc->Status = ETH_DMATxDesc_TCH;
|
|
|
- 801095c: f843 5c20 str.w r5, [r3, #-32]
|
|
|
+ 80108d4: f843 5c20 str.w r5, [r3, #-32]
|
|
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
|
if(i < (TxBuffCount-1))
|
|
|
{
|
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
|
DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
|
|
|
- 8010960: f843 7c14 str.w r7, [r3, #-20]
|
|
|
+ 80108d8: f843 7c14 str.w r7, [r3, #-20]
|
|
|
ETH_DMADESCTypeDef *DMATxDesc;
|
|
|
|
|
|
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
|
|
DMATxDescToSet = DMATxDescTab;
|
|
|
/* Fill each DMATxDesc descriptor with the right values */
|
|
|
for(i=0; i < TxBuffCount; i++)
|
|
|
- 8010964: 3401 adds r4, #1
|
|
|
- 8010966: 3320 adds r3, #32
|
|
|
- 8010968: f201 51f4 addw r1, r1, #1524 ; 0x5f4
|
|
|
- 801096c: 4294 cmp r4, r2
|
|
|
- 801096e: d1ef bne.n 8010950 <ETH_DMATxDescChainInit+0x14>
|
|
|
+ 80108dc: 3401 adds r4, #1
|
|
|
+ 80108de: 3320 adds r3, #32
|
|
|
+ 80108e0: f201 51f4 addw r1, r1, #1524 ; 0x5f4
|
|
|
+ 80108e4: 4294 cmp r4, r2
|
|
|
+ 80108e6: d1ef bne.n 80108c8 <ETH_DMATxDescChainInit+0x14>
|
|
|
DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Set Transmit Desciptor List Address Register */
|
|
|
ETH->DMATDLAR = (uint32_t) DMATxDescTab;
|
|
|
- 8010970: 4b02 ldr r3, [pc, #8] ; (801097c <ETH_DMATxDescChainInit+0x40>)
|
|
|
- 8010972: 6118 str r0, [r3, #16]
|
|
|
- 8010974: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
- 8010976: bf00 nop
|
|
|
- 8010978: 20008cc0 .word 0x20008cc0
|
|
|
- 801097c: 40029000 .word 0x40029000
|
|
|
+ 80108e8: 4b02 ldr r3, [pc, #8] ; (80108f4 <ETH_DMATxDescChainInit+0x40>)
|
|
|
+ 80108ea: 6118 str r0, [r3, #16]
|
|
|
+ 80108ec: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 80108ee: bf00 nop
|
|
|
+ 80108f0: 20008afc .word 0x20008afc
|
|
|
+ 80108f4: 40029000 .word 0x40029000
|
|
|
|
|
|
-08010980 <ETH_DMATxDescChecksumInsertionConfig>:
|
|
|
+080108f8 <ETH_DMATxDescChecksumInsertionConfig>:
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
|
|
|
|
|
|
/* Set the selected DMA Tx desc checksum insertion control */
|
|
|
DMATxDesc->Status |= DMATxDesc_Checksum;
|
|
|
- 8010980: 6803 ldr r3, [r0, #0]
|
|
|
- 8010982: 4319 orrs r1, r3
|
|
|
- 8010984: 6001 str r1, [r0, #0]
|
|
|
- 8010986: 4770 bx lr
|
|
|
+ 80108f8: 6803 ldr r3, [r0, #0]
|
|
|
+ 80108fa: 4319 orrs r1, r3
|
|
|
+ 80108fc: 6001 str r1, [r0, #0]
|
|
|
+ 80108fe: 4770 bx lr
|
|
|
|
|
|
-08010988 <ETH_SoftwareReset>:
|
|
|
+08010900 <ETH_SoftwareReset>:
|
|
|
*/
|
|
|
void ETH_SoftwareReset(void)
|
|
|
{
|
|
|
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
|
|
|
/* After reset all the registers holds their respective reset values */
|
|
|
ETH->DMABMR |= ETH_DMABMR_SR;
|
|
|
- 8010988: 4b02 ldr r3, [pc, #8] ; (8010994 <ETH_SoftwareReset+0xc>)
|
|
|
- 801098a: 681a ldr r2, [r3, #0]
|
|
|
- 801098c: f042 0201 orr.w r2, r2, #1
|
|
|
- 8010990: 601a str r2, [r3, #0]
|
|
|
- 8010992: 4770 bx lr
|
|
|
- 8010994: 40029000 .word 0x40029000
|
|
|
-
|
|
|
-08010998 <ETH_GetSoftwareResetStatus>:
|
|
|
+ 8010900: 4b02 ldr r3, [pc, #8] ; (801090c <ETH_SoftwareReset+0xc>)
|
|
|
+ 8010902: 681a ldr r2, [r3, #0]
|
|
|
+ 8010904: f042 0201 orr.w r2, r2, #1
|
|
|
+ 8010908: 601a str r2, [r3, #0]
|
|
|
+ 801090a: 4770 bx lr
|
|
|
+ 801090c: 40029000 .word 0x40029000
|
|
|
+
|
|
|
+08010910 <ETH_GetSoftwareResetStatus>:
|
|
|
* @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
|
|
|
*/
|
|
|
FlagStatus ETH_GetSoftwareResetStatus(void)
|
|
|
{
|
|
|
FlagStatus bitstatus = RESET;
|
|
|
if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
|
|
|
- 8010998: 4b02 ldr r3, [pc, #8] ; (80109a4 <ETH_GetSoftwareResetStatus+0xc>)
|
|
|
- 801099a: 6818 ldr r0, [r3, #0]
|
|
|
+ 8010910: 4b02 ldr r3, [pc, #8] ; (801091c <ETH_GetSoftwareResetStatus+0xc>)
|
|
|
+ 8010912: 6818 ldr r0, [r3, #0]
|
|
|
else
|
|
|
{
|
|
|
bitstatus = RESET;
|
|
|
}
|
|
|
return bitstatus;
|
|
|
}
|
|
|
- 801099c: f000 0001 and.w r0, r0, #1
|
|
|
- 80109a0: 4770 bx lr
|
|
|
- 80109a2: bf00 nop
|
|
|
- 80109a4: 40029000 .word 0x40029000
|
|
|
+ 8010914: f000 0001 and.w r0, r0, #1
|
|
|
+ 8010918: 4770 bx lr
|
|
|
+ 801091a: bf00 nop
|
|
|
+ 801091c: 40029000 .word 0x40029000
|
|
|
|
|
|
-080109a8 <ETH_DMAITConfig>:
|
|
|
+08010920 <ETH_DMAITConfig>:
|
|
|
* @param NewState: new state of the specified ETHERNET DMA interrupts.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
|
|
|
{
|
|
|
- 80109a8: 4b04 ldr r3, [pc, #16] ; (80109bc <ETH_DMAITConfig+0x14>)
|
|
|
+ 8010920: 4b04 ldr r3, [pc, #16] ; (8010934 <ETH_DMAITConfig+0x14>)
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the selected ETHERNET DMA interrupts */
|
|
|
ETH->DMAIER |= ETH_DMA_IT;
|
|
|
- 80109aa: 69da ldr r2, [r3, #28]
|
|
|
+ 8010922: 69da ldr r2, [r3, #28]
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
- 80109ac: b109 cbz r1, 80109b2 <ETH_DMAITConfig+0xa>
|
|
|
+ 8010924: b109 cbz r1, 801092a <ETH_DMAITConfig+0xa>
|
|
|
{
|
|
|
/* Enable the selected ETHERNET DMA interrupts */
|
|
|
ETH->DMAIER |= ETH_DMA_IT;
|
|
|
- 80109ae: 4310 orrs r0, r2
|
|
|
- 80109b0: e001 b.n 80109b6 <ETH_DMAITConfig+0xe>
|
|
|
+ 8010926: 4310 orrs r0, r2
|
|
|
+ 8010928: e001 b.n 801092e <ETH_DMAITConfig+0xe>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the selected ETHERNET DMA interrupts */
|
|
|
ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
|
|
|
- 80109b2: ea22 0000 bic.w r0, r2, r0
|
|
|
- 80109b6: 61d8 str r0, [r3, #28]
|
|
|
- 80109b8: 4770 bx lr
|
|
|
- 80109ba: bf00 nop
|
|
|
- 80109bc: 40029000 .word 0x40029000
|
|
|
+ 801092a: ea22 0000 bic.w r0, r2, r0
|
|
|
+ 801092e: 61d8 str r0, [r3, #28]
|
|
|
+ 8010930: 4770 bx lr
|
|
|
+ 8010932: bf00 nop
|
|
|
+ 8010934: 40029000 .word 0x40029000
|
|
|
|
|
|
-080109c0 <ETH_FlushTransmitFIFO>:
|
|
|
+08010938 <ETH_FlushTransmitFIFO>:
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_FlushTransmitFIFO(void)
|
|
|
{
|
|
|
/* Set the Flush Transmit FIFO bit */
|
|
|
ETH->DMAOMR |= ETH_DMAOMR_FTF;
|
|
|
- 80109c0: 4b02 ldr r3, [pc, #8] ; (80109cc <ETH_FlushTransmitFIFO+0xc>)
|
|
|
- 80109c2: 699a ldr r2, [r3, #24]
|
|
|
- 80109c4: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
|
- 80109c8: 619a str r2, [r3, #24]
|
|
|
- 80109ca: 4770 bx lr
|
|
|
- 80109cc: 40029000 .word 0x40029000
|
|
|
-
|
|
|
-080109d0 <ETH_DMATransmissionCmd>:
|
|
|
+ 8010938: 4b02 ldr r3, [pc, #8] ; (8010944 <ETH_FlushTransmitFIFO+0xc>)
|
|
|
+ 801093a: 699a ldr r2, [r3, #24]
|
|
|
+ 801093c: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
|
+ 8010940: 619a str r2, [r3, #24]
|
|
|
+ 8010942: 4770 bx lr
|
|
|
+ 8010944: 40029000 .word 0x40029000
|
|
|
+
|
|
|
+08010948 <ETH_DMATransmissionCmd>:
|
|
|
* @param NewState: new state of the DMA transmission.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMATransmissionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
- 80109d0: 4b04 ldr r3, [pc, #16] ; (80109e4 <ETH_DMATransmissionCmd+0x14>)
|
|
|
+ 8010948: 4b04 ldr r3, [pc, #16] ; (801095c <ETH_DMATransmissionCmd+0x14>)
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the DMA transmission */
|
|
|
ETH->DMAOMR |= ETH_DMAOMR_ST;
|
|
|
- 80109d2: 699a ldr r2, [r3, #24]
|
|
|
+ 801094a: 699a ldr r2, [r3, #24]
|
|
|
void ETH_DMATransmissionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
- 80109d4: b110 cbz r0, 80109dc <ETH_DMATransmissionCmd+0xc>
|
|
|
+ 801094c: b110 cbz r0, 8010954 <ETH_DMATransmissionCmd+0xc>
|
|
|
{
|
|
|
/* Enable the DMA transmission */
|
|
|
ETH->DMAOMR |= ETH_DMAOMR_ST;
|
|
|
- 80109d6: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
|
- 80109da: e001 b.n 80109e0 <ETH_DMATransmissionCmd+0x10>
|
|
|
+ 801094e: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
|
+ 8010952: e001 b.n 8010958 <ETH_DMATransmissionCmd+0x10>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the DMA transmission */
|
|
|
ETH->DMAOMR &= ~ETH_DMAOMR_ST;
|
|
|
- 80109dc: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
|
- 80109e0: 619a str r2, [r3, #24]
|
|
|
- 80109e2: 4770 bx lr
|
|
|
- 80109e4: 40029000 .word 0x40029000
|
|
|
+ 8010954: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
|
+ 8010958: 619a str r2, [r3, #24]
|
|
|
+ 801095a: 4770 bx lr
|
|
|
+ 801095c: 40029000 .word 0x40029000
|
|
|
|
|
|
-080109e8 <ETH_DMAReceptionCmd>:
|
|
|
+08010960 <ETH_DMAReceptionCmd>:
|
|
|
* @param NewState: new state of the DMA reception.
|
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_DMAReceptionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
- 80109e8: 4b04 ldr r3, [pc, #16] ; (80109fc <ETH_DMAReceptionCmd+0x14>)
|
|
|
+ 8010960: 4b04 ldr r3, [pc, #16] ; (8010974 <ETH_DMAReceptionCmd+0x14>)
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
{
|
|
|
/* Enable the DMA reception */
|
|
|
ETH->DMAOMR |= ETH_DMAOMR_SR;
|
|
|
- 80109ea: 699a ldr r2, [r3, #24]
|
|
|
+ 8010962: 699a ldr r2, [r3, #24]
|
|
|
void ETH_DMAReceptionCmd(FunctionalState NewState)
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
|
|
if (NewState != DISABLE)
|
|
|
- 80109ec: b110 cbz r0, 80109f4 <ETH_DMAReceptionCmd+0xc>
|
|
|
+ 8010964: b110 cbz r0, 801096c <ETH_DMAReceptionCmd+0xc>
|
|
|
{
|
|
|
/* Enable the DMA reception */
|
|
|
ETH->DMAOMR |= ETH_DMAOMR_SR;
|
|
|
- 80109ee: f042 0202 orr.w r2, r2, #2
|
|
|
- 80109f2: e001 b.n 80109f8 <ETH_DMAReceptionCmd+0x10>
|
|
|
+ 8010966: f042 0202 orr.w r2, r2, #2
|
|
|
+ 801096a: e001 b.n 8010970 <ETH_DMAReceptionCmd+0x10>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the DMA reception */
|
|
|
ETH->DMAOMR &= ~ETH_DMAOMR_SR;
|
|
|
- 80109f4: f022 0202 bic.w r2, r2, #2
|
|
|
- 80109f8: 619a str r2, [r3, #24]
|
|
|
- 80109fa: 4770 bx lr
|
|
|
- 80109fc: 40029000 .word 0x40029000
|
|
|
+ 801096c: f022 0202 bic.w r2, r2, #2
|
|
|
+ 8010970: 619a str r2, [r3, #24]
|
|
|
+ 8010972: 4770 bx lr
|
|
|
+ 8010974: 40029000 .word 0x40029000
|
|
|
|
|
|
-08010a00 <ETH_Start>:
|
|
|
+08010978 <ETH_Start>:
|
|
|
* @brief Enables ENET MAC and DMA reception/transmission
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void ETH_Start(void)
|
|
|
{
|
|
|
- 8010a00: b508 push {r3, lr}
|
|
|
+ 8010978: b508 push {r3, lr}
|
|
|
/* Enable transmit state machine of the MAC for transmission on the MII */
|
|
|
ETH_MACTransmissionCmd(ENABLE);
|
|
|
- 8010a02: 2001 movs r0, #1
|
|
|
- 8010a04: f7ff fe8c bl 8010720 <ETH_MACTransmissionCmd>
|
|
|
+ 801097a: 2001 movs r0, #1
|
|
|
+ 801097c: f7ff fe8c bl 8010698 <ETH_MACTransmissionCmd>
|
|
|
/* Flush Transmit FIFO */
|
|
|
ETH_FlushTransmitFIFO();
|
|
|
- 8010a08: f7ff ffda bl 80109c0 <ETH_FlushTransmitFIFO>
|
|
|
+ 8010980: f7ff ffda bl 8010938 <ETH_FlushTransmitFIFO>
|
|
|
/* Enable receive state machine of the MAC for reception from the MII */
|
|
|
ETH_MACReceptionCmd(ENABLE);
|
|
|
- 8010a0c: 2001 movs r0, #1
|
|
|
- 8010a0e: f7ff fe93 bl 8010738 <ETH_MACReceptionCmd>
|
|
|
+ 8010984: 2001 movs r0, #1
|
|
|
+ 8010986: f7ff fe93 bl 80106b0 <ETH_MACReceptionCmd>
|
|
|
|
|
|
/* Start DMA transmission */
|
|
|
ETH_DMATransmissionCmd(ENABLE);
|
|
|
- 8010a12: 2001 movs r0, #1
|
|
|
- 8010a14: f7ff ffdc bl 80109d0 <ETH_DMATransmissionCmd>
|
|
|
+ 801098a: 2001 movs r0, #1
|
|
|
+ 801098c: f7ff ffdc bl 8010948 <ETH_DMATransmissionCmd>
|
|
|
/* Start DMA reception */
|
|
|
ETH_DMAReceptionCmd(ENABLE);
|
|
|
- 8010a18: 2001 movs r0, #1
|
|
|
+ 8010990: 2001 movs r0, #1
|
|
|
}
|
|
|
- 8010a1a: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
+ 8010992: e8bd 4008 ldmia.w sp!, {r3, lr}
|
|
|
ETH_MACReceptionCmd(ENABLE);
|
|
|
|
|
|
/* Start DMA transmission */
|
|
|
ETH_DMATransmissionCmd(ENABLE);
|
|
|
/* Start DMA reception */
|
|
|
ETH_DMAReceptionCmd(ENABLE);
|
|
|
- 8010a1e: f7ff bfe3 b.w 80109e8 <ETH_DMAReceptionCmd>
|
|
|
- 8010a22: 0000 movs r0, r0
|
|
|
+ 8010996: f7ff bfe3 b.w 8010960 <ETH_DMAReceptionCmd>
|
|
|
+ 801099a: 0000 movs r0, r0
|
|
|
|
|
|
-08010a24 <ETH_ReadPHYRegister>:
|
|
|
+0801099c <ETH_ReadPHYRegister>:
|
|
|
* @arg More PHY register could be read depending on the used PHY
|
|
|
* @retval ETH_ERROR: in case of timeout
|
|
|
* MAC MIIDR register value: Data read from the selected PHY register (correct read )
|
|
|
*/
|
|
|
uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
|
|
|
{
|
|
|
- 8010a24: b082 sub sp, #8
|
|
|
+ 801099c: b082 sub sp, #8
|
|
|
uint32_t tmpreg = 0;
|
|
|
__IO uint32_t timeout = 0;
|
|
|
- 8010a26: 2300 movs r3, #0
|
|
|
- 8010a28: 9301 str r3, [sp, #4]
|
|
|
+ 801099e: 2300 movs r3, #0
|
|
|
+ 80109a0: 9301 str r3, [sp, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
|
|
|
assert_param(IS_ETH_PHY_REG(PHYReg));
|
|
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010a2a: 4b11 ldr r3, [pc, #68] ; (8010a70 <ETH_ReadPHYRegister+0x4c>)
|
|
|
- 8010a2c: 691a ldr r2, [r3, #16]
|
|
|
+ 80109a2: 4b11 ldr r3, [pc, #68] ; (80109e8 <ETH_ReadPHYRegister+0x4c>)
|
|
|
+ 80109a4: 691a ldr r2, [r3, #16]
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
|
tmpreg &= ~MACMIIAR_CR_MASK;
|
|
|
/* Prepare the MII address register value */
|
|
|
tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
|
- 8010a2e: 06c0 lsls r0, r0, #27
|
|
|
+ 80109a6: 06c0 lsls r0, r0, #27
|
|
|
assert_param(IS_ETH_PHY_REG(PHYReg));
|
|
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
|
tmpreg &= ~MACMIIAR_CR_MASK;
|
|
|
- 8010a30: f002 021c and.w r2, r2, #28
|
|
|
+ 80109a8: f002 021c and.w r2, r2, #28
|
|
|
/* Prepare the MII address register value */
|
|
|
tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
|
- 8010a34: 0189 lsls r1, r1, #6
|
|
|
+ 80109ac: 0189 lsls r1, r1, #6
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
|
tmpreg &= ~MACMIIAR_CR_MASK;
|
|
|
/* Prepare the MII address register value */
|
|
|
tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
|
- 8010a36: ea42 4210 orr.w r2, r2, r0, lsr #16
|
|
|
+ 80109ae: ea42 4210 orr.w r2, r2, r0, lsr #16
|
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
|
- 8010a3a: f401 61f8 and.w r1, r1, #1984 ; 0x7c0
|
|
|
+ 80109b2: f401 61f8 and.w r1, r1, #1984 ; 0x7c0
|
|
|
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
|
|
|
- 8010a3e: 430a orrs r2, r1
|
|
|
+ 80109b6: 430a orrs r2, r1
|
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
|
- 8010a40: f042 0201 orr.w r2, r2, #1
|
|
|
+ 80109b8: f042 0201 orr.w r2, r2, #1
|
|
|
/* Write the result value into the MII Address register */
|
|
|
ETH->MACMIIAR = tmpreg;
|
|
|
- 8010a44: 611a str r2, [r3, #16]
|
|
|
+ 80109bc: 611a str r2, [r3, #16]
|
|
|
/* Check for the Busy flag */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010a46: 4a0b ldr r2, [pc, #44] ; (8010a74 <ETH_ReadPHYRegister+0x50>)
|
|
|
+ 80109be: 4a0b ldr r2, [pc, #44] ; (80109ec <ETH_ReadPHYRegister+0x50>)
|
|
|
/* Write the result value into the MII Address register */
|
|
|
ETH->MACMIIAR = tmpreg;
|
|
|
/* Check for the Busy flag */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010a48: 9901 ldr r1, [sp, #4]
|
|
|
- 8010a4a: 3101 adds r1, #1
|
|
|
- 8010a4c: 9101 str r1, [sp, #4]
|
|
|
+ 80109c0: 9901 ldr r1, [sp, #4]
|
|
|
+ 80109c2: 3101 adds r1, #1
|
|
|
+ 80109c4: 9101 str r1, [sp, #4]
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010a4e: 6919 ldr r1, [r3, #16]
|
|
|
+ 80109c6: 6919 ldr r1, [r3, #16]
|
|
|
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010a50: 07c9 lsls r1, r1, #31
|
|
|
- 8010a52: d502 bpl.n 8010a5a <ETH_ReadPHYRegister+0x36>
|
|
|
- 8010a54: 9901 ldr r1, [sp, #4]
|
|
|
- 8010a56: 4291 cmp r1, r2
|
|
|
- 8010a58: d9f6 bls.n 8010a48 <ETH_ReadPHYRegister+0x24>
|
|
|
+ 80109c8: 07c9 lsls r1, r1, #31
|
|
|
+ 80109ca: d502 bpl.n 80109d2 <ETH_ReadPHYRegister+0x36>
|
|
|
+ 80109cc: 9901 ldr r1, [sp, #4]
|
|
|
+ 80109ce: 4291 cmp r1, r2
|
|
|
+ 80109d0: d9f6 bls.n 80109c0 <ETH_ReadPHYRegister+0x24>
|
|
|
/* Return ERROR in case of timeout */
|
|
|
if(timeout == PHY_READ_TO)
|
|
|
- 8010a5a: 4b07 ldr r3, [pc, #28] ; (8010a78 <ETH_ReadPHYRegister+0x54>)
|
|
|
- 8010a5c: 9a01 ldr r2, [sp, #4]
|
|
|
- 8010a5e: 429a cmp r2, r3
|
|
|
+ 80109d2: 4b07 ldr r3, [pc, #28] ; (80109f0 <ETH_ReadPHYRegister+0x54>)
|
|
|
+ 80109d4: 9a01 ldr r2, [sp, #4]
|
|
|
+ 80109d6: 429a cmp r2, r3
|
|
|
{
|
|
|
return (uint16_t)ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Return data register value */
|
|
|
return (uint16_t)(ETH->MACMIIDR);
|
|
|
- 8010a60: bf1d ittte ne
|
|
|
- 8010a62: 4b03 ldrne r3, [pc, #12] ; (8010a70 <ETH_ReadPHYRegister+0x4c>)
|
|
|
- 8010a64: 6958 ldrne r0, [r3, #20]
|
|
|
- 8010a66: b280 uxthne r0, r0
|
|
|
+ 80109d8: bf1d ittte ne
|
|
|
+ 80109da: 4b03 ldrne r3, [pc, #12] ; (80109e8 <ETH_ReadPHYRegister+0x4c>)
|
|
|
+ 80109dc: 6958 ldrne r0, [r3, #20]
|
|
|
+ 80109de: b280 uxthne r0, r0
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
/* Return ERROR in case of timeout */
|
|
|
if(timeout == PHY_READ_TO)
|
|
|
{
|
|
|
return (uint16_t)ETH_ERROR;
|
|
|
- 8010a68: 2000 moveq r0, #0
|
|
|
+ 80109e0: 2000 moveq r0, #0
|
|
|
}
|
|
|
|
|
|
/* Return data register value */
|
|
|
return (uint16_t)(ETH->MACMIIDR);
|
|
|
}
|
|
|
- 8010a6a: b002 add sp, #8
|
|
|
- 8010a6c: 4770 bx lr
|
|
|
- 8010a6e: bf00 nop
|
|
|
- 8010a70: 40028000 .word 0x40028000
|
|
|
- 8010a74: 0004fffe .word 0x0004fffe
|
|
|
- 8010a78: 0004ffff .word 0x0004ffff
|
|
|
-
|
|
|
-08010a7c <ETH_WritePHYRegister>:
|
|
|
+ 80109e2: b002 add sp, #8
|
|
|
+ 80109e4: 4770 bx lr
|
|
|
+ 80109e6: bf00 nop
|
|
|
+ 80109e8: 40028000 .word 0x40028000
|
|
|
+ 80109ec: 0004fffe .word 0x0004fffe
|
|
|
+ 80109f0: 0004ffff .word 0x0004ffff
|
|
|
+
|
|
|
+080109f4 <ETH_WritePHYRegister>:
|
|
|
* @param PHYValue: the value to write
|
|
|
* @retval ETH_ERROR: in case of timeout
|
|
|
* ETH_SUCCESS: for correct write
|
|
|
*/
|
|
|
uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
|
|
|
{
|
|
|
- 8010a7c: b513 push {r0, r1, r4, lr}
|
|
|
+ 80109f4: b513 push {r0, r1, r4, lr}
|
|
|
uint32_t tmpreg = 0;
|
|
|
__IO uint32_t timeout = 0;
|
|
|
- 8010a7e: 2300 movs r3, #0
|
|
|
- 8010a80: 9301 str r3, [sp, #4]
|
|
|
+ 80109f6: 2300 movs r3, #0
|
|
|
+ 80109f8: 9301 str r3, [sp, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
|
|
|
assert_param(IS_ETH_PHY_REG(PHYReg));
|
|
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010a82: 4b0f ldr r3, [pc, #60] ; (8010ac0 <ETH_WritePHYRegister+0x44>)
|
|
|
- 8010a84: 691c ldr r4, [r3, #16]
|
|
|
+ 80109fa: 4b0f ldr r3, [pc, #60] ; (8010a38 <ETH_WritePHYRegister+0x44>)
|
|
|
+ 80109fc: 691c ldr r4, [r3, #16]
|
|
|
tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
|
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
|
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
|
/* Give the value to the MII data register */
|
|
|
ETH->MACMIIDR = PHYValue;
|
|
|
- 8010a86: 615a str r2, [r3, #20]
|
|
|
+ 80109fe: 615a str r2, [r3, #20]
|
|
|
assert_param(IS_ETH_PHY_REG(PHYReg));
|
|
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
|
tmpreg &= ~MACMIIAR_CR_MASK;
|
|
|
- 8010a88: f004 041c and.w r4, r4, #28
|
|
|
+ 8010a00: f004 041c and.w r4, r4, #28
|
|
|
/* Prepare the MII register address value */
|
|
|
tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
|
- 8010a8c: f044 0403 orr.w r4, r4, #3
|
|
|
- 8010a90: 06c0 lsls r0, r0, #27
|
|
|
+ 8010a04: f044 0403 orr.w r4, r4, #3
|
|
|
+ 8010a08: 06c0 lsls r0, r0, #27
|
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
|
- 8010a92: 0189 lsls r1, r1, #6
|
|
|
- 8010a94: ea44 4410 orr.w r4, r4, r0, lsr #16
|
|
|
- 8010a98: f401 61f8 and.w r1, r1, #1984 ; 0x7c0
|
|
|
+ 8010a0a: 0189 lsls r1, r1, #6
|
|
|
+ 8010a0c: ea44 4410 orr.w r4, r4, r0, lsr #16
|
|
|
+ 8010a10: f401 61f8 and.w r1, r1, #1984 ; 0x7c0
|
|
|
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
|
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
|
- 8010a9c: 430c orrs r4, r1
|
|
|
+ 8010a14: 430c orrs r4, r1
|
|
|
/* Check for the Busy flag */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
|
|
|
- 8010a9e: 4a09 ldr r2, [pc, #36] ; (8010ac4 <ETH_WritePHYRegister+0x48>)
|
|
|
+ 8010a16: 4a09 ldr r2, [pc, #36] ; (8010a3c <ETH_WritePHYRegister+0x48>)
|
|
|
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
|
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
|
/* Give the value to the MII data register */
|
|
|
ETH->MACMIIDR = PHYValue;
|
|
|
/* Write the result value into the MII Address register */
|
|
|
ETH->MACMIIAR = tmpreg;
|
|
|
- 8010aa0: 611c str r4, [r3, #16]
|
|
|
+ 8010a18: 611c str r4, [r3, #16]
|
|
|
/* Check for the Busy flag */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010aa2: 9901 ldr r1, [sp, #4]
|
|
|
- 8010aa4: 3101 adds r1, #1
|
|
|
- 8010aa6: 9101 str r1, [sp, #4]
|
|
|
+ 8010a1a: 9901 ldr r1, [sp, #4]
|
|
|
+ 8010a1c: 3101 adds r1, #1
|
|
|
+ 8010a1e: 9101 str r1, [sp, #4]
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010aa8: 6919 ldr r1, [r3, #16]
|
|
|
+ 8010a20: 6919 ldr r1, [r3, #16]
|
|
|
} while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
|
|
|
- 8010aaa: 07c8 lsls r0, r1, #31
|
|
|
- 8010aac: d502 bpl.n 8010ab4 <ETH_WritePHYRegister+0x38>
|
|
|
- 8010aae: 9901 ldr r1, [sp, #4]
|
|
|
- 8010ab0: 4291 cmp r1, r2
|
|
|
- 8010ab2: d9f6 bls.n 8010aa2 <ETH_WritePHYRegister+0x26>
|
|
|
+ 8010a22: 07c8 lsls r0, r1, #31
|
|
|
+ 8010a24: d502 bpl.n 8010a2c <ETH_WritePHYRegister+0x38>
|
|
|
+ 8010a26: 9901 ldr r1, [sp, #4]
|
|
|
+ 8010a28: 4291 cmp r1, r2
|
|
|
+ 8010a2a: d9f6 bls.n 8010a1a <ETH_WritePHYRegister+0x26>
|
|
|
/* Return ERROR in case of timeout */
|
|
|
if(timeout == PHY_WRITE_TO)
|
|
|
- 8010ab4: 9801 ldr r0, [sp, #4]
|
|
|
+ 8010a2c: 9801 ldr r0, [sp, #4]
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Return SUCCESS */
|
|
|
return ETH_SUCCESS;
|
|
|
}
|
|
|
- 8010ab6: 4b04 ldr r3, [pc, #16] ; (8010ac8 <ETH_WritePHYRegister+0x4c>)
|
|
|
- 8010ab8: 1ac0 subs r0, r0, r3
|
|
|
- 8010aba: bf18 it ne
|
|
|
- 8010abc: 2001 movne r0, #1
|
|
|
- 8010abe: bd1c pop {r2, r3, r4, pc}
|
|
|
- 8010ac0: 40028000 .word 0x40028000
|
|
|
- 8010ac4: 0004fffe .word 0x0004fffe
|
|
|
- 8010ac8: 0004ffff .word 0x0004ffff
|
|
|
-
|
|
|
-08010acc <ETH_Init>:
|
|
|
+ 8010a2e: 4b04 ldr r3, [pc, #16] ; (8010a40 <ETH_WritePHYRegister+0x4c>)
|
|
|
+ 8010a30: 1ac0 subs r0, r0, r3
|
|
|
+ 8010a32: bf18 it ne
|
|
|
+ 8010a34: 2001 movne r0, #1
|
|
|
+ 8010a36: bd1c pop {r2, r3, r4, pc}
|
|
|
+ 8010a38: 40028000 .word 0x40028000
|
|
|
+ 8010a3c: 0004fffe .word 0x0004fffe
|
|
|
+ 8010a40: 0004ffff .word 0x0004ffff
|
|
|
+
|
|
|
+08010a44 <ETH_Init>:
|
|
|
* @param PHYAddress: external PHY address
|
|
|
* @retval ETH_ERROR: Ethernet initialization failed
|
|
|
* ETH_SUCCESS: Ethernet successfully initialized
|
|
|
*/
|
|
|
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
|
|
|
{
|
|
|
- 8010acc: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
- 8010ace: b087 sub sp, #28
|
|
|
+ 8010a44: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
+ 8010a46: b087 sub sp, #28
|
|
|
uint32_t RegValue = 0, tmpreg = 0;
|
|
|
__IO uint32_t i = 0;
|
|
|
- 8010ad0: 2300 movs r3, #0
|
|
|
+ 8010a48: 2300 movs r3, #0
|
|
|
assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
|
|
|
assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
|
|
|
/*-------------------------------- MAC Config ------------------------------*/
|
|
|
/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010ad2: 4f90 ldr r7, [pc, #576] ; (8010d14 <ETH_Init+0x248>)
|
|
|
+ 8010a4a: 4f90 ldr r7, [pc, #576] ; (8010c8c <ETH_Init+0x248>)
|
|
|
* ETH_SUCCESS: Ethernet successfully initialized
|
|
|
*/
|
|
|
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
|
|
|
{
|
|
|
uint32_t RegValue = 0, tmpreg = 0;
|
|
|
__IO uint32_t i = 0;
|
|
|
- 8010ad4: 9300 str r3, [sp, #0]
|
|
|
+ 8010a4c: 9300 str r3, [sp, #0]
|
|
|
* @param PHYAddress: external PHY address
|
|
|
* @retval ETH_ERROR: Ethernet initialization failed
|
|
|
* ETH_SUCCESS: Ethernet successfully initialized
|
|
|
*/
|
|
|
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
|
|
|
{
|
|
|
- 8010ad6: 4604 mov r4, r0
|
|
|
+ 8010a4e: 4604 mov r4, r0
|
|
|
uint32_t RegValue = 0, tmpreg = 0;
|
|
|
__IO uint32_t i = 0;
|
|
|
RCC_ClocksTypeDef rcc_clocks;
|
|
|
uint32_t hclk = 60000000;
|
|
|
__IO uint32_t timeout = 0;
|
|
|
- 8010ad8: 9301 str r3, [sp, #4]
|
|
|
+ 8010a50: 9301 str r3, [sp, #4]
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
/* Clear CSR Clock Range CR[2:0] bits */
|
|
|
tmpreg &= MACMIIAR_CR_MASK;
|
|
|
/* Get hclk frequency value */
|
|
|
RCC_GetClocksFreq(&rcc_clocks);
|
|
|
- 8010ada: a802 add r0, sp, #8
|
|
|
+ 8010a52: a802 add r0, sp, #8
|
|
|
* @param PHYAddress: external PHY address
|
|
|
* @retval ETH_ERROR: Ethernet initialization failed
|
|
|
* ETH_SUCCESS: Ethernet successfully initialized
|
|
|
*/
|
|
|
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
|
|
|
{
|
|
|
- 8010adc: 460e mov r6, r1
|
|
|
+ 8010a54: 460e mov r6, r1
|
|
|
assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
|
|
|
assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
|
|
|
/*-------------------------------- MAC Config ------------------------------*/
|
|
|
/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
- 8010ade: 693d ldr r5, [r7, #16]
|
|
|
+ 8010a56: 693d ldr r5, [r7, #16]
|
|
|
/* Clear CSR Clock Range CR[2:0] bits */
|
|
|
tmpreg &= MACMIIAR_CR_MASK;
|
|
|
/* Get hclk frequency value */
|
|
|
RCC_GetClocksFreq(&rcc_clocks);
|
|
|
- 8010ae0: f7f9 fa12 bl 8009f08 <RCC_GetClocksFreq>
|
|
|
+ 8010a58: f7f9 fa56 bl 8009f08 <RCC_GetClocksFreq>
|
|
|
hclk = rcc_clocks.HCLK_Frequency;
|
|
|
- 8010ae4: 9b03 ldr r3, [sp, #12]
|
|
|
+ 8010a5c: 9b03 ldr r3, [sp, #12]
|
|
|
|
|
|
/* Set CR bits depending on hclk value */
|
|
|
if((hclk >= 20000000)&&(hclk < 35000000))
|
|
|
- 8010ae6: 4a8c ldr r2, [pc, #560] ; (8010d18 <ETH_Init+0x24c>)
|
|
|
- 8010ae8: 498c ldr r1, [pc, #560] ; (8010d1c <ETH_Init+0x250>)
|
|
|
- 8010aea: 189a adds r2, r3, r2
|
|
|
- 8010aec: 428a cmp r2, r1
|
|
|
+ 8010a5e: 4a8c ldr r2, [pc, #560] ; (8010c90 <ETH_Init+0x24c>)
|
|
|
+ 8010a60: 498c ldr r1, [pc, #560] ; (8010c94 <ETH_Init+0x250>)
|
|
|
+ 8010a62: 189a adds r2, r3, r2
|
|
|
+ 8010a64: 428a cmp r2, r1
|
|
|
/*-------------------------------- MAC Config ------------------------------*/
|
|
|
/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
|
tmpreg = ETH->MACMIIAR;
|
|
|
/* Clear CSR Clock Range CR[2:0] bits */
|
|
|
tmpreg &= MACMIIAR_CR_MASK;
|
|
|
- 8010aee: f025 051c bic.w r5, r5, #28
|
|
|
+ 8010a66: f025 051c bic.w r5, r5, #28
|
|
|
/* Get hclk frequency value */
|
|
|
RCC_GetClocksFreq(&rcc_clocks);
|
|
|
hclk = rcc_clocks.HCLK_Frequency;
|
|
|
|
|
|
/* Set CR bits depending on hclk value */
|
|
|
if((hclk >= 20000000)&&(hclk < 35000000))
|
|
|
- 8010af2: d802 bhi.n 8010afa <ETH_Init+0x2e>
|
|
|
+ 8010a6a: d802 bhi.n 8010a72 <ETH_Init+0x2e>
|
|
|
{
|
|
|
/* CSR Clock Range between 20-35 MHz */
|
|
|
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
|
|
|
- 8010af4: f045 0508 orr.w r5, r5, #8
|
|
|
- 8010af8: e015 b.n 8010b26 <ETH_Init+0x5a>
|
|
|
+ 8010a6c: f045 0508 orr.w r5, r5, #8
|
|
|
+ 8010a70: e015 b.n 8010a9e <ETH_Init+0x5a>
|
|
|
}
|
|
|
else if((hclk >= 35000000)&&(hclk < 60000000))
|
|
|
- 8010afa: 4a89 ldr r2, [pc, #548] ; (8010d20 <ETH_Init+0x254>)
|
|
|
- 8010afc: 4989 ldr r1, [pc, #548] ; (8010d24 <ETH_Init+0x258>)
|
|
|
- 8010afe: 189a adds r2, r3, r2
|
|
|
- 8010b00: 428a cmp r2, r1
|
|
|
- 8010b02: d802 bhi.n 8010b0a <ETH_Init+0x3e>
|
|
|
+ 8010a72: 4a89 ldr r2, [pc, #548] ; (8010c98 <ETH_Init+0x254>)
|
|
|
+ 8010a74: 4989 ldr r1, [pc, #548] ; (8010c9c <ETH_Init+0x258>)
|
|
|
+ 8010a76: 189a adds r2, r3, r2
|
|
|
+ 8010a78: 428a cmp r2, r1
|
|
|
+ 8010a7a: d802 bhi.n 8010a82 <ETH_Init+0x3e>
|
|
|
{
|
|
|
/* CSR Clock Range between 35-60 MHz */
|
|
|
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
|
|
|
- 8010b04: f045 050c orr.w r5, r5, #12
|
|
|
- 8010b08: e00d b.n 8010b26 <ETH_Init+0x5a>
|
|
|
+ 8010a7c: f045 050c orr.w r5, r5, #12
|
|
|
+ 8010a80: e00d b.n 8010a9e <ETH_Init+0x5a>
|
|
|
}
|
|
|
else if((hclk >= 60000000)&&(hclk < 100000000))
|
|
|
- 8010b0a: 4a87 ldr r2, [pc, #540] ; (8010d28 <ETH_Init+0x25c>)
|
|
|
- 8010b0c: 4987 ldr r1, [pc, #540] ; (8010d2c <ETH_Init+0x260>)
|
|
|
- 8010b0e: 189a adds r2, r3, r2
|
|
|
- 8010b10: 428a cmp r2, r1
|
|
|
- 8010b12: d908 bls.n 8010b26 <ETH_Init+0x5a>
|
|
|
+ 8010a82: 4a87 ldr r2, [pc, #540] ; (8010ca0 <ETH_Init+0x25c>)
|
|
|
+ 8010a84: 4987 ldr r1, [pc, #540] ; (8010ca4 <ETH_Init+0x260>)
|
|
|
+ 8010a86: 189a adds r2, r3, r2
|
|
|
+ 8010a88: 428a cmp r2, r1
|
|
|
+ 8010a8a: d908 bls.n 8010a9e <ETH_Init+0x5a>
|
|
|
{
|
|
|
/* CSR Clock Range between 60-100 MHz */
|
|
|
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
|
|
|
}
|
|
|
else if((hclk >= 100000000)&&(hclk < 150000000))
|
|
|
- 8010b14: 4a86 ldr r2, [pc, #536] ; (8010d30 <ETH_Init+0x264>)
|
|
|
- 8010b16: 189a adds r2, r3, r2
|
|
|
- 8010b18: 4b86 ldr r3, [pc, #536] ; (8010d34 <ETH_Init+0x268>)
|
|
|
- 8010b1a: 429a cmp r2, r3
|
|
|
+ 8010a8c: 4a86 ldr r2, [pc, #536] ; (8010ca8 <ETH_Init+0x264>)
|
|
|
+ 8010a8e: 189a adds r2, r3, r2
|
|
|
+ 8010a90: 4b86 ldr r3, [pc, #536] ; (8010cac <ETH_Init+0x268>)
|
|
|
+ 8010a92: 429a cmp r2, r3
|
|
|
{
|
|
|
/* CSR Clock Range between 100-150 MHz */
|
|
|
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
|
|
|
- 8010b1c: bf94 ite ls
|
|
|
- 8010b1e: f045 0504 orrls.w r5, r5, #4
|
|
|
+ 8010a94: bf94 ite ls
|
|
|
+ 8010a96: f045 0504 orrls.w r5, r5, #4
|
|
|
}
|
|
|
else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
|
|
|
{
|
|
|
/* CSR Clock Range between 150-168 MHz */
|
|
|
tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
|
|
|
- 8010b22: f045 0510 orrhi.w r5, r5, #16
|
|
|
+ 8010a9a: f045 0510 orrhi.w r5, r5, #16
|
|
|
}
|
|
|
|
|
|
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
|
|
|
ETH->MACMIIAR = (uint32_t)tmpreg;
|
|
|
- 8010b26: 613d str r5, [r7, #16]
|
|
|
+ 8010a9e: 613d str r5, [r7, #16]
|
|
|
/*-------------------- PHY initialization and configuration ----------------*/
|
|
|
/* Put the PHY in reset mode */
|
|
|
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
|
|
|
- 8010b28: 4630 mov r0, r6
|
|
|
- 8010b2a: 2100 movs r1, #0
|
|
|
- 8010b2c: f44f 4200 mov.w r2, #32768 ; 0x8000
|
|
|
- 8010b30: f7ff ffa4 bl 8010a7c <ETH_WritePHYRegister>
|
|
|
- 8010b34: b908 cbnz r0, 8010b3a <ETH_Init+0x6e>
|
|
|
+ 8010aa0: 4630 mov r0, r6
|
|
|
+ 8010aa2: 2100 movs r1, #0
|
|
|
+ 8010aa4: f44f 4200 mov.w r2, #32768 ; 0x8000
|
|
|
+ 8010aa8: f7ff ffa4 bl 80109f4 <ETH_WritePHYRegister>
|
|
|
+ 8010aac: b908 cbnz r0, 8010ab2 <ETH_Init+0x6e>
|
|
|
{
|
|
|
/* Return ERROR in case of write timeout */
|
|
|
return ETH_ERROR;
|
|
|
- 8010b36: 2000 movs r0, #0
|
|
|
- 8010b38: e0e9 b.n 8010d0e <ETH_Init+0x242>
|
|
|
+ 8010aae: 2000 movs r0, #0
|
|
|
+ 8010ab0: e0e9 b.n 8010c86 <ETH_Init+0x242>
|
|
|
}
|
|
|
|
|
|
/* Delay to assure PHY reset */
|
|
|
_eth_delay_(PHY_RESET_DELAY);
|
|
|
- 8010b3a: 487f ldr r0, [pc, #508] ; (8010d38 <ETH_Init+0x26c>)
|
|
|
- 8010b3c: f7ff fd80 bl 8010640 <ETH_Delay>
|
|
|
+ 8010ab2: 487f ldr r0, [pc, #508] ; (8010cb0 <ETH_Init+0x26c>)
|
|
|
+ 8010ab4: f7ff fd80 bl 80105b8 <ETH_Delay>
|
|
|
|
|
|
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
|
|
|
- 8010b40: 6821 ldr r1, [r4, #0]
|
|
|
- 8010b42: 2900 cmp r1, #0
|
|
|
- 8010b44: d050 beq.n 8010be8 <ETH_Init+0x11c>
|
|
|
+ 8010ab8: 6821 ldr r1, [r4, #0]
|
|
|
+ 8010aba: 2900 cmp r1, #0
|
|
|
+ 8010abc: d050 beq.n 8010b60 <ETH_Init+0x11c>
|
|
|
{
|
|
|
/* We wait for linked status... */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
|
|
|
- 8010b46: 4d7d ldr r5, [pc, #500] ; (8010d3c <ETH_Init+0x270>)
|
|
|
+ 8010abe: 4d7d ldr r5, [pc, #500] ; (8010cb4 <ETH_Init+0x270>)
|
|
|
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
|
|
|
{
|
|
|
/* We wait for linked status... */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b48: 9b01 ldr r3, [sp, #4]
|
|
|
+ 8010ac0: 9b01 ldr r3, [sp, #4]
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
|
|
|
- 8010b4a: 4630 mov r0, r6
|
|
|
+ 8010ac2: 4630 mov r0, r6
|
|
|
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
|
|
|
{
|
|
|
/* We wait for linked status... */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b4c: 3301 adds r3, #1
|
|
|
+ 8010ac4: 3301 adds r3, #1
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
|
|
|
- 8010b4e: 2101 movs r1, #1
|
|
|
+ 8010ac6: 2101 movs r1, #1
|
|
|
if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
|
|
|
{
|
|
|
/* We wait for linked status... */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b50: 9301 str r3, [sp, #4]
|
|
|
+ 8010ac8: 9301 str r3, [sp, #4]
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
|
|
|
- 8010b52: f7ff ff67 bl 8010a24 <ETH_ReadPHYRegister>
|
|
|
- 8010b56: f000 0004 and.w r0, r0, #4
|
|
|
- 8010b5a: b280 uxth r0, r0
|
|
|
- 8010b5c: b910 cbnz r0, 8010b64 <ETH_Init+0x98>
|
|
|
- 8010b5e: 9b01 ldr r3, [sp, #4]
|
|
|
- 8010b60: 42ab cmp r3, r5
|
|
|
- 8010b62: d9f1 bls.n 8010b48 <ETH_Init+0x7c>
|
|
|
+ 8010aca: f7ff ff67 bl 801099c <ETH_ReadPHYRegister>
|
|
|
+ 8010ace: f000 0004 and.w r0, r0, #4
|
|
|
+ 8010ad2: b280 uxth r0, r0
|
|
|
+ 8010ad4: b910 cbnz r0, 8010adc <ETH_Init+0x98>
|
|
|
+ 8010ad6: 9b01 ldr r3, [sp, #4]
|
|
|
+ 8010ad8: 42ab cmp r3, r5
|
|
|
+ 8010ada: d9f1 bls.n 8010ac0 <ETH_Init+0x7c>
|
|
|
|
|
|
/* Return ERROR in case of timeout */
|
|
|
if(timeout == PHY_READ_TO)
|
|
|
- 8010b64: 9a01 ldr r2, [sp, #4]
|
|
|
- 8010b66: 4b76 ldr r3, [pc, #472] ; (8010d40 <ETH_Init+0x274>)
|
|
|
- 8010b68: 429a cmp r2, r3
|
|
|
- 8010b6a: d0e4 beq.n 8010b36 <ETH_Init+0x6a>
|
|
|
+ 8010adc: 9a01 ldr r2, [sp, #4]
|
|
|
+ 8010ade: 4b76 ldr r3, [pc, #472] ; (8010cb8 <ETH_Init+0x274>)
|
|
|
+ 8010ae0: 429a cmp r2, r3
|
|
|
+ 8010ae2: d0e4 beq.n 8010aae <ETH_Init+0x6a>
|
|
|
{
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Reset Timeout counter */
|
|
|
timeout = 0;
|
|
|
- 8010b6c: 2100 movs r1, #0
|
|
|
+ 8010ae4: 2100 movs r1, #0
|
|
|
/* Enable Auto-Negotiation */
|
|
|
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
|
|
|
- 8010b6e: 4630 mov r0, r6
|
|
|
- 8010b70: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
|
+ 8010ae6: 4630 mov r0, r6
|
|
|
+ 8010ae8: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
|
{
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Reset Timeout counter */
|
|
|
timeout = 0;
|
|
|
- 8010b74: 9101 str r1, [sp, #4]
|
|
|
+ 8010aec: 9101 str r1, [sp, #4]
|
|
|
/* Enable Auto-Negotiation */
|
|
|
if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
|
|
|
- 8010b76: f7ff ff81 bl 8010a7c <ETH_WritePHYRegister>
|
|
|
- 8010b7a: 2800 cmp r0, #0
|
|
|
- 8010b7c: d0db beq.n 8010b36 <ETH_Init+0x6a>
|
|
|
+ 8010aee: f7ff ff81 bl 80109f4 <ETH_WritePHYRegister>
|
|
|
+ 8010af2: 2800 cmp r0, #0
|
|
|
+ 8010af4: d0db beq.n 8010aae <ETH_Init+0x6a>
|
|
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010b7e: 4d6f ldr r5, [pc, #444] ; (8010d3c <ETH_Init+0x270>)
|
|
|
+ 8010af6: 4d6f ldr r5, [pc, #444] ; (8010cb4 <ETH_Init+0x270>)
|
|
|
}
|
|
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b80: 9b01 ldr r3, [sp, #4]
|
|
|
+ 8010af8: 9b01 ldr r3, [sp, #4]
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010b82: 4630 mov r0, r6
|
|
|
+ 8010afa: 4630 mov r0, r6
|
|
|
}
|
|
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b84: 3301 adds r3, #1
|
|
|
+ 8010afc: 3301 adds r3, #1
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010b86: 2101 movs r1, #1
|
|
|
+ 8010afe: 2101 movs r1, #1
|
|
|
}
|
|
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
|
do
|
|
|
{
|
|
|
timeout++;
|
|
|
- 8010b88: 9301 str r3, [sp, #4]
|
|
|
+ 8010b00: 9301 str r3, [sp, #4]
|
|
|
} while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
|
|
|
- 8010b8a: f7ff ff4b bl 8010a24 <ETH_ReadPHYRegister>
|
|
|
- 8010b8e: f000 0020 and.w r0, r0, #32
|
|
|
- 8010b92: b280 uxth r0, r0
|
|
|
- 8010b94: b910 cbnz r0, 8010b9c <ETH_Init+0xd0>
|
|
|
- 8010b96: 9b01 ldr r3, [sp, #4]
|
|
|
- 8010b98: 42ab cmp r3, r5
|
|
|
- 8010b9a: d9f1 bls.n 8010b80 <ETH_Init+0xb4>
|
|
|
+ 8010b02: f7ff ff4b bl 801099c <ETH_ReadPHYRegister>
|
|
|
+ 8010b06: f000 0020 and.w r0, r0, #32
|
|
|
+ 8010b0a: b280 uxth r0, r0
|
|
|
+ 8010b0c: b910 cbnz r0, 8010b14 <ETH_Init+0xd0>
|
|
|
+ 8010b0e: 9b01 ldr r3, [sp, #4]
|
|
|
+ 8010b10: 42ab cmp r3, r5
|
|
|
+ 8010b12: d9f1 bls.n 8010af8 <ETH_Init+0xb4>
|
|
|
|
|
|
/* Return ERROR in case of timeout */
|
|
|
if(timeout == PHY_READ_TO)
|
|
|
- 8010b9c: 9a01 ldr r2, [sp, #4]
|
|
|
- 8010b9e: 4b68 ldr r3, [pc, #416] ; (8010d40 <ETH_Init+0x274>)
|
|
|
- 8010ba0: 429a cmp r2, r3
|
|
|
- 8010ba2: d0c8 beq.n 8010b36 <ETH_Init+0x6a>
|
|
|
+ 8010b14: 9a01 ldr r2, [sp, #4]
|
|
|
+ 8010b16: 4b68 ldr r3, [pc, #416] ; (8010cb8 <ETH_Init+0x274>)
|
|
|
+ 8010b18: 429a cmp r2, r3
|
|
|
+ 8010b1a: d0c8 beq.n 8010aae <ETH_Init+0x6a>
|
|
|
{
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Reset Timeout counter */
|
|
|
timeout = 0;
|
|
|
- 8010ba4: 2500 movs r5, #0
|
|
|
+ 8010b1c: 2500 movs r5, #0
|
|
|
|
|
|
/* Read the result of the auto-negotiation */
|
|
|
RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
|
|
|
- 8010ba6: 211f movs r1, #31
|
|
|
- 8010ba8: 4630 mov r0, r6
|
|
|
+ 8010b1e: 211f movs r1, #31
|
|
|
+ 8010b20: 4630 mov r0, r6
|
|
|
{
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Reset Timeout counter */
|
|
|
timeout = 0;
|
|
|
- 8010baa: 9501 str r5, [sp, #4]
|
|
|
+ 8010b22: 9501 str r5, [sp, #4]
|
|
|
|
|
|
/* Read the result of the auto-negotiation */
|
|
|
RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
|
|
|
- 8010bac: f7ff ff3a bl 8010a24 <ETH_ReadPHYRegister>
|
|
|
+ 8010b24: f7ff ff3a bl 801099c <ETH_ReadPHYRegister>
|
|
|
|
|
|
switch (RegValue & PHY_DUPLEX_SPEED_STATUS_MASK)
|
|
|
- 8010bb0: f000 001c and.w r0, r0, #28
|
|
|
- 8010bb4: 2808 cmp r0, #8
|
|
|
- 8010bb6: d00b beq.n 8010bd0 <ETH_Init+0x104>
|
|
|
- 8010bb8: d802 bhi.n 8010bc0 <ETH_Init+0xf4>
|
|
|
- 8010bba: 2804 cmp r0, #4
|
|
|
- 8010bbc: d123 bne.n 8010c06 <ETH_Init+0x13a>
|
|
|
- 8010bbe: e010 b.n 8010be2 <ETH_Init+0x116>
|
|
|
- 8010bc0: 280e cmp r0, #14
|
|
|
- 8010bc2: d00a beq.n 8010bda <ETH_Init+0x10e>
|
|
|
- 8010bc4: 2812 cmp r0, #18
|
|
|
- 8010bc6: d11e bne.n 8010c06 <ETH_Init+0x13a>
|
|
|
+ 8010b28: f000 001c and.w r0, r0, #28
|
|
|
+ 8010b2c: 2808 cmp r0, #8
|
|
|
+ 8010b2e: d00b beq.n 8010b48 <ETH_Init+0x104>
|
|
|
+ 8010b30: d802 bhi.n 8010b38 <ETH_Init+0xf4>
|
|
|
+ 8010b32: 2804 cmp r0, #4
|
|
|
+ 8010b34: d123 bne.n 8010b7e <ETH_Init+0x13a>
|
|
|
+ 8010b36: e010 b.n 8010b5a <ETH_Init+0x116>
|
|
|
+ 8010b38: 280e cmp r0, #14
|
|
|
+ 8010b3a: d00a beq.n 8010b52 <ETH_Init+0x10e>
|
|
|
+ 8010b3c: 2812 cmp r0, #18
|
|
|
+ 8010b3e: d11e bne.n 8010b7e <ETH_Init+0x13a>
|
|
|
{
|
|
|
case PHY_100BTX_FULL:
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
- 8010bc8: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
|
- 8010bcc: 6223 str r3, [r4, #32]
|
|
|
- 8010bce: e000 b.n 8010bd2 <ETH_Init+0x106>
|
|
|
+ 8010b40: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
|
+ 8010b44: 6223 str r3, [r4, #32]
|
|
|
+ 8010b46: e000 b.n 8010b4a <ETH_Init+0x106>
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
|
|
|
break;
|
|
|
|
|
|
case PHY_100BTX_HALF:
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
|
|
|
- 8010bd0: 6225 str r5, [r4, #32]
|
|
|
+ 8010b48: 6225 str r5, [r4, #32]
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
|
|
|
- 8010bd2: f44f 4380 mov.w r3, #16384 ; 0x4000
|
|
|
- 8010bd6: 6163 str r3, [r4, #20]
|
|
|
+ 8010b4a: f44f 4380 mov.w r3, #16384 ; 0x4000
|
|
|
+ 8010b4e: 6163 str r3, [r4, #20]
|
|
|
break;
|
|
|
- 8010bd8: e015 b.n 8010c06 <ETH_Init+0x13a>
|
|
|
+ 8010b50: e015 b.n 8010b7e <ETH_Init+0x13a>
|
|
|
|
|
|
case PHY_10M_FULL:
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
|
|
|
- 8010bda: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
|
- 8010bde: 6223 str r3, [r4, #32]
|
|
|
- 8010be0: e000 b.n 8010be4 <ETH_Init+0x118>
|
|
|
+ 8010b52: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
|
+ 8010b56: 6223 str r3, [r4, #32]
|
|
|
+ 8010b58: e000 b.n 8010b5c <ETH_Init+0x118>
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
|
|
|
break;
|
|
|
|
|
|
case PHY_10M_HALF:
|
|
|
ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
|
|
|
- 8010be2: 6225 str r5, [r4, #32]
|
|
|
+ 8010b5a: 6225 str r5, [r4, #32]
|
|
|
ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
|
|
|
- 8010be4: 6165 str r5, [r4, #20]
|
|
|
+ 8010b5c: 6165 str r5, [r4, #20]
|
|
|
break;
|
|
|
- 8010be6: e00e b.n 8010c06 <ETH_Init+0x13a>
|
|
|
+ 8010b5e: e00e b.n 8010b7e <ETH_Init+0x13a>
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
|
|
|
- 8010be8: 6a22 ldr r2, [r4, #32]
|
|
|
+ 8010b60: 6a22 ldr r2, [r4, #32]
|
|
|
(uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
|
|
|
- 8010bea: 6963 ldr r3, [r4, #20]
|
|
|
+ 8010b62: 6963 ldr r3, [r4, #20]
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
|
|
|
- 8010bec: 08d2 lsrs r2, r2, #3
|
|
|
- 8010bee: ea42 0253 orr.w r2, r2, r3, lsr #1
|
|
|
- 8010bf2: 4630 mov r0, r6
|
|
|
- 8010bf4: b292 uxth r2, r2
|
|
|
- 8010bf6: f7ff ff41 bl 8010a7c <ETH_WritePHYRegister>
|
|
|
- 8010bfa: 2800 cmp r0, #0
|
|
|
- 8010bfc: d09b beq.n 8010b36 <ETH_Init+0x6a>
|
|
|
+ 8010b64: 08d2 lsrs r2, r2, #3
|
|
|
+ 8010b66: ea42 0253 orr.w r2, r2, r3, lsr #1
|
|
|
+ 8010b6a: 4630 mov r0, r6
|
|
|
+ 8010b6c: b292 uxth r2, r2
|
|
|
+ 8010b6e: f7ff ff41 bl 80109f4 <ETH_WritePHYRegister>
|
|
|
+ 8010b72: 2800 cmp r0, #0
|
|
|
+ 8010b74: d09b beq.n 8010aae <ETH_Init+0x6a>
|
|
|
{
|
|
|
/* Return ERROR in case of write timeout */
|
|
|
return ETH_ERROR;
|
|
|
}
|
|
|
/* Delay to assure PHY configuration */
|
|
|
_eth_delay_(PHY_CONFIG_DELAY);
|
|
|
- 8010bfe: f06f 407f mvn.w r0, #4278190080 ; 0xff000000
|
|
|
- 8010c02: f7ff fd1d bl 8010640 <ETH_Delay>
|
|
|
+ 8010b76: f06f 407f mvn.w r0, #4278190080 ; 0xff000000
|
|
|
+ 8010b7a: f7ff fd1d bl 80105b8 <ETH_Delay>
|
|
|
|
|
|
}
|
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
|
/* Get the ETHERNET MACCR value */
|
|
|
tmpreg = ETH->MACCR;
|
|
|
- 8010c06: 4b43 ldr r3, [pc, #268] ; (8010d14 <ETH_Init+0x248>)
|
|
|
+ 8010b7e: 4b43 ldr r3, [pc, #268] ; (8010c8c <ETH_Init+0x248>)
|
|
|
/* Clear WD, PCE, PS, TE and RE bits */
|
|
|
tmpreg &= MACCR_CLEAR_MASK;
|
|
|
- 8010c08: 4a4e ldr r2, [pc, #312] ; (8010d44 <ETH_Init+0x278>)
|
|
|
+ 8010b80: 4a4e ldr r2, [pc, #312] ; (8010cbc <ETH_Init+0x278>)
|
|
|
_eth_delay_(PHY_CONFIG_DELAY);
|
|
|
|
|
|
}
|
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
|
/* Get the ETHERNET MACCR value */
|
|
|
tmpreg = ETH->MACCR;
|
|
|
- 8010c0a: 6819 ldr r1, [r3, #0]
|
|
|
+ 8010b82: 6819 ldr r1, [r3, #0]
|
|
|
/* Set the IPCO bit according to ETH_ChecksumOffload value */
|
|
|
/* Set the DR bit according to ETH_RetryTransmission value */
|
|
|
/* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
|
|
|
/* Set the BL bit according to ETH_BackOffLimit value */
|
|
|
/* Set the DC bit according to ETH_DeferralCheck value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
|
|
- 8010c0c: 68a0 ldr r0, [r4, #8]
|
|
|
+ 8010b84: 68a0 ldr r0, [r4, #8]
|
|
|
}
|
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
|
/* Get the ETHERNET MACCR value */
|
|
|
tmpreg = ETH->MACCR;
|
|
|
/* Clear WD, PCE, PS, TE and RE bits */
|
|
|
tmpreg &= MACCR_CLEAR_MASK;
|
|
|
- 8010c0e: 400a ands r2, r1
|
|
|
+ 8010b86: 400a ands r2, r1
|
|
|
/* Set the IPCO bit according to ETH_ChecksumOffload value */
|
|
|
/* Set the DR bit according to ETH_RetryTransmission value */
|
|
|
/* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
|
|
|
/* Set the BL bit according to ETH_BackOffLimit value */
|
|
|
/* Set the DC bit according to ETH_DeferralCheck value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
|
|
- 8010c10: 6861 ldr r1, [r4, #4]
|
|
|
- 8010c12: 4308 orrs r0, r1
|
|
|
+ 8010b88: 6861 ldr r1, [r4, #4]
|
|
|
+ 8010b8a: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_Jabber |
|
|
|
- 8010c14: 68e1 ldr r1, [r4, #12]
|
|
|
- 8010c16: 4308 orrs r0, r1
|
|
|
+ 8010b8c: 68e1 ldr r1, [r4, #12]
|
|
|
+ 8010b8e: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_InterFrameGap |
|
|
|
- 8010c18: 6921 ldr r1, [r4, #16]
|
|
|
- 8010c1a: 4308 orrs r0, r1
|
|
|
+ 8010b90: 6921 ldr r1, [r4, #16]
|
|
|
+ 8010b92: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_CarrierSense |
|
|
|
- 8010c1c: 6961 ldr r1, [r4, #20]
|
|
|
- 8010c1e: 4308 orrs r0, r1
|
|
|
+ 8010b94: 6961 ldr r1, [r4, #20]
|
|
|
+ 8010b96: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_Speed |
|
|
|
- 8010c20: 69a1 ldr r1, [r4, #24]
|
|
|
- 8010c22: 4308 orrs r0, r1
|
|
|
+ 8010b98: 69a1 ldr r1, [r4, #24]
|
|
|
+ 8010b9a: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_ReceiveOwn |
|
|
|
- 8010c24: 69e1 ldr r1, [r4, #28]
|
|
|
- 8010c26: 4308 orrs r0, r1
|
|
|
+ 8010b9c: 69e1 ldr r1, [r4, #28]
|
|
|
+ 8010b9e: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_LoopbackMode |
|
|
|
- 8010c28: 6a21 ldr r1, [r4, #32]
|
|
|
- 8010c2a: 4308 orrs r0, r1
|
|
|
+ 8010ba0: 6a21 ldr r1, [r4, #32]
|
|
|
+ 8010ba2: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_Mode |
|
|
|
- 8010c2c: 6a61 ldr r1, [r4, #36] ; 0x24
|
|
|
- 8010c2e: 4308 orrs r0, r1
|
|
|
+ 8010ba4: 6a61 ldr r1, [r4, #36] ; 0x24
|
|
|
+ 8010ba6: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_ChecksumOffload |
|
|
|
- 8010c30: 6aa1 ldr r1, [r4, #40] ; 0x28
|
|
|
- 8010c32: 4308 orrs r0, r1
|
|
|
+ 8010ba8: 6aa1 ldr r1, [r4, #40] ; 0x28
|
|
|
+ 8010baa: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_RetryTransmission |
|
|
|
- 8010c34: 6ae1 ldr r1, [r4, #44] ; 0x2c
|
|
|
- 8010c36: 4308 orrs r0, r1
|
|
|
+ 8010bac: 6ae1 ldr r1, [r4, #44] ; 0x2c
|
|
|
+ 8010bae: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
|
|
- 8010c38: 6b21 ldr r1, [r4, #48] ; 0x30
|
|
|
- 8010c3a: 4308 orrs r0, r1
|
|
|
+ 8010bb0: 6b21 ldr r1, [r4, #48] ; 0x30
|
|
|
+ 8010bb2: 4308 orrs r0, r1
|
|
|
/* Set the IPCO bit according to ETH_ChecksumOffload value */
|
|
|
/* Set the DR bit according to ETH_RetryTransmission value */
|
|
|
/* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
|
|
|
/* Set the BL bit according to ETH_BackOffLimit value */
|
|
|
/* Set the DC bit according to ETH_DeferralCheck value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
|
|
- 8010c3c: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
|
- 8010c3e: 4301 orrs r1, r0
|
|
|
- 8010c40: 430a orrs r2, r1
|
|
|
+ 8010bb4: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
|
+ 8010bb6: 4301 orrs r1, r0
|
|
|
+ 8010bb8: 430a orrs r2, r1
|
|
|
ETH_InitStruct->ETH_RetryTransmission |
|
|
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
|
|
ETH_InitStruct->ETH_BackOffLimit |
|
|
|
ETH_InitStruct->ETH_DeferralCheck);
|
|
|
/* Write to ETHERNET MACCR */
|
|
|
ETH->MACCR = (uint32_t)tmpreg;
|
|
|
- 8010c42: 601a str r2, [r3, #0]
|
|
|
+ 8010bba: 601a str r2, [r3, #0]
|
|
|
/* Set the DAIF bit according to ETH_DestinationAddrFilter value */
|
|
|
/* Set the PR bit according to ETH_PromiscuousMode value */
|
|
|
/* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
|
|
|
/* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
|
|
|
/* Write to ETHERNET MACFFR */
|
|
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
|
|
- 8010c44: 6ba2 ldr r2, [r4, #56] ; 0x38
|
|
|
- 8010c46: 6be1 ldr r1, [r4, #60] ; 0x3c
|
|
|
- 8010c48: 4311 orrs r1, r2
|
|
|
+ 8010bbc: 6ba2 ldr r2, [r4, #56] ; 0x38
|
|
|
+ 8010bbe: 6be1 ldr r1, [r4, #60] ; 0x3c
|
|
|
+ 8010bc0: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_SourceAddrFilter |
|
|
|
- 8010c4a: 6c22 ldr r2, [r4, #64] ; 0x40
|
|
|
- 8010c4c: 4311 orrs r1, r2
|
|
|
+ 8010bc2: 6c22 ldr r2, [r4, #64] ; 0x40
|
|
|
+ 8010bc4: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_PassControlFrames |
|
|
|
- 8010c4e: 6c62 ldr r2, [r4, #68] ; 0x44
|
|
|
- 8010c50: 4311 orrs r1, r2
|
|
|
+ 8010bc6: 6c62 ldr r2, [r4, #68] ; 0x44
|
|
|
+ 8010bc8: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_BroadcastFramesReception |
|
|
|
- 8010c52: 6ca2 ldr r2, [r4, #72] ; 0x48
|
|
|
- 8010c54: 4311 orrs r1, r2
|
|
|
+ 8010bca: 6ca2 ldr r2, [r4, #72] ; 0x48
|
|
|
+ 8010bcc: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_DestinationAddrFilter |
|
|
|
- 8010c56: 6ce2 ldr r2, [r4, #76] ; 0x4c
|
|
|
- 8010c58: 4311 orrs r1, r2
|
|
|
+ 8010bce: 6ce2 ldr r2, [r4, #76] ; 0x4c
|
|
|
+ 8010bd0: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_PromiscuousMode |
|
|
|
- 8010c5a: 6d22 ldr r2, [r4, #80] ; 0x50
|
|
|
- 8010c5c: 4311 orrs r1, r2
|
|
|
+ 8010bd2: 6d22 ldr r2, [r4, #80] ; 0x50
|
|
|
+ 8010bd4: 4311 orrs r1, r2
|
|
|
/* Set the DAIF bit according to ETH_DestinationAddrFilter value */
|
|
|
/* Set the PR bit according to ETH_PromiscuousMode value */
|
|
|
/* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
|
|
|
/* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
|
|
|
/* Write to ETHERNET MACFFR */
|
|
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
|
|
- 8010c5e: 6d62 ldr r2, [r4, #84] ; 0x54
|
|
|
- 8010c60: 430a orrs r2, r1
|
|
|
- 8010c62: 605a str r2, [r3, #4]
|
|
|
+ 8010bd6: 6d62 ldr r2, [r4, #84] ; 0x54
|
|
|
+ 8010bd8: 430a orrs r2, r1
|
|
|
+ 8010bda: 605a str r2, [r3, #4]
|
|
|
ETH_InitStruct->ETH_PromiscuousMode |
|
|
|
ETH_InitStruct->ETH_MulticastFramesFilter |
|
|
|
ETH_InitStruct->ETH_UnicastFramesFilter);
|
|
|
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
|
|
|
/* Write to ETHERNET MACHTHR */
|
|
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
|
|
- 8010c64: 6da2 ldr r2, [r4, #88] ; 0x58
|
|
|
- 8010c66: 609a str r2, [r3, #8]
|
|
|
+ 8010bdc: 6da2 ldr r2, [r4, #88] ; 0x58
|
|
|
+ 8010bde: 609a str r2, [r3, #8]
|
|
|
/* Write to ETHERNET MACHTLR */
|
|
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
|
|
- 8010c68: 6de2 ldr r2, [r4, #92] ; 0x5c
|
|
|
- 8010c6a: 60da str r2, [r3, #12]
|
|
|
+ 8010be0: 6de2 ldr r2, [r4, #92] ; 0x5c
|
|
|
+ 8010be2: 60da str r2, [r3, #12]
|
|
|
/* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
|
|
|
/* Set the PLT bit according to ETH_PauseLowThreshold value */
|
|
|
/* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
|
|
|
/* Set the RFE bit according to ETH_ReceiveFlowControl value */
|
|
|
/* Set the TFE bit according to ETH_TransmitFlowControl value */
|
|
|
tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
|
|
- 8010c6c: 6e62 ldr r2, [r4, #100] ; 0x64
|
|
|
- 8010c6e: 6ea1 ldr r1, [r4, #104] ; 0x68
|
|
|
+ 8010be4: 6e62 ldr r2, [r4, #100] ; 0x64
|
|
|
+ 8010be6: 6ea1 ldr r1, [r4, #104] ; 0x68
|
|
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
|
|
/* Write to ETHERNET MACHTLR */
|
|
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
|
|
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
|
|
|
/* Get the ETHERNET MACFCR value */
|
|
|
tmpreg = ETH->MACFCR;
|
|
|
- 8010c70: 6998 ldr r0, [r3, #24]
|
|
|
+ 8010be8: 6998 ldr r0, [r3, #24]
|
|
|
/* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
|
|
|
/* Set the PLT bit according to ETH_PauseLowThreshold value */
|
|
|
/* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
|
|
|
/* Set the RFE bit according to ETH_ReceiveFlowControl value */
|
|
|
/* Set the TFE bit according to ETH_TransmitFlowControl value */
|
|
|
tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
|
|
- 8010c72: 4311 orrs r1, r2
|
|
|
+ 8010bea: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_ZeroQuantaPause |
|
|
|
- 8010c74: 6ee2 ldr r2, [r4, #108] ; 0x6c
|
|
|
- 8010c76: 4311 orrs r1, r2
|
|
|
+ 8010bec: 6ee2 ldr r2, [r4, #108] ; 0x6c
|
|
|
+ 8010bee: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_PauseLowThreshold |
|
|
|
- 8010c78: 6f22 ldr r2, [r4, #112] ; 0x70
|
|
|
- 8010c7a: 4311 orrs r1, r2
|
|
|
+ 8010bf0: 6f22 ldr r2, [r4, #112] ; 0x70
|
|
|
+ 8010bf2: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
|
|
- 8010c7c: 6f62 ldr r2, [r4, #116] ; 0x74
|
|
|
- 8010c7e: 4311 orrs r1, r2
|
|
|
+ 8010bf4: 6f62 ldr r2, [r4, #116] ; 0x74
|
|
|
+ 8010bf6: 4311 orrs r1, r2
|
|
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
|
|
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
|
|
|
/* Get the ETHERNET MACFCR value */
|
|
|
tmpreg = ETH->MACFCR;
|
|
|
/* Clear xx bits */
|
|
|
tmpreg &= MACFCR_CLEAR_MASK;
|
|
|
- 8010c80: f64f 7241 movw r2, #65345 ; 0xff41
|
|
|
- 8010c84: 4002 ands r2, r0
|
|
|
+ 8010bf8: f64f 7241 movw r2, #65345 ; 0xff41
|
|
|
+ 8010bfc: 4002 ands r2, r0
|
|
|
/* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
|
|
|
/* Set the PLT bit according to ETH_PauseLowThreshold value */
|
|
|
/* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
|
|
|
/* Set the RFE bit according to ETH_ReceiveFlowControl value */
|
|
|
/* Set the TFE bit according to ETH_TransmitFlowControl value */
|
|
|
tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
|
|
- 8010c86: 430a orrs r2, r1
|
|
|
- 8010c88: 6e21 ldr r1, [r4, #96] ; 0x60
|
|
|
- 8010c8a: ea42 4101 orr.w r1, r2, r1, lsl #16
|
|
|
+ 8010bfe: 430a orrs r2, r1
|
|
|
+ 8010c00: 6e21 ldr r1, [r4, #96] ; 0x60
|
|
|
+ 8010c02: ea42 4101 orr.w r1, r2, r1, lsl #16
|
|
|
ETH_InitStruct->ETH_PauseLowThreshold |
|
|
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
|
|
ETH_InitStruct->ETH_ReceiveFlowControl |
|
|
|
ETH_InitStruct->ETH_TransmitFlowControl);
|
|
|
/* Write to ETHERNET MACFCR */
|
|
|
ETH->MACFCR = (uint32_t)tmpreg;
|
|
|
- 8010c8e: 6199 str r1, [r3, #24]
|
|
|
+ 8010c06: 6199 str r1, [r3, #24]
|
|
|
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
|
|
|
/* Set the ETV bit according to ETH_VLANTagComparison value */
|
|
|
/* Set the VL bit according to ETH_VLANTagIdentifier value */
|
|
|
ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
|
|
- 8010c90: 6fe1 ldr r1, [r4, #124] ; 0x7c
|
|
|
- 8010c92: 6fa2 ldr r2, [r4, #120] ; 0x78
|
|
|
- 8010c94: 430a orrs r2, r1
|
|
|
- 8010c96: 61da str r2, [r3, #28]
|
|
|
+ 8010c08: 6fe1 ldr r1, [r4, #124] ; 0x7c
|
|
|
+ 8010c0a: 6fa2 ldr r2, [r4, #120] ; 0x78
|
|
|
+ 8010c0c: 430a orrs r2, r1
|
|
|
+ 8010c0e: 61da str r2, [r3, #28]
|
|
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
|
|
|
|
|
/*-------------------------------- DMA Config ------------------------------*/
|
|
|
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
|
|
|
/* Get the ETHERNET DMAOMR value */
|
|
|
tmpreg = ETH->DMAOMR;
|
|
|
- 8010c98: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
|
+ 8010c10: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
|
/* Clear xx bits */
|
|
|
tmpreg &= DMAOMR_CLEAR_MASK;
|
|
|
- 8010c9c: 4a2a ldr r2, [pc, #168] ; (8010d48 <ETH_Init+0x27c>)
|
|
|
+ 8010c14: 4a2a ldr r2, [pc, #168] ; (8010cc0 <ETH_Init+0x27c>)
|
|
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
|
|
|
|
|
/*-------------------------------- DMA Config ------------------------------*/
|
|
|
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
|
|
|
/* Get the ETHERNET DMAOMR value */
|
|
|
tmpreg = ETH->DMAOMR;
|
|
|
- 8010c9e: 6999 ldr r1, [r3, #24]
|
|
|
+ 8010c16: 6999 ldr r1, [r3, #24]
|
|
|
/* Set the TTC bit according to ETH_TransmitThresholdControl value */
|
|
|
/* Set the FEF bit according to ETH_ForwardErrorFrames value */
|
|
|
/* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
|
|
|
/* Set the RTC bit according to ETH_ReceiveThresholdControl value */
|
|
|
/* Set the OSF bit according to ETH_SecondFrameOperate value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
|
|
- 8010ca0: f8d4 0084 ldr.w r0, [r4, #132] ; 0x84
|
|
|
+ 8010c18: f8d4 0084 ldr.w r0, [r4, #132] ; 0x84
|
|
|
/*-------------------------------- DMA Config ------------------------------*/
|
|
|
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
|
|
|
/* Get the ETHERNET DMAOMR value */
|
|
|
tmpreg = ETH->DMAOMR;
|
|
|
/* Clear xx bits */
|
|
|
tmpreg &= DMAOMR_CLEAR_MASK;
|
|
|
- 8010ca4: 400a ands r2, r1
|
|
|
+ 8010c1c: 400a ands r2, r1
|
|
|
/* Set the TTC bit according to ETH_TransmitThresholdControl value */
|
|
|
/* Set the FEF bit according to ETH_ForwardErrorFrames value */
|
|
|
/* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
|
|
|
/* Set the RTC bit according to ETH_ReceiveThresholdControl value */
|
|
|
/* Set the OSF bit according to ETH_SecondFrameOperate value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
|
|
- 8010ca6: f8d4 1080 ldr.w r1, [r4, #128] ; 0x80
|
|
|
- 8010caa: 4308 orrs r0, r1
|
|
|
+ 8010c1e: f8d4 1080 ldr.w r1, [r4, #128] ; 0x80
|
|
|
+ 8010c22: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_ReceiveStoreForward |
|
|
|
- 8010cac: f8d4 1088 ldr.w r1, [r4, #136] ; 0x88
|
|
|
- 8010cb0: 4308 orrs r0, r1
|
|
|
+ 8010c24: f8d4 1088 ldr.w r1, [r4, #136] ; 0x88
|
|
|
+ 8010c28: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_FlushReceivedFrame |
|
|
|
- 8010cb2: f8d4 108c ldr.w r1, [r4, #140] ; 0x8c
|
|
|
- 8010cb6: 4308 orrs r0, r1
|
|
|
+ 8010c2a: f8d4 108c ldr.w r1, [r4, #140] ; 0x8c
|
|
|
+ 8010c2e: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_TransmitStoreForward |
|
|
|
- 8010cb8: f8d4 1090 ldr.w r1, [r4, #144] ; 0x90
|
|
|
- 8010cbc: 4308 orrs r0, r1
|
|
|
+ 8010c30: f8d4 1090 ldr.w r1, [r4, #144] ; 0x90
|
|
|
+ 8010c34: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_TransmitThresholdControl |
|
|
|
- 8010cbe: f8d4 1094 ldr.w r1, [r4, #148] ; 0x94
|
|
|
- 8010cc2: 4308 orrs r0, r1
|
|
|
+ 8010c36: f8d4 1094 ldr.w r1, [r4, #148] ; 0x94
|
|
|
+ 8010c3a: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
|
|
- 8010cc4: f8d4 1098 ldr.w r1, [r4, #152] ; 0x98
|
|
|
- 8010cc8: 4308 orrs r0, r1
|
|
|
+ 8010c3c: f8d4 1098 ldr.w r1, [r4, #152] ; 0x98
|
|
|
+ 8010c40: 4308 orrs r0, r1
|
|
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
|
|
|
- 8010cca: f8d4 109c ldr.w r1, [r4, #156] ; 0x9c
|
|
|
- 8010cce: 4308 orrs r0, r1
|
|
|
+ 8010c42: f8d4 109c ldr.w r1, [r4, #156] ; 0x9c
|
|
|
+ 8010c46: 4308 orrs r0, r1
|
|
|
/* Set the TTC bit according to ETH_TransmitThresholdControl value */
|
|
|
/* Set the FEF bit according to ETH_ForwardErrorFrames value */
|
|
|
/* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
|
|
|
/* Set the RTC bit according to ETH_ReceiveThresholdControl value */
|
|
|
/* Set the OSF bit according to ETH_SecondFrameOperate value */
|
|
|
tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
|
|
- 8010cd0: f8d4 10a0 ldr.w r1, [r4, #160] ; 0xa0
|
|
|
- 8010cd4: 4301 orrs r1, r0
|
|
|
- 8010cd6: 430a orrs r2, r1
|
|
|
+ 8010c48: f8d4 10a0 ldr.w r1, [r4, #160] ; 0xa0
|
|
|
+ 8010c4c: 4301 orrs r1, r0
|
|
|
+ 8010c4e: 430a orrs r2, r1
|
|
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
|
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
|
|
|
ETH_InitStruct->ETH_ReceiveThresholdControl |
|
|
|
ETH_InitStruct->ETH_SecondFrameOperate);
|
|
|
/* Write to ETHERNET DMAOMR */
|
|
|
ETH->DMAOMR = (uint32_t)tmpreg;
|
|
|
- 8010cd8: 619a str r2, [r3, #24]
|
|
|
+ 8010c50: 619a str r2, [r3, #24]
|
|
|
/* Set the FB bit according to ETH_FixedBurst value */
|
|
|
/* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
|
|
|
/* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
|
|
|
/* Set the DSL bit according to ETH_DesciptorSkipLength value */
|
|
|
/* Set the PR and DA bits according to ETH_DMAArbitration value */
|
|
|
ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
|
|
|
- 8010cda: f8d4 20a8 ldr.w r2, [r4, #168] ; 0xa8
|
|
|
- 8010cde: f8d4 10a4 ldr.w r1, [r4, #164] ; 0xa4
|
|
|
- 8010ce2: 4311 orrs r1, r2
|
|
|
+ 8010c52: f8d4 20a8 ldr.w r2, [r4, #168] ; 0xa8
|
|
|
+ 8010c56: f8d4 10a4 ldr.w r1, [r4, #164] ; 0xa4
|
|
|
+ 8010c5a: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_FixedBurst |
|
|
|
ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
|
|
- 8010ce4: f8d4 20ac ldr.w r2, [r4, #172] ; 0xac
|
|
|
+ 8010c5c: f8d4 20ac ldr.w r2, [r4, #172] ; 0xac
|
|
|
/* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
|
|
|
/* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
|
|
|
/* Set the DSL bit according to ETH_DesciptorSkipLength value */
|
|
|
/* Set the PR and DA bits according to ETH_DMAArbitration value */
|
|
|
ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
|
|
|
ETH_InitStruct->ETH_FixedBurst |
|
|
|
- 8010ce8: f441 0100 orr.w r1, r1, #8388608 ; 0x800000
|
|
|
+ 8010c60: f441 0100 orr.w r1, r1, #8388608 ; 0x800000
|
|
|
ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
|
|
- 8010cec: 4311 orrs r1, r2
|
|
|
+ 8010c64: 4311 orrs r1, r2
|
|
|
ETH_InitStruct->ETH_TxDMABurstLength |
|
|
|
- 8010cee: f8d4 20b0 ldr.w r2, [r4, #176] ; 0xb0
|
|
|
- 8010cf2: 4311 orrs r1, r2
|
|
|
+ 8010c66: f8d4 20b0 ldr.w r2, [r4, #176] ; 0xb0
|
|
|
+ 8010c6a: 4311 orrs r1, r2
|
|
|
(ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
|
|
|
- 8010cf4: f8d4 20b8 ldr.w r2, [r4, #184] ; 0xb8
|
|
|
- 8010cf8: 430a orrs r2, r1
|
|
|
- 8010cfa: f8d4 10b4 ldr.w r1, [r4, #180] ; 0xb4
|
|
|
+ 8010c6c: f8d4 20b8 ldr.w r2, [r4, #184] ; 0xb8
|
|
|
+ 8010c70: 430a orrs r2, r1
|
|
|
+ 8010c72: f8d4 10b4 ldr.w r1, [r4, #180] ; 0xb4
|
|
|
/* Set the FB bit according to ETH_FixedBurst value */
|
|
|
/* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
|
|
|
/* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
|
|
|
/* Set the DSL bit according to ETH_DesciptorSkipLength value */
|
|
|
/* Set the PR and DA bits according to ETH_DMAArbitration value */
|
|
|
ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
|
|
|
- 8010cfe: ea42 0281 orr.w r2, r2, r1, lsl #2
|
|
|
- 8010d02: 601a str r2, [r3, #0]
|
|
|
+ 8010c76: ea42 0281 orr.w r2, r2, r1, lsl #2
|
|
|
+ 8010c7a: 601a str r2, [r3, #0]
|
|
|
ETH_InitStruct->ETH_DMAArbitration |
|
|
|
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
|
|
|
|
|
|
#ifdef USE_ENHANCED_DMA_DESCRIPTORS
|
|
|
/* Enable the Enhanced DMA descriptors */
|
|
|
ETH->DMABMR |= ETH_DMABMR_EDE;
|
|
|
- 8010d04: 681a ldr r2, [r3, #0]
|
|
|
- 8010d06: f042 0280 orr.w r2, r2, #128 ; 0x80
|
|
|
- 8010d0a: 601a str r2, [r3, #0]
|
|
|
+ 8010c7c: 681a ldr r2, [r3, #0]
|
|
|
+ 8010c7e: f042 0280 orr.w r2, r2, #128 ; 0x80
|
|
|
+ 8010c82: 601a str r2, [r3, #0]
|
|
|
#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
|
|
|
|
|
|
/* Return Ethernet configuration success */
|
|
|
return ETH_SUCCESS;
|
|
|
- 8010d0c: 2001 movs r0, #1
|
|
|
+ 8010c84: 2001 movs r0, #1
|
|
|
}
|
|
|
- 8010d0e: b007 add sp, #28
|
|
|
- 8010d10: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
- 8010d12: bf00 nop
|
|
|
- 8010d14: 40028000 .word 0x40028000
|
|
|
- 8010d18: feced300 .word 0xfeced300
|
|
|
- 8010d1c: 00e4e1bf .word 0x00e4e1bf
|
|
|
- 8010d20: fde9f140 .word 0xfde9f140
|
|
|
- 8010d24: 017d783f .word 0x017d783f
|
|
|
- 8010d28: fc6c7900 .word 0xfc6c7900
|
|
|
- 8010d2c: 026259ff .word 0x026259ff
|
|
|
- 8010d30: fa0a1f00 .word 0xfa0a1f00
|
|
|
- 8010d34: 02faf07f .word 0x02faf07f
|
|
|
- 8010d38: 000fffff .word 0x000fffff
|
|
|
- 8010d3c: 0004fffe .word 0x0004fffe
|
|
|
- 8010d40: 0004ffff .word 0x0004ffff
|
|
|
- 8010d44: ff20810f .word 0xff20810f
|
|
|
- 8010d48: f8de3f23 .word 0xf8de3f23
|
|
|
-
|
|
|
-08010d4c <NVIC_SystemReset>:
|
|
|
- 8010d4c: f3bf 8f4f dsb sy
|
|
|
+ 8010c86: b007 add sp, #28
|
|
|
+ 8010c88: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
+ 8010c8a: bf00 nop
|
|
|
+ 8010c8c: 40028000 .word 0x40028000
|
|
|
+ 8010c90: feced300 .word 0xfeced300
|
|
|
+ 8010c94: 00e4e1bf .word 0x00e4e1bf
|
|
|
+ 8010c98: fde9f140 .word 0xfde9f140
|
|
|
+ 8010c9c: 017d783f .word 0x017d783f
|
|
|
+ 8010ca0: fc6c7900 .word 0xfc6c7900
|
|
|
+ 8010ca4: 026259ff .word 0x026259ff
|
|
|
+ 8010ca8: fa0a1f00 .word 0xfa0a1f00
|
|
|
+ 8010cac: 02faf07f .word 0x02faf07f
|
|
|
+ 8010cb0: 000fffff .word 0x000fffff
|
|
|
+ 8010cb4: 0004fffe .word 0x0004fffe
|
|
|
+ 8010cb8: 0004ffff .word 0x0004ffff
|
|
|
+ 8010cbc: ff20810f .word 0xff20810f
|
|
|
+ 8010cc0: f8de3f23 .word 0xf8de3f23
|
|
|
+
|
|
|
+08010cc4 <NVIC_SystemReset>:
|
|
|
+ 8010cc4: f3bf 8f4f dsb sy
|
|
|
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
|
|
|
- 8010d50: 4a04 ldr r2, [pc, #16] ; (8010d64 <NVIC_SystemReset+0x18>)
|
|
|
- 8010d52: 4b05 ldr r3, [pc, #20] ; (8010d68 <NVIC_SystemReset+0x1c>)
|
|
|
- 8010d54: 68d1 ldr r1, [r2, #12]
|
|
|
- 8010d56: f401 61e0 and.w r1, r1, #1792 ; 0x700
|
|
|
- 8010d5a: 430b orrs r3, r1
|
|
|
+ 8010cc8: 4a04 ldr r2, [pc, #16] ; (8010cdc <NVIC_SystemReset+0x18>)
|
|
|
+ 8010cca: 4b05 ldr r3, [pc, #20] ; (8010ce0 <NVIC_SystemReset+0x1c>)
|
|
|
+ 8010ccc: 68d1 ldr r1, [r2, #12]
|
|
|
+ 8010cce: f401 61e0 and.w r1, r1, #1792 ; 0x700
|
|
|
+ 8010cd2: 430b orrs r3, r1
|
|
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
|
|
//static inline void NVIC_SystemReset(void)
|
|
|
{
|
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
|
buffered write are completed before reset */
|
|
|
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
- 8010d5c: 60d3 str r3, [r2, #12]
|
|
|
- 8010d5e: f3bf 8f4f dsb sy
|
|
|
- 8010d62: e7fe b.n 8010d62 <NVIC_SystemReset+0x16>
|
|
|
- 8010d64: e000ed00 .word 0xe000ed00
|
|
|
- 8010d68: 05fa0004 .word 0x05fa0004
|
|
|
+ 8010cd4: 60d3 str r3, [r2, #12]
|
|
|
+ 8010cd6: f3bf 8f4f dsb sy
|
|
|
+ 8010cda: e7fe b.n 8010cda <NVIC_SystemReset+0x16>
|
|
|
+ 8010cdc: e000ed00 .word 0xe000ed00
|
|
|
+ 8010ce0: 05fa0004 .word 0x05fa0004
|
|
|
|
|
|
-08010d6c <UpdateTimeout_Handler>:
|
|
|
+08010ce4 <UpdateTimeout_Handler>:
|
|
|
void UpdateTimeout_Handler(void)
|
|
|
{
|
|
|
static char lcdbuf[32] = {0};
|
|
|
static uint8_t time = UPDATE_TIMEOUT;
|
|
|
|
|
|
if ((fUpload) || (fInvalidFw)) return;
|
|
|
- 8010d6c: 4b07 ldr r3, [pc, #28] ; (8010d8c <UpdateTimeout_Handler+0x20>)
|
|
|
- 8010d6e: 781b ldrb r3, [r3, #0]
|
|
|
- 8010d70: b953 cbnz r3, 8010d88 <UpdateTimeout_Handler+0x1c>
|
|
|
- 8010d72: 4b07 ldr r3, [pc, #28] ; (8010d90 <UpdateTimeout_Handler+0x24>)
|
|
|
- 8010d74: 781b ldrb r3, [r3, #0]
|
|
|
- 8010d76: b93b cbnz r3, 8010d88 <UpdateTimeout_Handler+0x1c>
|
|
|
+ 8010ce4: 4b07 ldr r3, [pc, #28] ; (8010d04 <UpdateTimeout_Handler+0x20>)
|
|
|
+ 8010ce6: 781b ldrb r3, [r3, #0]
|
|
|
+ 8010ce8: b953 cbnz r3, 8010d00 <UpdateTimeout_Handler+0x1c>
|
|
|
+ 8010cea: 4b07 ldr r3, [pc, #28] ; (8010d08 <UpdateTimeout_Handler+0x24>)
|
|
|
+ 8010cec: 781b ldrb r3, [r3, #0]
|
|
|
+ 8010cee: b93b cbnz r3, 8010d00 <UpdateTimeout_Handler+0x1c>
|
|
|
|
|
|
if (time == 0) {
|
|
|
- 8010d78: 4b06 ldr r3, [pc, #24] ; (8010d94 <UpdateTimeout_Handler+0x28>)
|
|
|
- 8010d7a: 781a ldrb r2, [r3, #0]
|
|
|
- 8010d7c: b912 cbnz r2, 8010d84 <UpdateTimeout_Handler+0x18>
|
|
|
+ 8010cf0: 4b06 ldr r3, [pc, #24] ; (8010d0c <UpdateTimeout_Handler+0x28>)
|
|
|
+ 8010cf2: 781a ldrb r2, [r3, #0]
|
|
|
+ 8010cf4: b912 cbnz r2, 8010cfc <UpdateTimeout_Handler+0x18>
|
|
|
UpdateTimeoutFlag = true;
|
|
|
- 8010d7e: 2201 movs r2, #1
|
|
|
- 8010d80: 4b05 ldr r3, [pc, #20] ; (8010d98 <UpdateTimeout_Handler+0x2c>)
|
|
|
- 8010d82: e000 b.n 8010d86 <UpdateTimeout_Handler+0x1a>
|
|
|
+ 8010cf6: 2201 movs r2, #1
|
|
|
+ 8010cf8: 4b05 ldr r3, [pc, #20] ; (8010d10 <UpdateTimeout_Handler+0x2c>)
|
|
|
+ 8010cfa: e000 b.n 8010cfe <UpdateTimeout_Handler+0x1a>
|
|
|
}
|
|
|
else {
|
|
|
time--;
|
|
|
- 8010d84: 3a01 subs r2, #1
|
|
|
- 8010d86: 701a strb r2, [r3, #0]
|
|
|
- 8010d88: 4770 bx lr
|
|
|
- 8010d8a: bf00 nop
|
|
|
- 8010d8c: 20006db0 .word 0x20006db0
|
|
|
- 8010d90: 20006dc4 .word 0x20006dc4
|
|
|
- 8010d94: 20000115 .word 0x20000115
|
|
|
- 8010d98: 20006db9 .word 0x20006db9
|
|
|
-
|
|
|
-08010d9c <main>:
|
|
|
+ 8010cfc: 3a01 subs r2, #1
|
|
|
+ 8010cfe: 701a strb r2, [r3, #0]
|
|
|
+ 8010d00: 4770 bx lr
|
|
|
+ 8010d02: bf00 nop
|
|
|
+ 8010d04: 20006db0 .word 0x20006db0
|
|
|
+ 8010d08: 20006dc4 .word 0x20006dc4
|
|
|
+ 8010d0c: 20000115 .word 0x20000115
|
|
|
+ 8010d10: 20006dba .word 0x20006dba
|
|
|
+
|
|
|
+08010d14 <main>:
|
|
|
extern SETTINGS_t sSettings;
|
|
|
|
|
|
void UpdateTimeout_Handler(void);
|
|
|
|
|
|
void main(void)
|
|
|
{
|
|
|
- 8010d9c: b570 push {r4, r5, r6, lr}
|
|
|
+ 8010d14: b570 push {r4, r5, r6, lr}
|
|
|
uint8_t bootTry;
|
|
|
uint8_t loadMode;
|
|
|
|
|
|
WDG_Init();
|
|
|
- 8010d9e: f7fe ff45 bl 800fc2c <WDG_Init>
|
|
|
+ 8010d16: f7fe ff45 bl 800fba4 <WDG_Init>
|
|
|
IO_Init();
|
|
|
- 8010da2: f7fe fcad bl 800f700 <IO_Init>
|
|
|
+ 8010d1a: f7fe fcf1 bl 800f700 <IO_Init>
|
|
|
InitUSART();
|
|
|
- 8010da6: f7fe fee9 bl 800fb7c <InitUSART>
|
|
|
+ 8010d1e: f7fe fee9 bl 800faf4 <InitUSART>
|
|
|
|
|
|
/* Enable PWR peripheral clock */
|
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
|
|
|
- 8010daa: 2101 movs r1, #1
|
|
|
- 8010dac: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
|
- 8010db0: f7f9 f8fc bl 8009fac <RCC_APB1PeriphClockCmd>
|
|
|
+ 8010d22: 2101 movs r1, #1
|
|
|
+ 8010d24: f04f 5080 mov.w r0, #268435456 ; 0x10000000
|
|
|
+ 8010d28: f7f9 f940 bl 8009fac <RCC_APB1PeriphClockCmd>
|
|
|
|
|
|
/* Allow access to BKP Domain */
|
|
|
PWR_BackupAccessCmd(ENABLE);
|
|
|
- 8010db4: 2001 movs r0, #1
|
|
|
- 8010db6: f7f9 f8a1 bl 8009efc <PWR_BackupAccessCmd>
|
|
|
+ 8010d2c: 2001 movs r0, #1
|
|
|
+ 8010d2e: f7f9 f8e5 bl 8009efc <PWR_BackupAccessCmd>
|
|
|
|
|
|
/* Включаем тактирование модуля CRC */
|
|
|
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_CRC, ENABLE);
|
|
|
- 8010dba: 2101 movs r1, #1
|
|
|
- 8010dbc: f44f 5080 mov.w r0, #4096 ; 0x1000
|
|
|
- 8010dc0: f7f9 f8e8 bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
+ 8010d32: 2101 movs r1, #1
|
|
|
+ 8010d34: f44f 5080 mov.w r0, #4096 ; 0x1000
|
|
|
+ 8010d38: f7f9 f92c bl 8009f94 <RCC_AHB1PeriphClockCmd>
|
|
|
|
|
|
/* Проверка флага, определяющего состояние устройства. */
|
|
|
/* Флаг установлен - работает Bootloader */
|
|
|
/* Флаг сброшен - запускается основная программа */
|
|
|
|
|
|
SETTINGS_Load();
|
|
|
- 8010dc4: f7fe fe44 bl 800fa50 <SETTINGS_Load>
|
|
|
+ 8010d3c: f7fe fe46 bl 800f9cc <SETTINGS_Load>
|
|
|
|
|
|
/* Проверка флага bootTry. Если флаг установлен, значит произошел сбой в
|
|
|
основной прошивке. Нужно загружать bootloader и ждать обновления ПО */
|
|
|
/* TODO remove if tested */
|
|
|
//bootTry = sSettings.bootParams.bootTry;
|
|
|
loadMode = RTC_ReadBackupRegister(RTC_BKP_DR1);
|
|
|
- 8010dc8: 2001 movs r0, #1
|
|
|
- 8010dca: f7f9 f923 bl 800a014 <RTC_ReadBackupRegister>
|
|
|
- 8010dce: b2c5 uxtb r5, r0
|
|
|
+ 8010d40: 2001 movs r0, #1
|
|
|
+ 8010d42: f7f9 f967 bl 800a014 <RTC_ReadBackupRegister>
|
|
|
+ 8010d46: b2c5 uxtb r5, r0
|
|
|
bootTry = RTC_ReadBackupRegister(RTC_BKP_DR2);
|
|
|
- 8010dd0: 2002 movs r0, #2
|
|
|
- 8010dd2: f7f9 f91f bl 800a014 <RTC_ReadBackupRegister>
|
|
|
- 8010dd6: b2c4 uxtb r4, r0
|
|
|
+ 8010d48: 2002 movs r0, #2
|
|
|
+ 8010d4a: f7f9 f963 bl 800a014 <RTC_ReadBackupRegister>
|
|
|
+ 8010d4e: b2c4 uxtb r4, r0
|
|
|
printf("loadMode: %d\r\nbootTry: %d\r\n", loadMode, bootTry);
|
|
|
- 8010dd8: 4629 mov r1, r5
|
|
|
- 8010dda: 485f ldr r0, [pc, #380] ; (8010f58 <main+0x1bc>)
|
|
|
- 8010ddc: 4622 mov r2, r4
|
|
|
- 8010dde: f000 fc49 bl 8011674 <tfp_printf>
|
|
|
+ 8010d50: 4629 mov r1, r5
|
|
|
+ 8010d52: 485f ldr r0, [pc, #380] ; (8010ed0 <main+0x1bc>)
|
|
|
+ 8010d54: 4622 mov r2, r4
|
|
|
+ 8010d56: f000 fc49 bl 80115ec <tfp_printf>
|
|
|
|
|
|
if (bootTry > 1)
|
|
|
- 8010de2: 2c01 cmp r4, #1
|
|
|
- 8010de4: d91a bls.n 8010e1c <main+0x80>
|
|
|
+ 8010d5a: 2c01 cmp r4, #1
|
|
|
+ 8010d5c: d91a bls.n 8010d94 <main+0x80>
|
|
|
{
|
|
|
bootTry--;
|
|
|
- 8010de6: 1e61 subs r1, r4, #1
|
|
|
+ 8010d5e: 1e61 subs r1, r4, #1
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010de8: 2002 movs r0, #2
|
|
|
- 8010dea: b2c9 uxtb r1, r1
|
|
|
- 8010dec: f7f9 f902 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010d60: 2002 movs r0, #2
|
|
|
+ 8010d62: b2c9 uxtb r1, r1
|
|
|
+ 8010d64: f7f9 f946 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
|
|
|
/* Check if valid stack address (RAM address) then jump to user application */
|
|
|
if (((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) & 0x2FFE0000 ) == 0x20000000)
|
|
|
- 8010df0: 4a5a ldr r2, [pc, #360] ; (8010f5c <main+0x1c0>)
|
|
|
- 8010df2: 4b5b ldr r3, [pc, #364] ; (8010f60 <main+0x1c4>)
|
|
|
- 8010df4: 6811 ldr r1, [r2, #0]
|
|
|
- 8010df6: 400b ands r3, r1
|
|
|
- 8010df8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
- 8010dfc: d10a bne.n 8010e14 <main+0x78>
|
|
|
+ 8010d68: 4a5a ldr r2, [pc, #360] ; (8010ed4 <main+0x1c0>)
|
|
|
+ 8010d6a: 4b5b ldr r3, [pc, #364] ; (8010ed8 <main+0x1c4>)
|
|
|
+ 8010d6c: 6811 ldr r1, [r2, #0]
|
|
|
+ 8010d6e: 400b ands r3, r1
|
|
|
+ 8010d70: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
+ 8010d74: d10a bne.n 8010d8c <main+0x78>
|
|
|
{
|
|
|
JumpAdd = *(__IO uint32_t*) (USER_FLASH_FIRST_PAGE_ADDRESS + 4);
|
|
|
- 8010dfe: 4b59 ldr r3, [pc, #356] ; (8010f64 <main+0x1c8>)
|
|
|
- 8010e00: 4959 ldr r1, [pc, #356] ; (8010f68 <main+0x1cc>)
|
|
|
- 8010e02: 681b ldr r3, [r3, #0]
|
|
|
- 8010e04: 600b str r3, [r1, #0]
|
|
|
+ 8010d76: 4b59 ldr r3, [pc, #356] ; (8010edc <main+0x1c8>)
|
|
|
+ 8010d78: 4959 ldr r1, [pc, #356] ; (8010ee0 <main+0x1cc>)
|
|
|
+ 8010d7a: 681b ldr r3, [r3, #0]
|
|
|
+ 8010d7c: 600b str r3, [r1, #0]
|
|
|
Jump_To_App = (pFunction) JumpAdd;
|
|
|
- 8010e06: 4959 ldr r1, [pc, #356] ; (8010f6c <main+0x1d0>)
|
|
|
+ 8010d7e: 4959 ldr r1, [pc, #356] ; (8010ee4 <main+0x1d0>)
|
|
|
__set_MSP(*(__IO uint32_t*) USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
- 8010e08: 6812 ldr r2, [r2, #0]
|
|
|
+ 8010d80: 6812 ldr r2, [r2, #0]
|
|
|
|
|
|
/* Check if valid stack address (RAM address) then jump to user application */
|
|
|
if (((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) & 0x2FFE0000 ) == 0x20000000)
|
|
|
{
|
|
|
JumpAdd = *(__IO uint32_t*) (USER_FLASH_FIRST_PAGE_ADDRESS + 4);
|
|
|
Jump_To_App = (pFunction) JumpAdd;
|
|
|
- 8010e0a: 600b str r3, [r1, #0]
|
|
|
+ 8010d82: 600b str r3, [r1, #0]
|
|
|
|
|
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
|
|
*/
|
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
|
|
{
|
|
|
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
|
|
- 8010e0c: f382 8808 msr MSP, r2
|
|
|
+ 8010d84: f382 8808 msr MSP, r2
|
|
|
__set_MSP(*(__IO uint32_t*) USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
Jump_To_App();
|
|
|
- 8010e10: 4798 blx r3
|
|
|
- 8010e12: e00f b.n 8010e34 <main+0x98>
|
|
|
+ 8010d88: 4798 blx r3
|
|
|
+ 8010d8a: e00f b.n 8010dac <main+0x98>
|
|
|
}
|
|
|
else {
|
|
|
/* Флеш пустая, нечего загружать, висим в аварийном режиме */
|
|
|
fInvalidFw = 1;
|
|
|
- 8010e14: 4b56 ldr r3, [pc, #344] ; (8010f70 <main+0x1d4>)
|
|
|
- 8010e16: 2201 movs r2, #1
|
|
|
- 8010e18: 701a strb r2, [r3, #0]
|
|
|
- 8010e1a: e00b b.n 8010e34 <main+0x98>
|
|
|
+ 8010d8c: 4b56 ldr r3, [pc, #344] ; (8010ee8 <main+0x1d4>)
|
|
|
+ 8010d8e: 2201 movs r2, #1
|
|
|
+ 8010d90: 701a strb r2, [r3, #0]
|
|
|
+ 8010d92: e00b b.n 8010dac <main+0x98>
|
|
|
PRINT_USART("\n\rFW empty. Started bootloader\n\r");
|
|
|
}
|
|
|
}
|
|
|
else if (bootTry == 1)
|
|
|
- 8010e1c: d10a bne.n 8010e34 <main+0x98>
|
|
|
+ 8010d94: d10a bne.n 8010dac <main+0x98>
|
|
|
{
|
|
|
fBootFailed = 1;
|
|
|
- 8010e1e: 4b55 ldr r3, [pc, #340] ; (8010f74 <main+0x1d8>)
|
|
|
+ 8010d96: 4b55 ldr r3, [pc, #340] ; (8010eec <main+0x1d8>)
|
|
|
PRINT_USART("\n\rFW boot failed. Started bootloader\n\r");
|
|
|
|
|
|
bootTry = 0;
|
|
|
loadMode = 1;
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010e20: 2002 movs r0, #2
|
|
|
- 8010e22: 2100 movs r1, #0
|
|
|
+ 8010d98: 2002 movs r0, #2
|
|
|
+ 8010d9a: 2100 movs r1, #0
|
|
|
PRINT_USART("\n\rFW empty. Started bootloader\n\r");
|
|
|
}
|
|
|
}
|
|
|
else if (bootTry == 1)
|
|
|
{
|
|
|
fBootFailed = 1;
|
|
|
- 8010e24: 701c strb r4, [r3, #0]
|
|
|
+ 8010d9c: 701c strb r4, [r3, #0]
|
|
|
PRINT_USART("\n\rFW boot failed. Started bootloader\n\r");
|
|
|
|
|
|
bootTry = 0;
|
|
|
loadMode = 1;
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010e26: f7f9 f8e5 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010d9e: f7f9 f929 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR1, loadMode);
|
|
|
- 8010e2a: 4620 mov r0, r4
|
|
|
- 8010e2c: 4621 mov r1, r4
|
|
|
- 8010e2e: f7f9 f8e1 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
- 8010e32: e018 b.n 8010e66 <main+0xca>
|
|
|
+ 8010da2: 4620 mov r0, r4
|
|
|
+ 8010da4: 4621 mov r1, r4
|
|
|
+ 8010da6: f7f9 f925 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010daa: e018 b.n 8010dde <main+0xca>
|
|
|
}
|
|
|
|
|
|
/* Флаг не установлен прыгаем на основную программу */
|
|
|
if (loadMode == 0)
|
|
|
- 8010e34: b9bd cbnz r5, 8010e66 <main+0xca>
|
|
|
+ 8010dac: b9bd cbnz r5, 8010dde <main+0xca>
|
|
|
{
|
|
|
printf("Run main FW\n\r");
|
|
|
- 8010e36: 4850 ldr r0, [pc, #320] ; (8010f78 <main+0x1dc>)
|
|
|
- 8010e38: f000 fc1c bl 8011674 <tfp_printf>
|
|
|
+ 8010dae: 4850 ldr r0, [pc, #320] ; (8010ef0 <main+0x1dc>)
|
|
|
+ 8010db0: f000 fc1c bl 80115ec <tfp_printf>
|
|
|
//printf("*(__IO uint32_t*)(USER_FLASH_FIRST_PAGE_ADDRESS + 4) = 0x%X\n\r", *(__IO uint32_t*)(USER_FLASH_FIRST_PAGE_ADDRESS + 4));
|
|
|
|
|
|
/* Set bootTry flag every time to ensure that
|
|
|
* IAP will starts again if FW is corrupted */
|
|
|
bootTry = BOOT_TRY;
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010e3c: 2106 movs r1, #6
|
|
|
- 8010e3e: 2002 movs r0, #2
|
|
|
- 8010e40: f7f9 f8d8 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010db4: 2106 movs r1, #6
|
|
|
+ 8010db6: 2002 movs r0, #2
|
|
|
+ 8010db8: f7f9 f91c bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
|
|
|
/* Check if valid stack address (RAM address) then jump to user application */
|
|
|
if (((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) & 0x2FFE0000 ) == 0x20000000)
|
|
|
- 8010e44: 4a45 ldr r2, [pc, #276] ; (8010f5c <main+0x1c0>)
|
|
|
- 8010e46: 4b46 ldr r3, [pc, #280] ; (8010f60 <main+0x1c4>)
|
|
|
- 8010e48: 6811 ldr r1, [r2, #0]
|
|
|
- 8010e4a: 400b ands r3, r1
|
|
|
- 8010e4c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
- 8010e50: d109 bne.n 8010e66 <main+0xca>
|
|
|
+ 8010dbc: 4a45 ldr r2, [pc, #276] ; (8010ed4 <main+0x1c0>)
|
|
|
+ 8010dbe: 4b46 ldr r3, [pc, #280] ; (8010ed8 <main+0x1c4>)
|
|
|
+ 8010dc0: 6811 ldr r1, [r2, #0]
|
|
|
+ 8010dc2: 400b ands r3, r1
|
|
|
+ 8010dc4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
+ 8010dc8: d109 bne.n 8010dde <main+0xca>
|
|
|
{
|
|
|
/* Jump to user application */
|
|
|
JumpAdd = *(__IO uint32_t*) (USER_FLASH_FIRST_PAGE_ADDRESS + 4);
|
|
|
- 8010e52: 4b44 ldr r3, [pc, #272] ; (8010f64 <main+0x1c8>)
|
|
|
- 8010e54: 4944 ldr r1, [pc, #272] ; (8010f68 <main+0x1cc>)
|
|
|
- 8010e56: 681b ldr r3, [r3, #0]
|
|
|
- 8010e58: 600b str r3, [r1, #0]
|
|
|
+ 8010dca: 4b44 ldr r3, [pc, #272] ; (8010edc <main+0x1c8>)
|
|
|
+ 8010dcc: 4944 ldr r1, [pc, #272] ; (8010ee0 <main+0x1cc>)
|
|
|
+ 8010dce: 681b ldr r3, [r3, #0]
|
|
|
+ 8010dd0: 600b str r3, [r1, #0]
|
|
|
Jump_To_App = (pFunction) JumpAdd;
|
|
|
- 8010e5a: 4944 ldr r1, [pc, #272] ; (8010f6c <main+0x1d0>)
|
|
|
+ 8010dd2: 4944 ldr r1, [pc, #272] ; (8010ee4 <main+0x1d0>)
|
|
|
/* Initialize user application's Stack Pointer */
|
|
|
__set_MSP(*(__IO uint32_t*) USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
- 8010e5c: 6812 ldr r2, [r2, #0]
|
|
|
+ 8010dd4: 6812 ldr r2, [r2, #0]
|
|
|
/* Check if valid stack address (RAM address) then jump to user application */
|
|
|
if (((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) & 0x2FFE0000 ) == 0x20000000)
|
|
|
{
|
|
|
/* Jump to user application */
|
|
|
JumpAdd = *(__IO uint32_t*) (USER_FLASH_FIRST_PAGE_ADDRESS + 4);
|
|
|
Jump_To_App = (pFunction) JumpAdd;
|
|
|
- 8010e5e: 600b str r3, [r1, #0]
|
|
|
- 8010e60: f382 8808 msr MSP, r2
|
|
|
+ 8010dd6: 600b str r3, [r1, #0]
|
|
|
+ 8010dd8: f382 8808 msr MSP, r2
|
|
|
/* Initialize user application's Stack Pointer */
|
|
|
__set_MSP(*(__IO uint32_t*) USER_FLASH_FIRST_PAGE_ADDRESS);
|
|
|
Jump_To_App();
|
|
|
- 8010e64: 4798 blx r3
|
|
|
+ 8010ddc: 4798 blx r3
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
|
{
|
|
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
|
|
|
|
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
|
|
- 8010e66: 4b45 ldr r3, [pc, #276] ; (8010f7c <main+0x1e0>)
|
|
|
- 8010e68: 4a45 ldr r2, [pc, #276] ; (8010f80 <main+0x1e4>)
|
|
|
- 8010e6a: 605a str r2, [r3, #4]
|
|
|
+ 8010dde: 4b45 ldr r3, [pc, #276] ; (8010ef4 <main+0x1e0>)
|
|
|
+ 8010de0: 4a45 ldr r2, [pc, #276] ; (8010ef8 <main+0x1e4>)
|
|
|
+ 8010de2: 605a str r2, [r3, #4]
|
|
|
\param [in] priority Priority to set.
|
|
|
*/
|
|
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
{
|
|
|
if(IRQn < 0) {
|
|
|
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
|
|
|
- 8010e6c: 4a45 ldr r2, [pc, #276] ; (8010f84 <main+0x1e8>)
|
|
|
- 8010e6e: 21f0 movs r1, #240 ; 0xf0
|
|
|
- 8010e70: f882 1023 strb.w r1, [r2, #35] ; 0x23
|
|
|
+ 8010de4: 4a45 ldr r2, [pc, #276] ; (8010efc <main+0x1e8>)
|
|
|
+ 8010de6: 21f0 movs r1, #240 ; 0xf0
|
|
|
+ 8010de8: f882 1023 strb.w r1, [r2, #35] ; 0x23
|
|
|
{
|
|
|
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
|
|
|
|
|
SysTick->LOAD = ticks - 1; /* set reload register */
|
|
|
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
|
|
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
|
|
- 8010e74: 2200 movs r2, #0
|
|
|
- 8010e76: 609a str r2, [r3, #8]
|
|
|
+ 8010dec: 2200 movs r2, #0
|
|
|
+ 8010dee: 609a str r2, [r3, #8]
|
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
|
- 8010e78: 2207 movs r2, #7
|
|
|
- 8010e7a: 601a str r2, [r3, #0]
|
|
|
+ 8010df0: 2207 movs r2, #7
|
|
|
+ 8010df2: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Загружается Bootloader... */
|
|
|
|
|
|
SysTick_Config(120000);
|
|
|
LED_Init();
|
|
|
- 8010e7c: f7fe fc84 bl 800f788 <LED_Init>
|
|
|
+ 8010df4: f7fe fcc8 bl 800f788 <LED_Init>
|
|
|
|
|
|
|
|
|
PRINT_USART("\n\rBootloader starting... \n\r");
|
|
|
|
|
|
LED_On(RED_STATUS);
|
|
|
- 8010e80: 2001 movs r0, #1
|
|
|
- 8010e82: f7fe fc65 bl 800f750 <LED_On>
|
|
|
+ 8010df8: 2001 movs r0, #1
|
|
|
+ 8010dfa: f7fe fca9 bl 800f750 <LED_On>
|
|
|
|
|
|
ETH_BSP_Config();
|
|
|
- 8010e86: f7ff fb03 bl 8010490 <ETH_BSP_Config>
|
|
|
+ 8010dfe: f7ff fb03 bl 8010408 <ETH_BSP_Config>
|
|
|
LwIP_Init();
|
|
|
- 8010e8a: f7ff fa61 bl 8010350 <LwIP_Init>
|
|
|
+ 8010e02: f7ff fa61 bl 80102c8 <LwIP_Init>
|
|
|
IAP_httpd_init();
|
|
|
- 8010e8e: f7ff fa49 bl 8010324 <IAP_httpd_init>
|
|
|
+ 8010e06: f7ff fa49 bl 801029c <IAP_httpd_init>
|
|
|
CRC_Init();
|
|
|
- 8010e92: f7fe fbb3 bl 800f5fc <CRC_Init>
|
|
|
+ 8010e0a: f7fe fbf7 bl 800f5fc <CRC_Init>
|
|
|
|
|
|
//Если нажата DEF начинаем обновление с sd
|
|
|
if (IO_BtnDefaultPressed())
|
|
|
- 8010e96: f7fe fc4d bl 800f734 <IO_BtnDefaultPressed>
|
|
|
- 8010e9a: b938 cbnz r0, 8010eac <main+0x110>
|
|
|
+ 8010e0e: f7fe fc91 bl 800f734 <IO_BtnDefaultPressed>
|
|
|
+ 8010e12: b938 cbnz r0, 8010e24 <main+0x110>
|
|
|
{
|
|
|
// IAPviaETH = false;
|
|
|
// timer_AddFunction(500, &LED_Blinky_Yellow);
|
|
|
// SD_NVIC_Init();
|
|
|
} else {
|
|
|
IAPviaETH = true;
|
|
|
- 8010e9c: 4b3a ldr r3, [pc, #232] ; (8010f88 <main+0x1ec>)
|
|
|
+ 8010e14: 4b3a ldr r3, [pc, #232] ; (8010f00 <main+0x1ec>)
|
|
|
timer_AddFunction(500, &LED_Blinky_Green);
|
|
|
- 8010e9e: 493b ldr r1, [pc, #236] ; (8010f8c <main+0x1f0>)
|
|
|
+ 8010e16: 493b ldr r1, [pc, #236] ; (8010f04 <main+0x1f0>)
|
|
|
{
|
|
|
// IAPviaETH = false;
|
|
|
// timer_AddFunction(500, &LED_Blinky_Yellow);
|
|
|
// SD_NVIC_Init();
|
|
|
} else {
|
|
|
IAPviaETH = true;
|
|
|
- 8010ea0: 2201 movs r2, #1
|
|
|
+ 8010e18: 2201 movs r2, #1
|
|
|
timer_AddFunction(500, &LED_Blinky_Green);
|
|
|
- 8010ea2: f44f 70fa mov.w r0, #500 ; 0x1f4
|
|
|
+ 8010e1a: f44f 70fa mov.w r0, #500 ; 0x1f4
|
|
|
{
|
|
|
// IAPviaETH = false;
|
|
|
// timer_AddFunction(500, &LED_Blinky_Yellow);
|
|
|
// SD_NVIC_Init();
|
|
|
} else {
|
|
|
IAPviaETH = true;
|
|
|
- 8010ea6: 701a strb r2, [r3, #0]
|
|
|
+ 8010e1e: 701a strb r2, [r3, #0]
|
|
|
timer_AddFunction(500, &LED_Blinky_Green);
|
|
|
- 8010ea8: f7fe fe08 bl 800fabc <timer_AddFunction>
|
|
|
+ 8010e20: f7fe fe08 bl 800fa34 <timer_AddFunction>
|
|
|
}
|
|
|
|
|
|
/* Check if valid stack address (RAM address) */
|
|
|
if (((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) & 0x2FFE0000 ) == 0x20000000) {
|
|
|
- 8010eac: 4b2b ldr r3, [pc, #172] ; (8010f5c <main+0x1c0>)
|
|
|
- 8010eae: 681a ldr r2, [r3, #0]
|
|
|
- 8010eb0: 4b2b ldr r3, [pc, #172] ; (8010f60 <main+0x1c4>)
|
|
|
- 8010eb2: 4013 ands r3, r2
|
|
|
- 8010eb4: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
- 8010eb8: d105 bne.n 8010ec6 <main+0x12a>
|
|
|
+ 8010e24: 4b2b ldr r3, [pc, #172] ; (8010ed4 <main+0x1c0>)
|
|
|
+ 8010e26: 681a ldr r2, [r3, #0]
|
|
|
+ 8010e28: 4b2b ldr r3, [pc, #172] ; (8010ed8 <main+0x1c4>)
|
|
|
+ 8010e2a: 4013 ands r3, r2
|
|
|
+ 8010e2c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
|
+ 8010e30: d105 bne.n 8010e3e <main+0x12a>
|
|
|
timer_AddFunction(1000, &UpdateTimeout_Handler);
|
|
|
- 8010eba: f44f 707a mov.w r0, #1000 ; 0x3e8
|
|
|
- 8010ebe: 4934 ldr r1, [pc, #208] ; (8010f90 <main+0x1f4>)
|
|
|
- 8010ec0: f7fe fdfc bl 800fabc <timer_AddFunction>
|
|
|
- 8010ec4: e002 b.n 8010ecc <main+0x130>
|
|
|
+ 8010e32: f44f 707a mov.w r0, #1000 ; 0x3e8
|
|
|
+ 8010e36: 4934 ldr r1, [pc, #208] ; (8010f08 <main+0x1f4>)
|
|
|
+ 8010e38: f7fe fdfc bl 800fa34 <timer_AddFunction>
|
|
|
+ 8010e3c: e002 b.n 8010e44 <main+0x130>
|
|
|
}
|
|
|
else {
|
|
|
/* Флеш пустая, нечего загружать, висим в аварийном режиме */
|
|
|
fInvalidFw = 1;
|
|
|
- 8010ec6: 4b2a ldr r3, [pc, #168] ; (8010f70 <main+0x1d4>)
|
|
|
- 8010ec8: 2201 movs r2, #1
|
|
|
- 8010eca: 701a strb r2, [r3, #0]
|
|
|
+ 8010e3e: 4b2a ldr r3, [pc, #168] ; (8010ee8 <main+0x1d4>)
|
|
|
+ 8010e40: 2201 movs r2, #1
|
|
|
+ 8010e42: 701a strb r2, [r3, #0]
|
|
|
|
|
|
while (1)
|
|
|
{
|
|
|
timer_Main();
|
|
|
|
|
|
if (IAPviaETH) { // Обновление по ETH
|
|
|
- 8010ecc: 4c2e ldr r4, [pc, #184] ; (8010f88 <main+0x1ec>)
|
|
|
+ 8010e44: 4c2e ldr r4, [pc, #184] ; (8010f00 <main+0x1ec>)
|
|
|
{
|
|
|
/* process received ethernet packet */
|
|
|
LwIP_Pkt_Handle();
|
|
|
}
|
|
|
/* handle periodic timers for LwIP */
|
|
|
LwIP_Periodic_Handle(LocalTime);
|
|
|
- 8010ece: 4d31 ldr r5, [pc, #196] ; (8010f94 <main+0x1f8>)
|
|
|
+ 8010e46: 4d31 ldr r5, [pc, #196] ; (8010f0c <main+0x1f8>)
|
|
|
|
|
|
if (fDoneReset)
|
|
|
- 8010ed0: 4e31 ldr r6, [pc, #196] ; (8010f98 <main+0x1fc>)
|
|
|
+ 8010e48: 4e31 ldr r6, [pc, #196] ; (8010f10 <main+0x1fc>)
|
|
|
}
|
|
|
|
|
|
|
|
|
while (1)
|
|
|
{
|
|
|
timer_Main();
|
|
|
- 8010ed2: f7fe fe11 bl 800faf8 <timer_Main>
|
|
|
+ 8010e4a: f7fe fe11 bl 800fa70 <timer_Main>
|
|
|
|
|
|
if (IAPviaETH) { // Обновление по ETH
|
|
|
- 8010ed6: 7823 ldrb r3, [r4, #0]
|
|
|
- 8010ed8: b333 cbz r3, 8010f28 <main+0x18c>
|
|
|
+ 8010e4e: 7823 ldrb r3, [r4, #0]
|
|
|
+ 8010e50: b333 cbz r3, 8010ea0 <main+0x18c>
|
|
|
/* check if any packet received */
|
|
|
if (ETH_CheckFrameReceived())
|
|
|
- 8010eda: f7ff fcf1 bl 80108c0 <ETH_CheckFrameReceived>
|
|
|
- 8010ede: b108 cbz r0, 8010ee4 <main+0x148>
|
|
|
+ 8010e52: f7ff fcf1 bl 8010838 <ETH_CheckFrameReceived>
|
|
|
+ 8010e56: b108 cbz r0, 8010e5c <main+0x148>
|
|
|
{
|
|
|
/* process received ethernet packet */
|
|
|
LwIP_Pkt_Handle();
|
|
|
- 8010ee0: f7ff fa76 bl 80103d0 <LwIP_Pkt_Handle>
|
|
|
+ 8010e58: f7ff fa76 bl 8010348 <LwIP_Pkt_Handle>
|
|
|
}
|
|
|
/* handle periodic timers for LwIP */
|
|
|
LwIP_Periodic_Handle(LocalTime);
|
|
|
- 8010ee4: 6828 ldr r0, [r5, #0]
|
|
|
- 8010ee6: f7ff fabd bl 8010464 <LwIP_Periodic_Handle>
|
|
|
+ 8010e5c: 6828 ldr r0, [r5, #0]
|
|
|
+ 8010e5e: f7ff fabd bl 80103dc <LwIP_Periodic_Handle>
|
|
|
|
|
|
if (fDoneReset)
|
|
|
- 8010eea: 7833 ldrb r3, [r6, #0]
|
|
|
- 8010eec: b18b cbz r3, 8010f12 <main+0x176>
|
|
|
+ 8010e62: 7833 ldrb r3, [r6, #0]
|
|
|
+ 8010e64: b18b cbz r3, 8010e8a <main+0x176>
|
|
|
{
|
|
|
resetCounter++;
|
|
|
- 8010eee: 4a2b ldr r2, [pc, #172] ; (8010f9c <main+0x200>)
|
|
|
- 8010ef0: 6813 ldr r3, [r2, #0]
|
|
|
- 8010ef2: 3301 adds r3, #1
|
|
|
- 8010ef4: 6013 str r3, [r2, #0]
|
|
|
+ 8010e66: 4a2b ldr r2, [pc, #172] ; (8010f14 <main+0x200>)
|
|
|
+ 8010e68: 6813 ldr r3, [r2, #0]
|
|
|
+ 8010e6a: 3301 adds r3, #1
|
|
|
+ 8010e6c: 6013 str r3, [r2, #0]
|
|
|
if (resetCounter > 100000)
|
|
|
- 8010ef6: 4a2a ldr r2, [pc, #168] ; (8010fa0 <main+0x204>)
|
|
|
- 8010ef8: 4293 cmp r3, r2
|
|
|
- 8010efa: d90a bls.n 8010f12 <main+0x176>
|
|
|
+ 8010e6e: 4a2a ldr r2, [pc, #168] ; (8010f18 <main+0x204>)
|
|
|
+ 8010e70: 4293 cmp r3, r2
|
|
|
+ 8010e72: d90a bls.n 8010e8a <main+0x176>
|
|
|
{
|
|
|
loadMode = 0;
|
|
|
bootTry = BOOT_TRY;
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR1, loadMode);
|
|
|
- 8010efc: 2001 movs r0, #1
|
|
|
- 8010efe: 2100 movs r1, #0
|
|
|
- 8010f00: f7f9 f878 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010e74: 2001 movs r0, #1
|
|
|
+ 8010e76: 2100 movs r1, #0
|
|
|
+ 8010e78: f7f9 f8bc bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010f04: 2002 movs r0, #2
|
|
|
- 8010f06: 2106 movs r1, #6
|
|
|
- 8010f08: f7f9 f874 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010e7c: 2002 movs r0, #2
|
|
|
+ 8010e7e: 2106 movs r1, #6
|
|
|
+ 8010e80: f7f9 f8b8 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
/* Set FW update flag */
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR3, 1);
|
|
|
- 8010f0c: 2003 movs r0, #3
|
|
|
- 8010f0e: 2101 movs r1, #1
|
|
|
- 8010f10: e01e b.n 8010f50 <main+0x1b4>
|
|
|
+ 8010e84: 2003 movs r0, #3
|
|
|
+ 8010e86: 2101 movs r1, #1
|
|
|
+ 8010e88: e01e b.n 8010ec8 <main+0x1b4>
|
|
|
|
|
|
NVIC_SystemReset();
|
|
|
}
|
|
|
}
|
|
|
if (fErrorReset)
|
|
|
- 8010f12: 4b24 ldr r3, [pc, #144] ; (8010fa4 <main+0x208>)
|
|
|
- 8010f14: 781b ldrb r3, [r3, #0]
|
|
|
- 8010f16: b13b cbz r3, 8010f28 <main+0x18c>
|
|
|
+ 8010e8a: 4b24 ldr r3, [pc, #144] ; (8010f1c <main+0x208>)
|
|
|
+ 8010e8c: 781b ldrb r3, [r3, #0]
|
|
|
+ 8010e8e: b13b cbz r3, 8010ea0 <main+0x18c>
|
|
|
{
|
|
|
resetCounter++;
|
|
|
- 8010f18: 4a20 ldr r2, [pc, #128] ; (8010f9c <main+0x200>)
|
|
|
- 8010f1a: 6813 ldr r3, [r2, #0]
|
|
|
- 8010f1c: 3301 adds r3, #1
|
|
|
- 8010f1e: 6013 str r3, [r2, #0]
|
|
|
+ 8010e90: 4a20 ldr r2, [pc, #128] ; (8010f14 <main+0x200>)
|
|
|
+ 8010e92: 6813 ldr r3, [r2, #0]
|
|
|
+ 8010e94: 3301 adds r3, #1
|
|
|
+ 8010e96: 6013 str r3, [r2, #0]
|
|
|
if (resetCounter > 100000) {
|
|
|
- 8010f20: 4a1f ldr r2, [pc, #124] ; (8010fa0 <main+0x204>)
|
|
|
- 8010f22: 4293 cmp r3, r2
|
|
|
- 8010f24: d900 bls.n 8010f28 <main+0x18c>
|
|
|
- 8010f26: e015 b.n 8010f54 <main+0x1b8>
|
|
|
+ 8010e98: 4a1f ldr r2, [pc, #124] ; (8010f18 <main+0x204>)
|
|
|
+ 8010e9a: 4293 cmp r3, r2
|
|
|
+ 8010e9c: d900 bls.n 8010ea0 <main+0x18c>
|
|
|
+ 8010e9e: e015 b.n 8010ecc <main+0x1b8>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
//Если нажата DEF переходим в основную прошивку
|
|
|
if (IO_BtnDefaultPressed() || UpdateTimeoutFlag)
|
|
|
- 8010f28: f7fe fc04 bl 800f734 <IO_BtnDefaultPressed>
|
|
|
- 8010f2c: b918 cbnz r0, 8010f36 <main+0x19a>
|
|
|
- 8010f2e: 4b1e ldr r3, [pc, #120] ; (8010fa8 <main+0x20c>)
|
|
|
- 8010f30: 781b ldrb r3, [r3, #0]
|
|
|
- 8010f32: 2b00 cmp r3, #0
|
|
|
- 8010f34: d0cd beq.n 8010ed2 <main+0x136>
|
|
|
+ 8010ea0: f7fe fc48 bl 800f734 <IO_BtnDefaultPressed>
|
|
|
+ 8010ea4: b918 cbnz r0, 8010eae <main+0x19a>
|
|
|
+ 8010ea6: 4b1e ldr r3, [pc, #120] ; (8010f20 <main+0x20c>)
|
|
|
+ 8010ea8: 781b ldrb r3, [r3, #0]
|
|
|
+ 8010eaa: 2b00 cmp r3, #0
|
|
|
+ 8010eac: d0cd beq.n 8010e4a <main+0x136>
|
|
|
{
|
|
|
if (!fUpload && ((*(__IO uint32_t*)USER_FLASH_FIRST_PAGE_ADDRESS) != 0xFFFFFFFF)) {
|
|
|
- 8010f36: 4b1d ldr r3, [pc, #116] ; (8010fac <main+0x210>)
|
|
|
- 8010f38: 7819 ldrb r1, [r3, #0]
|
|
|
- 8010f3a: 2900 cmp r1, #0
|
|
|
- 8010f3c: d1c9 bne.n 8010ed2 <main+0x136>
|
|
|
- 8010f3e: 4b07 ldr r3, [pc, #28] ; (8010f5c <main+0x1c0>)
|
|
|
- 8010f40: 681b ldr r3, [r3, #0]
|
|
|
- 8010f42: 3301 adds r3, #1
|
|
|
- 8010f44: d0c5 beq.n 8010ed2 <main+0x136>
|
|
|
+ 8010eae: 4b1d ldr r3, [pc, #116] ; (8010f24 <main+0x210>)
|
|
|
+ 8010eb0: 7819 ldrb r1, [r3, #0]
|
|
|
+ 8010eb2: 2900 cmp r1, #0
|
|
|
+ 8010eb4: d1c9 bne.n 8010e4a <main+0x136>
|
|
|
+ 8010eb6: 4b07 ldr r3, [pc, #28] ; (8010ed4 <main+0x1c0>)
|
|
|
+ 8010eb8: 681b ldr r3, [r3, #0]
|
|
|
+ 8010eba: 3301 adds r3, #1
|
|
|
+ 8010ebc: d0c5 beq.n 8010e4a <main+0x136>
|
|
|
PRINT_USART("\n\rUpdate timeout... Return to main FW\n\r");
|
|
|
loadMode = 0;
|
|
|
bootTry = BOOT_TRY;
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR1, loadMode);
|
|
|
- 8010f46: 2001 movs r0, #1
|
|
|
- 8010f48: f7f9 f854 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010ebe: 2001 movs r0, #1
|
|
|
+ 8010ec0: f7f9 f898 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
RTC_WriteBackupRegister(RTC_BKP_DR2, bootTry);
|
|
|
- 8010f4c: 2002 movs r0, #2
|
|
|
- 8010f4e: 2106 movs r1, #6
|
|
|
- 8010f50: f7f9 f850 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
+ 8010ec4: 2002 movs r0, #2
|
|
|
+ 8010ec6: 2106 movs r1, #6
|
|
|
+ 8010ec8: f7f9 f894 bl 8009ff4 <RTC_WriteBackupRegister>
|
|
|
NVIC_SystemReset();
|
|
|
- 8010f54: f7ff fefa bl 8010d4c <NVIC_SystemReset>
|
|
|
- 8010f58: 0801363f .word 0x0801363f
|
|
|
- 8010f5c: 08020000 .word 0x08020000
|
|
|
- 8010f60: 2ffe0000 .word 0x2ffe0000
|
|
|
- 8010f64: 08020004 .word 0x08020004
|
|
|
- 8010f68: 2000c998 .word 0x2000c998
|
|
|
- 8010f6c: 2000c994 .word 0x2000c994
|
|
|
- 8010f70: 20006dc4 .word 0x20006dc4
|
|
|
- 8010f74: 20006dba .word 0x20006dba
|
|
|
- 8010f78: 0801365b .word 0x0801365b
|
|
|
- 8010f7c: e000e010 .word 0xe000e010
|
|
|
- 8010f80: 0001d4bf .word 0x0001d4bf
|
|
|
- 8010f84: e000ed00 .word 0xe000ed00
|
|
|
- 8010f88: 20006db8 .word 0x20006db8
|
|
|
- 8010f8c: 0800f7f5 .word 0x0800f7f5
|
|
|
- 8010f90: 08010d6d .word 0x08010d6d
|
|
|
- 8010f94: 20006db4 .word 0x20006db4
|
|
|
- 8010f98: 20006dbc .word 0x20006dbc
|
|
|
- 8010f9c: 20006dc0 .word 0x20006dc0
|
|
|
- 8010fa0: 000186a0 .word 0x000186a0
|
|
|
- 8010fa4: 20006dbb .word 0x20006dbb
|
|
|
- 8010fa8: 20006db9 .word 0x20006db9
|
|
|
- 8010fac: 20006db0 .word 0x20006db0
|
|
|
-
|
|
|
-08010fb0 <Time_Update>:
|
|
|
+ 8010ecc: f7ff fefa bl 8010cc4 <NVIC_SystemReset>
|
|
|
+ 8010ed0: 0801359f .word 0x0801359f
|
|
|
+ 8010ed4: 08020000 .word 0x08020000
|
|
|
+ 8010ed8: 2ffe0000 .word 0x2ffe0000
|
|
|
+ 8010edc: 08020004 .word 0x08020004
|
|
|
+ 8010ee0: 2000c7d4 .word 0x2000c7d4
|
|
|
+ 8010ee4: 2000c7d0 .word 0x2000c7d0
|
|
|
+ 8010ee8: 20006dc4 .word 0x20006dc4
|
|
|
+ 8010eec: 20006dbb .word 0x20006dbb
|
|
|
+ 8010ef0: 080135bb .word 0x080135bb
|
|
|
+ 8010ef4: e000e010 .word 0xe000e010
|
|
|
+ 8010ef8: 0001d4bf .word 0x0001d4bf
|
|
|
+ 8010efc: e000ed00 .word 0xe000ed00
|
|
|
+ 8010f00: 20006db9 .word 0x20006db9
|
|
|
+ 8010f04: 0800f7f5 .word 0x0800f7f5
|
|
|
+ 8010f08: 08010ce5 .word 0x08010ce5
|
|
|
+ 8010f0c: 20006db4 .word 0x20006db4
|
|
|
+ 8010f10: 20006dbc .word 0x20006dbc
|
|
|
+ 8010f14: 20006dc0 .word 0x20006dc0
|
|
|
+ 8010f18: 000186a0 .word 0x000186a0
|
|
|
+ 8010f1c: 20006db8 .word 0x20006db8
|
|
|
+ 8010f20: 20006dba .word 0x20006dba
|
|
|
+ 8010f24: 20006db0 .word 0x20006db0
|
|
|
+
|
|
|
+08010f28 <Time_Update>:
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void Time_Update(void)
|
|
|
{
|
|
|
LocalTime += SYSTEMTICK_PERIOD_MS;
|
|
|
- 8010fb0: 4b02 ldr r3, [pc, #8] ; (8010fbc <Time_Update+0xc>)
|
|
|
- 8010fb2: 681a ldr r2, [r3, #0]
|
|
|
- 8010fb4: 3201 adds r2, #1
|
|
|
- 8010fb6: 601a str r2, [r3, #0]
|
|
|
- 8010fb8: 4770 bx lr
|
|
|
- 8010fba: bf00 nop
|
|
|
- 8010fbc: 20006db4 .word 0x20006db4
|
|
|
+ 8010f28: 4b02 ldr r3, [pc, #8] ; (8010f34 <Time_Update+0xc>)
|
|
|
+ 8010f2a: 681a ldr r2, [r3, #0]
|
|
|
+ 8010f2c: 3201 adds r2, #1
|
|
|
+ 8010f2e: 601a str r2, [r3, #0]
|
|
|
+ 8010f30: 4770 bx lr
|
|
|
+ 8010f32: bf00 nop
|
|
|
+ 8010f34: 20006db4 .word 0x20006db4
|
|
|
|
|
|
-08010fc0 <sys_now>:
|
|
|
+08010f38 <sys_now>:
|
|
|
|
|
|
/**
|
|
|
* @brief
|
|
|
*/
|
|
|
u32_t sys_now(void) {
|
|
|
return LocalTime;
|
|
|
- 8010fc0: 4b01 ldr r3, [pc, #4] ; (8010fc8 <sys_now+0x8>)
|
|
|
- 8010fc2: 6818 ldr r0, [r3, #0]
|
|
|
+ 8010f38: 4b01 ldr r3, [pc, #4] ; (8010f40 <sys_now+0x8>)
|
|
|
+ 8010f3a: 6818 ldr r0, [r3, #0]
|
|
|
}
|
|
|
- 8010fc4: 4770 bx lr
|
|
|
- 8010fc6: bf00 nop
|
|
|
- 8010fc8: 20006db4 .word 0x20006db4
|
|
|
+ 8010f3c: 4770 bx lr
|
|
|
+ 8010f3e: bf00 nop
|
|
|
+ 8010f40: 20006db4 .word 0x20006db4
|
|
|
|
|
|
-08010fcc <NMI_Handler>:
|
|
|
+08010f44 <NMI_Handler>:
|
|
|
* @brief This function handles NMI exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void NMI_Handler(void)
|
|
|
{
|
|
|
- 8010fcc: 4770 bx lr
|
|
|
+ 8010f44: 4770 bx lr
|
|
|
|
|
|
-08010fce <HardFault_Handler>:
|
|
|
+08010f46 <HardFault_Handler>:
|
|
|
* @brief This function handles Hard Fault exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HardFault_Handler(void)
|
|
|
{
|
|
|
- 8010fce: e7fe b.n 8010fce <HardFault_Handler>
|
|
|
+ 8010f46: e7fe b.n 8010f46 <HardFault_Handler>
|
|
|
|
|
|
-08010fd0 <MemManage_Handler>:
|
|
|
+08010f48 <MemManage_Handler>:
|
|
|
* @brief This function handles Memory Manage exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void MemManage_Handler(void)
|
|
|
{
|
|
|
- 8010fd0: e7fe b.n 8010fd0 <MemManage_Handler>
|
|
|
+ 8010f48: e7fe b.n 8010f48 <MemManage_Handler>
|
|
|
|
|
|
-08010fd2 <BusFault_Handler>:
|
|
|
+08010f4a <BusFault_Handler>:
|
|
|
* @brief This function handles Bus Fault exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void BusFault_Handler(void)
|
|
|
{
|
|
|
- 8010fd2: e7fe b.n 8010fd2 <BusFault_Handler>
|
|
|
+ 8010f4a: e7fe b.n 8010f4a <BusFault_Handler>
|
|
|
|
|
|
-08010fd4 <UsageFault_Handler>:
|
|
|
+08010f4c <UsageFault_Handler>:
|
|
|
* @brief This function handles Usage Fault exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void UsageFault_Handler(void)
|
|
|
{
|
|
|
- 8010fd4: e7fe b.n 8010fd4 <UsageFault_Handler>
|
|
|
+ 8010f4c: e7fe b.n 8010f4c <UsageFault_Handler>
|
|
|
|
|
|
-08010fd6 <DebugMon_Handler>:
|
|
|
+08010f4e <DebugMon_Handler>:
|
|
|
* @brief This function handles Debug Monitor exception.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void DebugMon_Handler(void)
|
|
|
{
|
|
|
- 8010fd6: 4770 bx lr
|
|
|
+ 8010f4e: 4770 bx lr
|
|
|
|
|
|
-08010fd8 <ulli2a>:
|
|
|
+08010f50 <ulli2a>:
|
|
|
|
|
|
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
static void _TFP_GCC_NO_INLINE_ ulli2a(
|
|
|
unsigned long long int num, struct param *p)
|
|
|
{
|
|
|
- 8010fd8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
+ 8010f50: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8010fdc: 68d3 ldr r3, [r2, #12]
|
|
|
+ 8010f54: 68d3 ldr r3, [r2, #12]
|
|
|
static void _TFP_GCC_NO_INLINE_ ulli2a(
|
|
|
unsigned long long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
- 8010fde: f8d2 b010 ldr.w fp, [r2, #16]
|
|
|
+ 8010f56: f8d2 b010 ldr.w fp, [r2, #16]
|
|
|
|
|
|
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
static void _TFP_GCC_NO_INLINE_ ulli2a(
|
|
|
unsigned long long int num, struct param *p)
|
|
|
{
|
|
|
- 8010fe2: 4681 mov r9, r0
|
|
|
- 8010fe4: 468a mov sl, r1
|
|
|
- 8010fe6: 4690 mov r8, r2
|
|
|
+ 8010f5a: 4681 mov r9, r0
|
|
|
+ 8010f5c: 468a mov sl, r1
|
|
|
+ 8010f5e: 4690 mov r8, r2
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8010fe8: 461e mov r6, r3
|
|
|
- 8010fea: 2700 movs r7, #0
|
|
|
+ 8010f60: 461e mov r6, r3
|
|
|
+ 8010f62: 2700 movs r7, #0
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
static void _TFP_GCC_NO_INLINE_ ulli2a(
|
|
|
unsigned long long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
- 8010fec: 2401 movs r4, #1
|
|
|
- 8010fee: 2500 movs r5, #0
|
|
|
+ 8010f64: 2401 movs r4, #1
|
|
|
+ 8010f66: 2500 movs r5, #0
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8010ff0: e006 b.n 8011000 <ulli2a+0x28>
|
|
|
+ 8010f68: e006 b.n 8010f78 <ulli2a+0x28>
|
|
|
d *= p->base;
|
|
|
- 8010ff2: fb04 f307 mul.w r3, r4, r7
|
|
|
- 8010ff6: fb06 3305 mla r3, r6, r5, r3
|
|
|
- 8010ffa: fba4 4506 umull r4, r5, r4, r6
|
|
|
- 8010ffe: 195d adds r5, r3, r5
|
|
|
+ 8010f6a: fb04 f307 mul.w r3, r4, r7
|
|
|
+ 8010f6e: fb06 3305 mla r3, r6, r5, r3
|
|
|
+ 8010f72: fba4 4506 umull r4, r5, r4, r6
|
|
|
+ 8010f76: 195d adds r5, r3, r5
|
|
|
unsigned long long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8011000: 4648 mov r0, r9
|
|
|
- 8011002: 4651 mov r1, sl
|
|
|
- 8011004: 4622 mov r2, r4
|
|
|
- 8011006: 462b mov r3, r5
|
|
|
- 8011008: f7f7 fcd8 bl 80089bc <__aeabi_uldivmod>
|
|
|
- 801100c: 42b9 cmp r1, r7
|
|
|
- 801100e: bf08 it eq
|
|
|
- 8011010: 42b0 cmpeq r0, r6
|
|
|
- 8011012: d2ee bcs.n 8010ff2 <ulli2a+0x1a>
|
|
|
- 8011014: 2600 movs r6, #0
|
|
|
- 8011016: e02d b.n 8011074 <ulli2a+0x9c>
|
|
|
+ 8010f78: 4648 mov r0, r9
|
|
|
+ 8010f7a: 4651 mov r1, sl
|
|
|
+ 8010f7c: 4622 mov r2, r4
|
|
|
+ 8010f7e: 462b mov r3, r5
|
|
|
+ 8010f80: f7f7 fd1c bl 80089bc <__aeabi_uldivmod>
|
|
|
+ 8010f84: 42b9 cmp r1, r7
|
|
|
+ 8010f86: bf08 it eq
|
|
|
+ 8010f88: 42b0 cmpeq r0, r6
|
|
|
+ 8010f8a: d2ee bcs.n 8010f6a <ulli2a+0x1a>
|
|
|
+ 8010f8c: 2600 movs r6, #0
|
|
|
+ 8010f8e: e02d b.n 8010fec <ulli2a+0x9c>
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
- 8011018: 4622 mov r2, r4
|
|
|
- 801101a: 462b mov r3, r5
|
|
|
- 801101c: 4648 mov r0, r9
|
|
|
- 801101e: 4651 mov r1, sl
|
|
|
- 8011020: f7f7 fccc bl 80089bc <__aeabi_uldivmod>
|
|
|
+ 8010f90: 4622 mov r2, r4
|
|
|
+ 8010f92: 462b mov r3, r5
|
|
|
+ 8010f94: 4648 mov r0, r9
|
|
|
+ 8010f96: 4651 mov r1, sl
|
|
|
+ 8010f98: f7f7 fd10 bl 80089bc <__aeabi_uldivmod>
|
|
|
num %= d;
|
|
|
- 8011024: 4651 mov r1, sl
|
|
|
- 8011026: 4622 mov r2, r4
|
|
|
- 8011028: 462b mov r3, r5
|
|
|
+ 8010f9c: 4651 mov r1, sl
|
|
|
+ 8010f9e: 4622 mov r2, r4
|
|
|
+ 8010fa0: 462b mov r3, r5
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
- 801102a: 4607 mov r7, r0
|
|
|
+ 8010fa2: 4607 mov r7, r0
|
|
|
num %= d;
|
|
|
- 801102c: 4648 mov r0, r9
|
|
|
- 801102e: f7f7 fcc5 bl 80089bc <__aeabi_uldivmod>
|
|
|
+ 8010fa4: 4648 mov r0, r9
|
|
|
+ 8010fa6: f7f7 fd09 bl 80089bc <__aeabi_uldivmod>
|
|
|
d /= p->base;
|
|
|
- 8011032: 4620 mov r0, r4
|
|
|
- 8011034: 4629 mov r1, r5
|
|
|
+ 8010faa: 4620 mov r0, r4
|
|
|
+ 8010fac: 4629 mov r1, r5
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
num %= d;
|
|
|
- 8011036: 4691 mov r9, r2
|
|
|
- 8011038: 469a mov sl, r3
|
|
|
+ 8010fae: 4691 mov r9, r2
|
|
|
+ 8010fb0: 469a mov sl, r3
|
|
|
d /= p->base;
|
|
|
- 801103a: f8d8 200c ldr.w r2, [r8, #12]
|
|
|
- 801103e: 2300 movs r3, #0
|
|
|
- 8011040: f7f7 fcbc bl 80089bc <__aeabi_uldivmod>
|
|
|
- 8011044: 4604 mov r4, r0
|
|
|
- 8011046: 460d mov r5, r1
|
|
|
+ 8010fb2: f8d8 200c ldr.w r2, [r8, #12]
|
|
|
+ 8010fb6: 2300 movs r3, #0
|
|
|
+ 8010fb8: f7f7 fd00 bl 80089bc <__aeabi_uldivmod>
|
|
|
+ 8010fbc: 4604 mov r4, r0
|
|
|
+ 8010fbe: 460d mov r5, r1
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
- 8011048: b926 cbnz r6, 8011054 <ulli2a+0x7c>
|
|
|
- 801104a: 2f00 cmp r7, #0
|
|
|
- 801104c: dc02 bgt.n 8011054 <ulli2a+0x7c>
|
|
|
- 801104e: ea54 0305 orrs.w r3, r4, r5
|
|
|
- 8011052: d1e1 bne.n 8011018 <ulli2a+0x40>
|
|
|
+ 8010fc0: b926 cbnz r6, 8010fcc <ulli2a+0x7c>
|
|
|
+ 8010fc2: 2f00 cmp r7, #0
|
|
|
+ 8010fc4: dc02 bgt.n 8010fcc <ulli2a+0x7c>
|
|
|
+ 8010fc6: ea54 0305 orrs.w r3, r4, r5
|
|
|
+ 8010fca: d1e1 bne.n 8010f90 <ulli2a+0x40>
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
- 8011054: 2f09 cmp r7, #9
|
|
|
- 8011056: b2fa uxtb r2, r7
|
|
|
- 8011058: dd07 ble.n 801106a <ulli2a+0x92>
|
|
|
- 801105a: f898 3000 ldrb.w r3, [r8]
|
|
|
- 801105e: f013 0f04 tst.w r3, #4
|
|
|
- 8011062: bf0c ite eq
|
|
|
- 8011064: 2357 moveq r3, #87 ; 0x57
|
|
|
- 8011066: 2337 movne r3, #55 ; 0x37
|
|
|
- 8011068: e000 b.n 801106c <ulli2a+0x94>
|
|
|
- 801106a: 2330 movs r3, #48 ; 0x30
|
|
|
- 801106c: 189b adds r3, r3, r2
|
|
|
- 801106e: f80b 3b01 strb.w r3, [fp], #1
|
|
|
+ 8010fcc: 2f09 cmp r7, #9
|
|
|
+ 8010fce: b2fa uxtb r2, r7
|
|
|
+ 8010fd0: dd07 ble.n 8010fe2 <ulli2a+0x92>
|
|
|
+ 8010fd2: f898 3000 ldrb.w r3, [r8]
|
|
|
+ 8010fd6: f013 0f04 tst.w r3, #4
|
|
|
+ 8010fda: bf0c ite eq
|
|
|
+ 8010fdc: 2357 moveq r3, #87 ; 0x57
|
|
|
+ 8010fde: 2337 movne r3, #55 ; 0x37
|
|
|
+ 8010fe0: e000 b.n 8010fe4 <ulli2a+0x94>
|
|
|
+ 8010fe2: 2330 movs r3, #48 ; 0x30
|
|
|
+ 8010fe4: 189b adds r3, r3, r2
|
|
|
+ 8010fe6: f80b 3b01 strb.w r3, [fp], #1
|
|
|
++n;
|
|
|
- 8011072: 3601 adds r6, #1
|
|
|
+ 8010fea: 3601 adds r6, #1
|
|
|
int n = 0;
|
|
|
unsigned long long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
- 8011074: ea54 0305 orrs.w r3, r4, r5
|
|
|
- 8011078: d1ce bne.n 8011018 <ulli2a+0x40>
|
|
|
+ 8010fec: ea54 0305 orrs.w r3, r4, r5
|
|
|
+ 8010ff0: d1ce bne.n 8010f90 <ulli2a+0x40>
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
++n;
|
|
|
}
|
|
|
}
|
|
|
*bf = 0;
|
|
|
- 801107a: 2300 movs r3, #0
|
|
|
- 801107c: f88b 3000 strb.w r3, [fp]
|
|
|
- 8011080: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
+ 8010ff2: 2300 movs r3, #0
|
|
|
+ 8010ff4: f88b 3000 strb.w r3, [fp]
|
|
|
+ 8010ff8: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
|
|
|
-08011084 <uli2a>:
|
|
|
+08010ffc <uli2a>:
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
static void uli2a(unsigned long int num, struct param *p)
|
|
|
{
|
|
|
- 8011084: b570 push {r4, r5, r6, lr}
|
|
|
+ 8010ffc: b570 push {r4, r5, r6, lr}
|
|
|
int n = 0;
|
|
|
unsigned long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8011086: 68ca ldr r2, [r1, #12]
|
|
|
+ 8010ffe: 68ca ldr r2, [r1, #12]
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
static void uli2a(unsigned long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
- 8011088: 690c ldr r4, [r1, #16]
|
|
|
+ 8011000: 690c ldr r4, [r1, #16]
|
|
|
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
static void uli2a(unsigned long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long int d = 1;
|
|
|
- 801108a: 2301 movs r3, #1
|
|
|
+ 8011002: 2301 movs r3, #1
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 801108c: e000 b.n 8011090 <uli2a+0xc>
|
|
|
+ 8011004: e000 b.n 8011008 <uli2a+0xc>
|
|
|
d *= p->base;
|
|
|
- 801108e: 4353 muls r3, r2
|
|
|
+ 8011006: 4353 muls r3, r2
|
|
|
static void uli2a(unsigned long int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 8011090: fbb0 f5f3 udiv r5, r0, r3
|
|
|
- 8011094: 4295 cmp r5, r2
|
|
|
- 8011096: d2fa bcs.n 801108e <uli2a+0xa>
|
|
|
- 8011098: 2500 movs r5, #0
|
|
|
- 801109a: e01a b.n 80110d2 <uli2a+0x4e>
|
|
|
+ 8011008: fbb0 f5f3 udiv r5, r0, r3
|
|
|
+ 801100c: 4295 cmp r5, r2
|
|
|
+ 801100e: d2fa bcs.n 8011006 <uli2a+0xa>
|
|
|
+ 8011010: 2500 movs r5, #0
|
|
|
+ 8011012: e01a b.n 801104a <uli2a+0x4e>
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
num %= d;
|
|
|
d /= p->base;
|
|
|
- 801109c: 68ce ldr r6, [r1, #12]
|
|
|
+ 8011014: 68ce ldr r6, [r1, #12]
|
|
|
unsigned long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
- 801109e: fbb0 f2f3 udiv r2, r0, r3
|
|
|
+ 8011016: fbb0 f2f3 udiv r2, r0, r3
|
|
|
num %= d;
|
|
|
- 80110a2: fb03 0012 mls r0, r3, r2, r0
|
|
|
+ 801101a: fb03 0012 mls r0, r3, r2, r0
|
|
|
d /= p->base;
|
|
|
- 80110a6: fbb3 f3f6 udiv r3, r3, r6
|
|
|
+ 801101e: fbb3 f3f6 udiv r3, r3, r6
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
- 80110aa: b91d cbnz r5, 80110b4 <uli2a+0x30>
|
|
|
- 80110ac: 2a00 cmp r2, #0
|
|
|
- 80110ae: dc01 bgt.n 80110b4 <uli2a+0x30>
|
|
|
- 80110b0: 2b00 cmp r3, #0
|
|
|
- 80110b2: d1f3 bne.n 801109c <uli2a+0x18>
|
|
|
+ 8011022: b91d cbnz r5, 801102c <uli2a+0x30>
|
|
|
+ 8011024: 2a00 cmp r2, #0
|
|
|
+ 8011026: dc01 bgt.n 801102c <uli2a+0x30>
|
|
|
+ 8011028: 2b00 cmp r3, #0
|
|
|
+ 801102a: d1f3 bne.n 8011014 <uli2a+0x18>
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
- 80110b4: 2a09 cmp r2, #9
|
|
|
- 80110b6: b2d6 uxtb r6, r2
|
|
|
- 80110b8: dd06 ble.n 80110c8 <uli2a+0x44>
|
|
|
- 80110ba: 780a ldrb r2, [r1, #0]
|
|
|
- 80110bc: f012 0f04 tst.w r2, #4
|
|
|
- 80110c0: bf0c ite eq
|
|
|
- 80110c2: 2257 moveq r2, #87 ; 0x57
|
|
|
- 80110c4: 2237 movne r2, #55 ; 0x37
|
|
|
- 80110c6: e000 b.n 80110ca <uli2a+0x46>
|
|
|
- 80110c8: 2230 movs r2, #48 ; 0x30
|
|
|
- 80110ca: 1992 adds r2, r2, r6
|
|
|
- 80110cc: f804 2b01 strb.w r2, [r4], #1
|
|
|
+ 801102c: 2a09 cmp r2, #9
|
|
|
+ 801102e: b2d6 uxtb r6, r2
|
|
|
+ 8011030: dd06 ble.n 8011040 <uli2a+0x44>
|
|
|
+ 8011032: 780a ldrb r2, [r1, #0]
|
|
|
+ 8011034: f012 0f04 tst.w r2, #4
|
|
|
+ 8011038: bf0c ite eq
|
|
|
+ 801103a: 2257 moveq r2, #87 ; 0x57
|
|
|
+ 801103c: 2237 movne r2, #55 ; 0x37
|
|
|
+ 801103e: e000 b.n 8011042 <uli2a+0x46>
|
|
|
+ 8011040: 2230 movs r2, #48 ; 0x30
|
|
|
+ 8011042: 1992 adds r2, r2, r6
|
|
|
+ 8011044: f804 2b01 strb.w r2, [r4], #1
|
|
|
++n;
|
|
|
- 80110d0: 3501 adds r5, #1
|
|
|
+ 8011048: 3501 adds r5, #1
|
|
|
int n = 0;
|
|
|
unsigned long int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
- 80110d2: 2b00 cmp r3, #0
|
|
|
- 80110d4: d1e2 bne.n 801109c <uli2a+0x18>
|
|
|
+ 801104a: 2b00 cmp r3, #0
|
|
|
+ 801104c: d1e2 bne.n 8011014 <uli2a+0x18>
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
++n;
|
|
|
}
|
|
|
}
|
|
|
*bf = 0;
|
|
|
- 80110d6: 7023 strb r3, [r4, #0]
|
|
|
- 80110d8: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 801104e: 7023 strb r3, [r4, #0]
|
|
|
+ 8011050: bd70 pop {r4, r5, r6, pc}
|
|
|
|
|
|
-080110da <ui2a>:
|
|
|
+08011052 <ui2a>:
|
|
|
uli2a(num, p);
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
static void ui2a(unsigned int num, struct param *p)
|
|
|
{
|
|
|
- 80110da: b570 push {r4, r5, r6, lr}
|
|
|
+ 8011052: b570 push {r4, r5, r6, lr}
|
|
|
int n = 0;
|
|
|
unsigned int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 80110dc: 68ca ldr r2, [r1, #12]
|
|
|
+ 8011054: 68ca ldr r2, [r1, #12]
|
|
|
|
|
|
static void ui2a(unsigned int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
- 80110de: 690c ldr r4, [r1, #16]
|
|
|
+ 8011056: 690c ldr r4, [r1, #16]
|
|
|
#endif
|
|
|
|
|
|
static void ui2a(unsigned int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned int d = 1;
|
|
|
- 80110e0: 2301 movs r3, #1
|
|
|
+ 8011058: 2301 movs r3, #1
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 80110e2: e000 b.n 80110e6 <ui2a+0xc>
|
|
|
+ 801105a: e000 b.n 801105e <ui2a+0xc>
|
|
|
d *= p->base;
|
|
|
- 80110e4: 4353 muls r3, r2
|
|
|
+ 801105c: 4353 muls r3, r2
|
|
|
static void ui2a(unsigned int num, struct param *p)
|
|
|
{
|
|
|
int n = 0;
|
|
|
unsigned int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
- 80110e6: fbb0 f5f3 udiv r5, r0, r3
|
|
|
- 80110ea: 4295 cmp r5, r2
|
|
|
- 80110ec: d2fa bcs.n 80110e4 <ui2a+0xa>
|
|
|
- 80110ee: 2500 movs r5, #0
|
|
|
- 80110f0: e01a b.n 8011128 <ui2a+0x4e>
|
|
|
+ 801105e: fbb0 f5f3 udiv r5, r0, r3
|
|
|
+ 8011062: 4295 cmp r5, r2
|
|
|
+ 8011064: d2fa bcs.n 801105c <ui2a+0xa>
|
|
|
+ 8011066: 2500 movs r5, #0
|
|
|
+ 8011068: e01a b.n 80110a0 <ui2a+0x4e>
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
num %= d;
|
|
|
d /= p->base;
|
|
|
- 80110f2: 68ce ldr r6, [r1, #12]
|
|
|
+ 801106a: 68ce ldr r6, [r1, #12]
|
|
|
unsigned int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
int dgt = num / d;
|
|
|
- 80110f4: fbb0 f2f3 udiv r2, r0, r3
|
|
|
+ 801106c: fbb0 f2f3 udiv r2, r0, r3
|
|
|
num %= d;
|
|
|
- 80110f8: fb03 0012 mls r0, r3, r2, r0
|
|
|
+ 8011070: fb03 0012 mls r0, r3, r2, r0
|
|
|
d /= p->base;
|
|
|
- 80110fc: fbb3 f3f6 udiv r3, r3, r6
|
|
|
+ 8011074: fbb3 f3f6 udiv r3, r3, r6
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
- 8011100: b91d cbnz r5, 801110a <ui2a+0x30>
|
|
|
- 8011102: 2a00 cmp r2, #0
|
|
|
- 8011104: dc01 bgt.n 801110a <ui2a+0x30>
|
|
|
- 8011106: 2b00 cmp r3, #0
|
|
|
- 8011108: d1f3 bne.n 80110f2 <ui2a+0x18>
|
|
|
+ 8011078: b91d cbnz r5, 8011082 <ui2a+0x30>
|
|
|
+ 801107a: 2a00 cmp r2, #0
|
|
|
+ 801107c: dc01 bgt.n 8011082 <ui2a+0x30>
|
|
|
+ 801107e: 2b00 cmp r3, #0
|
|
|
+ 8011080: d1f3 bne.n 801106a <ui2a+0x18>
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
- 801110a: 2a09 cmp r2, #9
|
|
|
- 801110c: b2d6 uxtb r6, r2
|
|
|
- 801110e: dd06 ble.n 801111e <ui2a+0x44>
|
|
|
- 8011110: 780a ldrb r2, [r1, #0]
|
|
|
- 8011112: f012 0f04 tst.w r2, #4
|
|
|
- 8011116: bf0c ite eq
|
|
|
- 8011118: 2257 moveq r2, #87 ; 0x57
|
|
|
- 801111a: 2237 movne r2, #55 ; 0x37
|
|
|
- 801111c: e000 b.n 8011120 <ui2a+0x46>
|
|
|
- 801111e: 2230 movs r2, #48 ; 0x30
|
|
|
- 8011120: 1992 adds r2, r2, r6
|
|
|
- 8011122: f804 2b01 strb.w r2, [r4], #1
|
|
|
+ 8011082: 2a09 cmp r2, #9
|
|
|
+ 8011084: b2d6 uxtb r6, r2
|
|
|
+ 8011086: dd06 ble.n 8011096 <ui2a+0x44>
|
|
|
+ 8011088: 780a ldrb r2, [r1, #0]
|
|
|
+ 801108a: f012 0f04 tst.w r2, #4
|
|
|
+ 801108e: bf0c ite eq
|
|
|
+ 8011090: 2257 moveq r2, #87 ; 0x57
|
|
|
+ 8011092: 2237 movne r2, #55 ; 0x37
|
|
|
+ 8011094: e000 b.n 8011098 <ui2a+0x46>
|
|
|
+ 8011096: 2230 movs r2, #48 ; 0x30
|
|
|
+ 8011098: 1992 adds r2, r2, r6
|
|
|
+ 801109a: f804 2b01 strb.w r2, [r4], #1
|
|
|
++n;
|
|
|
- 8011126: 3501 adds r5, #1
|
|
|
+ 801109e: 3501 adds r5, #1
|
|
|
int n = 0;
|
|
|
unsigned int d = 1;
|
|
|
char *bf = p->bf;
|
|
|
while (num / d >= p->base)
|
|
|
d *= p->base;
|
|
|
while (d != 0) {
|
|
|
- 8011128: 2b00 cmp r3, #0
|
|
|
- 801112a: d1e2 bne.n 80110f2 <ui2a+0x18>
|
|
|
+ 80110a0: 2b00 cmp r3, #0
|
|
|
+ 80110a2: d1e2 bne.n 801106a <ui2a+0x18>
|
|
|
if (n || dgt > 0 || d == 0) {
|
|
|
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
|
|
++n;
|
|
|
}
|
|
|
}
|
|
|
*bf = 0;
|
|
|
- 801112c: 7023 strb r3, [r4, #0]
|
|
|
- 801112e: bd70 pop {r4, r5, r6, pc}
|
|
|
+ 80110a4: 7023 strb r3, [r4, #0]
|
|
|
+ 80110a6: bd70 pop {r4, r5, r6, pc}
|
|
|
|
|
|
-08011130 <putchw>:
|
|
|
+080110a8 <putchw>:
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
static void putchw(void *putp, putcf putf, struct param *p)
|
|
|
{
|
|
|
- 8011130: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
+ 80110a8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
char ch;
|
|
|
int n = p->width;
|
|
|
char *bf = p->bf;
|
|
|
- 8011134: 6913 ldr r3, [r2, #16]
|
|
|
+ 80110ac: 6913 ldr r3, [r2, #16]
|
|
|
}
|
|
|
|
|
|
static void putchw(void *putp, putcf putf, struct param *p)
|
|
|
{
|
|
|
char ch;
|
|
|
int n = p->width;
|
|
|
- 8011136: 6854 ldr r4, [r2, #4]
|
|
|
+ 80110ae: 6854 ldr r4, [r2, #4]
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
static void putchw(void *putp, putcf putf, struct param *p)
|
|
|
{
|
|
|
- 8011138: 4606 mov r6, r0
|
|
|
- 801113a: 460f mov r7, r1
|
|
|
- 801113c: 4615 mov r5, r2
|
|
|
+ 80110b0: 4606 mov r6, r0
|
|
|
+ 80110b2: 460f mov r7, r1
|
|
|
+ 80110b4: 4615 mov r5, r2
|
|
|
char ch;
|
|
|
int n = p->width;
|
|
|
char *bf = p->bf;
|
|
|
|
|
|
/* Number of filling characters */
|
|
|
while (*bf++ && n > 0)
|
|
|
- 801113e: e000 b.n 8011142 <putchw+0x12>
|
|
|
+ 80110b6: e000 b.n 80110ba <putchw+0x12>
|
|
|
n--;
|
|
|
- 8011140: 3c01 subs r4, #1
|
|
|
+ 80110b8: 3c01 subs r4, #1
|
|
|
char ch;
|
|
|
int n = p->width;
|
|
|
char *bf = p->bf;
|
|
|
|
|
|
/* Number of filling characters */
|
|
|
while (*bf++ && n > 0)
|
|
|
- 8011142: f813 2b01 ldrb.w r2, [r3], #1
|
|
|
- 8011146: b912 cbnz r2, 801114e <putchw+0x1e>
|
|
|
+ 80110ba: f813 2b01 ldrb.w r2, [r3], #1
|
|
|
+ 80110be: b912 cbnz r2, 80110c6 <putchw+0x1e>
|
|
|
n--;
|
|
|
if (p->sign)
|
|
|
- 8011148: 7a2b ldrb r3, [r5, #8]
|
|
|
- 801114a: b91b cbnz r3, 8011154 <putchw+0x24>
|
|
|
- 801114c: e003 b.n 8011156 <putchw+0x26>
|
|
|
+ 80110c0: 7a2b ldrb r3, [r5, #8]
|
|
|
+ 80110c2: b91b cbnz r3, 80110cc <putchw+0x24>
|
|
|
+ 80110c4: e003 b.n 80110ce <putchw+0x26>
|
|
|
char ch;
|
|
|
int n = p->width;
|
|
|
char *bf = p->bf;
|
|
|
|
|
|
/* Number of filling characters */
|
|
|
while (*bf++ && n > 0)
|
|
|
- 801114e: 2c00 cmp r4, #0
|
|
|
- 8011150: dcf6 bgt.n 8011140 <putchw+0x10>
|
|
|
- 8011152: e7f9 b.n 8011148 <putchw+0x18>
|
|
|
+ 80110c6: 2c00 cmp r4, #0
|
|
|
+ 80110c8: dcf6 bgt.n 80110b8 <putchw+0x10>
|
|
|
+ 80110ca: e7f9 b.n 80110c0 <putchw+0x18>
|
|
|
n--;
|
|
|
if (p->sign)
|
|
|
n--;
|
|
|
- 8011154: 3c01 subs r4, #1
|
|
|
+ 80110cc: 3c01 subs r4, #1
|
|
|
if (p->alt && p->base == 16)
|
|
|
- 8011156: 782b ldrb r3, [r5, #0]
|
|
|
- 8011158: 0799 lsls r1, r3, #30
|
|
|
- 801115a: d507 bpl.n 801116c <putchw+0x3c>
|
|
|
- 801115c: 68eb ldr r3, [r5, #12]
|
|
|
- 801115e: 2b10 cmp r3, #16
|
|
|
- 8011160: d101 bne.n 8011166 <putchw+0x36>
|
|
|
+ 80110ce: 782b ldrb r3, [r5, #0]
|
|
|
+ 80110d0: 0799 lsls r1, r3, #30
|
|
|
+ 80110d2: d507 bpl.n 80110e4 <putchw+0x3c>
|
|
|
+ 80110d4: 68eb ldr r3, [r5, #12]
|
|
|
+ 80110d6: 2b10 cmp r3, #16
|
|
|
+ 80110d8: d101 bne.n 80110de <putchw+0x36>
|
|
|
n -= 2;
|
|
|
- 8011162: 3c02 subs r4, #2
|
|
|
- 8011164: e002 b.n 801116c <putchw+0x3c>
|
|
|
+ 80110da: 3c02 subs r4, #2
|
|
|
+ 80110dc: e002 b.n 80110e4 <putchw+0x3c>
|
|
|
else if (p->alt && p->base == 8)
|
|
|
- 8011166: 2b08 cmp r3, #8
|
|
|
+ 80110de: 2b08 cmp r3, #8
|
|
|
n--;
|
|
|
- 8011168: bf08 it eq
|
|
|
- 801116a: 3c01 subeq r4, #1
|
|
|
+ 80110e0: bf08 it eq
|
|
|
+ 80110e2: 3c01 subeq r4, #1
|
|
|
|
|
|
/* Fill with space to align to the right, before alternate or sign */
|
|
|
if (!p->lz && !p->align_left) {
|
|
|
- 801116c: 782b ldrb r3, [r5, #0]
|
|
|
- 801116e: f013 0f09 tst.w r3, #9
|
|
|
- 8011172: d10d bne.n 8011190 <putchw+0x60>
|
|
|
- 8011174: 46a0 mov r8, r4
|
|
|
- 8011176: e004 b.n 8011182 <putchw+0x52>
|
|
|
+ 80110e4: 782b ldrb r3, [r5, #0]
|
|
|
+ 80110e6: f013 0f09 tst.w r3, #9
|
|
|
+ 80110ea: d10d bne.n 8011108 <putchw+0x60>
|
|
|
+ 80110ec: 46a0 mov r8, r4
|
|
|
+ 80110ee: e004 b.n 80110fa <putchw+0x52>
|
|
|
while (n-- > 0)
|
|
|
putf(putp, ' ');
|
|
|
- 8011178: 4630 mov r0, r6
|
|
|
- 801117a: 2120 movs r1, #32
|
|
|
- 801117c: 47b8 blx r7
|
|
|
- 801117e: f108 38ff add.w r8, r8, #4294967295
|
|
|
+ 80110f0: 4630 mov r0, r6
|
|
|
+ 80110f2: 2120 movs r1, #32
|
|
|
+ 80110f4: 47b8 blx r7
|
|
|
+ 80110f6: f108 38ff add.w r8, r8, #4294967295
|
|
|
else if (p->alt && p->base == 8)
|
|
|
n--;
|
|
|
|
|
|
/* Fill with space to align to the right, before alternate or sign */
|
|
|
if (!p->lz && !p->align_left) {
|
|
|
while (n-- > 0)
|
|
|
- 8011182: f1b8 0f00 cmp.w r8, #0
|
|
|
- 8011186: dcf7 bgt.n 8011178 <putchw+0x48>
|
|
|
+ 80110fa: f1b8 0f00 cmp.w r8, #0
|
|
|
+ 80110fe: dcf7 bgt.n 80110f0 <putchw+0x48>
|
|
|
return neg ? -fvalue : fvalue;
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
static void putchw(void *putp, putcf putf, struct param *p)
|
|
|
- 8011188: 1e63 subs r3, r4, #1
|
|
|
- 801118a: ea24 74e4 bic.w r4, r4, r4, asr #31
|
|
|
- 801118e: 1b1c subs r4, r3, r4
|
|
|
+ 8011100: 1e63 subs r3, r4, #1
|
|
|
+ 8011102: ea24 74e4 bic.w r4, r4, r4, asr #31
|
|
|
+ 8011106: 1b1c subs r4, r3, r4
|
|
|
while (n-- > 0)
|
|
|
putf(putp, ' ');
|
|
|
}
|
|
|
|
|
|
/* print sign */
|
|
|
if (p->sign)
|
|
|
- 8011190: 7a29 ldrb r1, [r5, #8]
|
|
|
- 8011192: b109 cbz r1, 8011198 <putchw+0x68>
|
|
|
+ 8011108: 7a29 ldrb r1, [r5, #8]
|
|
|
+ 801110a: b109 cbz r1, 8011110 <putchw+0x68>
|
|
|
putf(putp, p->sign);
|
|
|
- 8011194: 4630 mov r0, r6
|
|
|
- 8011196: 47b8 blx r7
|
|
|
+ 801110c: 4630 mov r0, r6
|
|
|
+ 801110e: 47b8 blx r7
|
|
|
|
|
|
/* Alternate */
|
|
|
if (p->alt && p->base == 16) {
|
|
|
- 8011198: 782b ldrb r3, [r5, #0]
|
|
|
- 801119a: 079a lsls r2, r3, #30
|
|
|
- 801119c: d512 bpl.n 80111c4 <putchw+0x94>
|
|
|
- 801119e: 68eb ldr r3, [r5, #12]
|
|
|
- 80111a0: 2b10 cmp r3, #16
|
|
|
- 80111a2: d10a bne.n 80111ba <putchw+0x8a>
|
|
|
+ 8011110: 782b ldrb r3, [r5, #0]
|
|
|
+ 8011112: 079a lsls r2, r3, #30
|
|
|
+ 8011114: d512 bpl.n 801113c <putchw+0x94>
|
|
|
+ 8011116: 68eb ldr r3, [r5, #12]
|
|
|
+ 8011118: 2b10 cmp r3, #16
|
|
|
+ 801111a: d10a bne.n 8011132 <putchw+0x8a>
|
|
|
putf(putp, '0');
|
|
|
- 80111a4: 2130 movs r1, #48 ; 0x30
|
|
|
- 80111a6: 4630 mov r0, r6
|
|
|
- 80111a8: 47b8 blx r7
|
|
|
+ 801111c: 2130 movs r1, #48 ; 0x30
|
|
|
+ 801111e: 4630 mov r0, r6
|
|
|
+ 8011120: 47b8 blx r7
|
|
|
putf(putp, (p->uc ? 'X' : 'x'));
|
|
|
- 80111aa: 782b ldrb r3, [r5, #0]
|
|
|
- 80111ac: f013 0f04 tst.w r3, #4
|
|
|
- 80111b0: 4630 mov r0, r6
|
|
|
- 80111b2: bf0c ite eq
|
|
|
- 80111b4: 2178 moveq r1, #120 ; 0x78
|
|
|
- 80111b6: 2158 movne r1, #88 ; 0x58
|
|
|
- 80111b8: e003 b.n 80111c2 <putchw+0x92>
|
|
|
+ 8011122: 782b ldrb r3, [r5, #0]
|
|
|
+ 8011124: f013 0f04 tst.w r3, #4
|
|
|
+ 8011128: 4630 mov r0, r6
|
|
|
+ 801112a: bf0c ite eq
|
|
|
+ 801112c: 2178 moveq r1, #120 ; 0x78
|
|
|
+ 801112e: 2158 movne r1, #88 ; 0x58
|
|
|
+ 8011130: e003 b.n 801113a <putchw+0x92>
|
|
|
} else if (p->alt && p->base == 8) {
|
|
|
- 80111ba: 2b08 cmp r3, #8
|
|
|
- 80111bc: d102 bne.n 80111c4 <putchw+0x94>
|
|
|
+ 8011132: 2b08 cmp r3, #8
|
|
|
+ 8011134: d102 bne.n 801113c <putchw+0x94>
|
|
|
putf(putp, '0');
|
|
|
- 80111be: 4630 mov r0, r6
|
|
|
- 80111c0: 2130 movs r1, #48 ; 0x30
|
|
|
- 80111c2: 47b8 blx r7
|
|
|
+ 8011136: 4630 mov r0, r6
|
|
|
+ 8011138: 2130 movs r1, #48 ; 0x30
|
|
|
+ 801113a: 47b8 blx r7
|
|
|
}
|
|
|
|
|
|
/* Fill with zeros, after alternate or sign */
|
|
|
if (p->lz) {
|
|
|
- 80111c4: 782b ldrb r3, [r5, #0]
|
|
|
- 80111c6: 07db lsls r3, r3, #31
|
|
|
- 80111c8: d50d bpl.n 80111e6 <putchw+0xb6>
|
|
|
- 80111ca: 46a0 mov r8, r4
|
|
|
- 80111cc: e004 b.n 80111d8 <putchw+0xa8>
|
|
|
+ 801113c: 782b ldrb r3, [r5, #0]
|
|
|
+ 801113e: 07db lsls r3, r3, #31
|
|
|
+ 8011140: d50d bpl.n 801115e <putchw+0xb6>
|
|
|
+ 8011142: 46a0 mov r8, r4
|
|
|
+ 8011144: e004 b.n 8011150 <putchw+0xa8>
|
|
|
while (n-- > 0)
|
|
|
putf(putp, '0');
|
|
|
- 80111ce: 4630 mov r0, r6
|
|
|
- 80111d0: 2130 movs r1, #48 ; 0x30
|
|
|
- 80111d2: 47b8 blx r7
|
|
|
- 80111d4: f108 38ff add.w r8, r8, #4294967295
|
|
|
+ 8011146: 4630 mov r0, r6
|
|
|
+ 8011148: 2130 movs r1, #48 ; 0x30
|
|
|
+ 801114a: 47b8 blx r7
|
|
|
+ 801114c: f108 38ff add.w r8, r8, #4294967295
|
|
|
putf(putp, '0');
|
|
|
}
|
|
|
|
|
|
/* Fill with zeros, after alternate or sign */
|
|
|
if (p->lz) {
|
|
|
while (n-- > 0)
|
|
|
- 80111d8: f1b8 0f00 cmp.w r8, #0
|
|
|
- 80111dc: dcf7 bgt.n 80111ce <putchw+0x9e>
|
|
|
+ 8011150: f1b8 0f00 cmp.w r8, #0
|
|
|
+ 8011154: dcf7 bgt.n 8011146 <putchw+0x9e>
|
|
|
return neg ? -fvalue : fvalue;
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
static void putchw(void *putp, putcf putf, struct param *p)
|
|
|
- 80111de: 1e63 subs r3, r4, #1
|
|
|
- 80111e0: ea24 74e4 bic.w r4, r4, r4, asr #31
|
|
|
- 80111e4: 1b1c subs r4, r3, r4
|
|
|
+ 8011156: 1e63 subs r3, r4, #1
|
|
|
+ 8011158: ea24 74e4 bic.w r4, r4, r4, asr #31
|
|
|
+ 801115c: 1b1c subs r4, r3, r4
|
|
|
while (n-- > 0)
|
|
|
putf(putp, '0');
|
|
|
}
|
|
|
|
|
|
/* Put actual buffer */
|
|
|
bf = p->bf;
|
|
|
- 80111e6: f8d5 8010 ldr.w r8, [r5, #16]
|
|
|
+ 801115e: f8d5 8010 ldr.w r8, [r5, #16]
|
|
|
while ((ch = *bf++))
|
|
|
- 80111ea: e001 b.n 80111f0 <putchw+0xc0>
|
|
|
+ 8011162: e001 b.n 8011168 <putchw+0xc0>
|
|
|
putf(putp, ch);
|
|
|
- 80111ec: 4630 mov r0, r6
|
|
|
- 80111ee: 47b8 blx r7
|
|
|
+ 8011164: 4630 mov r0, r6
|
|
|
+ 8011166: 47b8 blx r7
|
|
|
putf(putp, '0');
|
|
|
}
|
|
|
|
|
|
/* Put actual buffer */
|
|
|
bf = p->bf;
|
|
|
while ((ch = *bf++))
|
|
|
- 80111f0: f818 1b01 ldrb.w r1, [r8], #1
|
|
|
- 80111f4: 2900 cmp r1, #0
|
|
|
- 80111f6: d1f9 bne.n 80111ec <putchw+0xbc>
|
|
|
+ 8011168: f818 1b01 ldrb.w r1, [r8], #1
|
|
|
+ 801116c: 2900 cmp r1, #0
|
|
|
+ 801116e: d1f9 bne.n 8011164 <putchw+0xbc>
|
|
|
putf(putp, ch);
|
|
|
|
|
|
/* Fill with space to align to the left, after string */
|
|
|
if (!p->lz && p->align_left) {
|
|
|
- 80111f8: 782b ldrb r3, [r5, #0]
|
|
|
- 80111fa: f003 0309 and.w r3, r3, #9
|
|
|
- 80111fe: 2b08 cmp r3, #8
|
|
|
- 8011200: d106 bne.n 8011210 <putchw+0xe0>
|
|
|
- 8011202: e003 b.n 801120c <putchw+0xdc>
|
|
|
+ 8011170: 782b ldrb r3, [r5, #0]
|
|
|
+ 8011172: f003 0309 and.w r3, r3, #9
|
|
|
+ 8011176: 2b08 cmp r3, #8
|
|
|
+ 8011178: d106 bne.n 8011188 <putchw+0xe0>
|
|
|
+ 801117a: e003 b.n 8011184 <putchw+0xdc>
|
|
|
while (n-- > 0)
|
|
|
putf(putp, ' ');
|
|
|
- 8011204: 4630 mov r0, r6
|
|
|
- 8011206: 2120 movs r1, #32
|
|
|
- 8011208: 47b8 blx r7
|
|
|
- 801120a: 3c01 subs r4, #1
|
|
|
+ 801117c: 4630 mov r0, r6
|
|
|
+ 801117e: 2120 movs r1, #32
|
|
|
+ 8011180: 47b8 blx r7
|
|
|
+ 8011182: 3c01 subs r4, #1
|
|
|
while ((ch = *bf++))
|
|
|
putf(putp, ch);
|
|
|
|
|
|
/* Fill with space to align to the left, after string */
|
|
|
if (!p->lz && p->align_left) {
|
|
|
while (n-- > 0)
|
|
|
- 801120c: 2c00 cmp r4, #0
|
|
|
- 801120e: dcf9 bgt.n 8011204 <putchw+0xd4>
|
|
|
- 8011210: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
+ 8011184: 2c00 cmp r4, #0
|
|
|
+ 8011186: dcf9 bgt.n 801117c <putchw+0xd4>
|
|
|
+ 8011188: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
|
|
|
-08011214 <_vsprintf_putcf>:
|
|
|
+0801118c <_vsprintf_putcf>:
|
|
|
};
|
|
|
|
|
|
static void _vsprintf_putcf(void *p, char c)
|
|
|
{
|
|
|
struct _vsprintf_putcf_data *data = (struct _vsprintf_putcf_data*)p;
|
|
|
data->dest[data->num_chars++] = c;
|
|
|
- 8011214: e890 000c ldmia.w r0, {r2, r3}
|
|
|
- 8011218: 54d1 strb r1, [r2, r3]
|
|
|
- 801121a: 3301 adds r3, #1
|
|
|
- 801121c: 6043 str r3, [r0, #4]
|
|
|
- 801121e: 4770 bx lr
|
|
|
+ 801118c: e890 000c ldmia.w r0, {r2, r3}
|
|
|
+ 8011190: 54d1 strb r1, [r2, r3]
|
|
|
+ 8011192: 3301 adds r3, #1
|
|
|
+ 8011194: 6043 str r3, [r0, #4]
|
|
|
+ 8011196: 4770 bx lr
|
|
|
|
|
|
-08011220 <tfp_format>:
|
|
|
+08011198 <tfp_format>:
|
|
|
putf(putp, ' ');
|
|
|
}
|
|
|
}
|
|
|
|
|
|
void tfp_format(void *putp, putcf putf, const char *fmt, va_list va)
|
|
|
{
|
|
|
- 8011220: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
- 8011224: b09b sub sp, #108 ; 0x6c
|
|
|
- 8011226: 4617 mov r7, r2
|
|
|
+ 8011198: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
+ 801119c: b09b sub sp, #108 ; 0x6c
|
|
|
+ 801119e: 4617 mov r7, r2
|
|
|
char bf[23]; /* long = 64b on some architectures */
|
|
|
#else
|
|
|
char bf[12]; /* int = 32b on some architectures */
|
|
|
#endif
|
|
|
char ch;
|
|
|
p.bf = bf;
|
|
|
- 8011228: aa04 add r2, sp, #16
|
|
|
+ 80111a0: aa04 add r2, sp, #16
|
|
|
putf(putp, ' ');
|
|
|
}
|
|
|
}
|
|
|
|
|
|
void tfp_format(void *putp, putcf putf, const char *fmt, va_list va)
|
|
|
{
|
|
|
- 801122a: 4605 mov r5, r0
|
|
|
- 801122c: 460e mov r6, r1
|
|
|
- 801122e: 461c mov r4, r3
|
|
|
+ 80111a2: 4605 mov r5, r0
|
|
|
+ 80111a4: 460e mov r6, r1
|
|
|
+ 80111a6: 461c mov r4, r3
|
|
|
char bf[23]; /* long = 64b on some architectures */
|
|
|
#else
|
|
|
char bf[12]; /* int = 32b on some architectures */
|
|
|
#endif
|
|
|
char ch;
|
|
|
p.bf = bf;
|
|
|
- 8011230: 920e str r2, [sp, #56] ; 0x38
|
|
|
+ 80111a8: 920e str r2, [sp, #56] ; 0x38
|
|
|
|
|
|
while ((ch = *(fmt++))) {
|
|
|
- 8011232: e208 b.n 8011646 <tfp_format+0x426>
|
|
|
+ 80111aa: e208 b.n 80115be <tfp_format+0x426>
|
|
|
if (ch != '%') {
|
|
|
- 8011234: 2925 cmp r1, #37 ; 0x25
|
|
|
- 8011236: d000 beq.n 801123a <tfp_format+0x1a>
|
|
|
- 8011238: e13a b.n 80114b0 <tfp_format+0x290>
|
|
|
+ 80111ac: 2925 cmp r1, #37 ; 0x25
|
|
|
+ 80111ae: d000 beq.n 80111b2 <tfp_format+0x1a>
|
|
|
+ 80111b0: e13a b.n 8011428 <tfp_format+0x290>
|
|
|
#endif
|
|
|
/* Init parameter struct */
|
|
|
p.lz = 0;
|
|
|
p.alt = 0;
|
|
|
p.width = 0;
|
|
|
p.align_left = 0;
|
|
|
- 801123a: f89d 2028 ldrb.w r2, [sp, #40] ; 0x28
|
|
|
+ 80111b2: f89d 2028 ldrb.w r2, [sp, #40] ; 0x28
|
|
|
char lng = 0; /* 1 for long, 2 for long long */
|
|
|
#endif
|
|
|
/* Init parameter struct */
|
|
|
p.lz = 0;
|
|
|
p.alt = 0;
|
|
|
p.width = 0;
|
|
|
- 801123e: 2300 movs r3, #0
|
|
|
+ 80111b6: 2300 movs r3, #0
|
|
|
p.align_left = 0;
|
|
|
- 8011240: f002 02fc and.w r2, r2, #252 ; 0xfc
|
|
|
- 8011244: f363 02c3 bfi r2, r3, #3, #1
|
|
|
- 8011248: f88d 2028 strb.w r2, [sp, #40] ; 0x28
|
|
|
+ 80111b8: f002 02fc and.w r2, r2, #252 ; 0xfc
|
|
|
+ 80111bc: f363 02c3 bfi r2, r3, #3, #1
|
|
|
+ 80111c0: f88d 2028 strb.w r2, [sp, #40] ; 0x28
|
|
|
p.sign = 0;
|
|
|
p.prec = 2;
|
|
|
- 801124c: 2102 movs r1, #2
|
|
|
+ 80111c4: 2102 movs r1, #2
|
|
|
} else {
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
char lng = 0; /* 1 for long, 2 for long long */
|
|
|
#endif
|
|
|
/* Init parameter struct */
|
|
|
p.lz = 0;
|
|
|
- 801124e: b2d2 uxtb r2, r2
|
|
|
- 8011250: f002 0c01 and.w ip, r2, #1
|
|
|
- 8011254: f3c2 0040 ubfx r0, r2, #1, #1
|
|
|
+ 80111c6: b2d2 uxtb r2, r2
|
|
|
+ 80111c8: f002 0c01 and.w ip, r2, #1
|
|
|
+ 80111cc: f3c2 0040 ubfx r0, r2, #1, #1
|
|
|
p.alt = 0;
|
|
|
p.width = 0;
|
|
|
- 8011258: 930b str r3, [sp, #44] ; 0x2c
|
|
|
+ 80111d0: 930b str r3, [sp, #44] ; 0x2c
|
|
|
p.align_left = 0;
|
|
|
p.sign = 0;
|
|
|
- 801125a: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
+ 80111d2: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
p.prec = 2;
|
|
|
- 801125e: f88d 103c strb.w r1, [sp, #60] ; 0x3c
|
|
|
- 8011262: f3c2 02c0 ubfx r2, r2, #3, #1
|
|
|
+ 80111d6: f88d 103c strb.w r1, [sp, #60] ; 0x3c
|
|
|
+ 80111da: f3c2 02c0 ubfx r2, r2, #3, #1
|
|
|
|
|
|
/* Flags */
|
|
|
while ((ch = *(fmt++))) {
|
|
|
- 8011266: e012 b.n 801128e <tfp_format+0x6e>
|
|
|
+ 80111de: e012 b.n 8011206 <tfp_format+0x6e>
|
|
|
switch (ch) {
|
|
|
- 8011268: 292d cmp r1, #45 ; 0x2d
|
|
|
- 801126a: d00f beq.n 801128c <tfp_format+0x6c>
|
|
|
- 801126c: d804 bhi.n 8011278 <tfp_format+0x58>
|
|
|
- 801126e: 2923 cmp r1, #35 ; 0x23
|
|
|
- 8011270: d008 beq.n 8011284 <tfp_format+0x64>
|
|
|
- 8011272: 292b cmp r1, #43 ; 0x2b
|
|
|
- 8011274: d10f bne.n 8011296 <tfp_format+0x76>
|
|
|
- 8011276: e007 b.n 8011288 <tfp_format+0x68>
|
|
|
- 8011278: 2930 cmp r1, #48 ; 0x30
|
|
|
- 801127a: d000 beq.n 801127e <tfp_format+0x5e>
|
|
|
- 801127c: e00b b.n 8011296 <tfp_format+0x76>
|
|
|
+ 80111e0: 292d cmp r1, #45 ; 0x2d
|
|
|
+ 80111e2: d00f beq.n 8011204 <tfp_format+0x6c>
|
|
|
+ 80111e4: d804 bhi.n 80111f0 <tfp_format+0x58>
|
|
|
+ 80111e6: 2923 cmp r1, #35 ; 0x23
|
|
|
+ 80111e8: d008 beq.n 80111fc <tfp_format+0x64>
|
|
|
+ 80111ea: 292b cmp r1, #43 ; 0x2b
|
|
|
+ 80111ec: d10f bne.n 801120e <tfp_format+0x76>
|
|
|
+ 80111ee: e007 b.n 8011200 <tfp_format+0x68>
|
|
|
+ 80111f0: 2930 cmp r1, #48 ; 0x30
|
|
|
+ 80111f2: d000 beq.n 80111f6 <tfp_format+0x5e>
|
|
|
+ 80111f4: e00b b.n 801120e <tfp_format+0x76>
|
|
|
case '-':
|
|
|
p.align_left = 1;
|
|
|
continue;
|
|
|
case '0':
|
|
|
p.lz = 1;
|
|
|
- 801127e: f04f 0c01 mov.w ip, #1
|
|
|
+ 80111f6: f04f 0c01 mov.w ip, #1
|
|
|
continue;
|
|
|
- 8011282: e004 b.n 801128e <tfp_format+0x6e>
|
|
|
+ 80111fa: e004 b.n 8011206 <tfp_format+0x6e>
|
|
|
case '#':
|
|
|
p.alt = 1;
|
|
|
- 8011284: 2001 movs r0, #1
|
|
|
+ 80111fc: 2001 movs r0, #1
|
|
|
continue;
|
|
|
- 8011286: e002 b.n 801128e <tfp_format+0x6e>
|
|
|
+ 80111fe: e002 b.n 8011206 <tfp_format+0x6e>
|
|
|
case '+':
|
|
|
p.sign = 1;
|
|
|
- 8011288: 2301 movs r3, #1
|
|
|
+ 8011200: 2301 movs r3, #1
|
|
|
continue;
|
|
|
- 801128a: e000 b.n 801128e <tfp_format+0x6e>
|
|
|
+ 8011202: e000 b.n 8011206 <tfp_format+0x6e>
|
|
|
|
|
|
/* Flags */
|
|
|
while ((ch = *(fmt++))) {
|
|
|
switch (ch) {
|
|
|
case '-':
|
|
|
p.align_left = 1;
|
|
|
- 801128c: 2201 movs r2, #1
|
|
|
+ 8011204: 2201 movs r2, #1
|
|
|
p.align_left = 0;
|
|
|
p.sign = 0;
|
|
|
p.prec = 2;
|
|
|
|
|
|
/* Flags */
|
|
|
while ((ch = *(fmt++))) {
|
|
|
- 801128e: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
- 8011292: 2900 cmp r1, #0
|
|
|
- 8011294: d1e8 bne.n 8011268 <tfp_format+0x48>
|
|
|
- 8011296: f89d 8028 ldrb.w r8, [sp, #40] ; 0x28
|
|
|
- 801129a: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
- 801129e: f36c 0800 bfi r8, ip, #0, #1
|
|
|
- 80112a2: 46c4 mov ip, r8
|
|
|
- 80112a4: f360 0c41 bfi ip, r0, #1, #1
|
|
|
- 80112a8: 4660 mov r0, ip
|
|
|
+ 8011206: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
+ 801120a: 2900 cmp r1, #0
|
|
|
+ 801120c: d1e8 bne.n 80111e0 <tfp_format+0x48>
|
|
|
+ 801120e: f89d 8028 ldrb.w r8, [sp, #40] ; 0x28
|
|
|
+ 8011212: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
+ 8011216: f36c 0800 bfi r8, ip, #0, #1
|
|
|
+ 801121a: 46c4 mov ip, r8
|
|
|
+ 801121c: f360 0c41 bfi ip, r0, #1, #1
|
|
|
+ 8011220: 4660 mov r0, ip
|
|
|
}
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
/* Width */
|
|
|
if (ch >= '0' && ch <= '9') {
|
|
|
- 80112aa: f1a1 0330 sub.w r3, r1, #48 ; 0x30
|
|
|
- 80112ae: f362 00c3 bfi r0, r2, #3, #1
|
|
|
- 80112b2: 2b09 cmp r3, #9
|
|
|
- 80112b4: f88d 0028 strb.w r0, [sp, #40] ; 0x28
|
|
|
- 80112b8: d81d bhi.n 80112f6 <tfp_format+0xd6>
|
|
|
- 80112ba: e004 b.n 80112c6 <tfp_format+0xa6>
|
|
|
+ 8011222: f1a1 0330 sub.w r3, r1, #48 ; 0x30
|
|
|
+ 8011226: f362 00c3 bfi r0, r2, #3, #1
|
|
|
+ 801122a: 2b09 cmp r3, #9
|
|
|
+ 801122c: f88d 0028 strb.w r0, [sp, #40] ; 0x28
|
|
|
+ 8011230: d81d bhi.n 801126e <tfp_format+0xd6>
|
|
|
+ 8011232: e004 b.n 801123e <tfp_format+0xa6>
|
|
|
unsigned int num = 0;
|
|
|
int digit;
|
|
|
while ((digit = a2d(ch)) >= 0) {
|
|
|
if (digit > base)
|
|
|
break;
|
|
|
num = num * base + digit;
|
|
|
- 80112bc: fb00 3202 mla r2, r0, r2, r3
|
|
|
+ 8011234: fb00 3202 mla r2, r0, r2, r3
|
|
|
ch = *p++;
|
|
|
- 80112c0: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
- 80112c4: e001 b.n 80112ca <tfp_format+0xaa>
|
|
|
+ 8011238: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
+ 801123c: e001 b.n 8011242 <tfp_format+0xaa>
|
|
|
}
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
/* Width */
|
|
|
if (ch >= '0' && ch <= '9') {
|
|
|
- 80112c6: 2200 movs r2, #0
|
|
|
+ 801123e: 2200 movs r2, #0
|
|
|
unsigned int num = 0;
|
|
|
int digit;
|
|
|
while ((digit = a2d(ch)) >= 0) {
|
|
|
if (digit > base)
|
|
|
break;
|
|
|
num = num * base + digit;
|
|
|
- 80112c8: 200a movs r0, #10
|
|
|
+ 8011240: 200a movs r0, #10
|
|
|
ui2a(num, p);
|
|
|
}
|
|
|
|
|
|
static int a2d(char ch)
|
|
|
{
|
|
|
if (ch >= '0' && ch <= '9')
|
|
|
- 80112ca: f1a1 0330 sub.w r3, r1, #48 ; 0x30
|
|
|
- 80112ce: fa5f fc83 uxtb.w ip, r3
|
|
|
- 80112d2: f1bc 0f09 cmp.w ip, #9
|
|
|
- 80112d6: d9f1 bls.n 80112bc <tfp_format+0x9c>
|
|
|
+ 8011242: f1a1 0330 sub.w r3, r1, #48 ; 0x30
|
|
|
+ 8011246: fa5f fc83 uxtb.w ip, r3
|
|
|
+ 801124a: f1bc 0f09 cmp.w ip, #9
|
|
|
+ 801124e: d9f1 bls.n 8011234 <tfp_format+0x9c>
|
|
|
return ch - '0';
|
|
|
else if (ch >= 'a' && ch <= 'f')
|
|
|
- 80112d8: f1a1 0361 sub.w r3, r1, #97 ; 0x61
|
|
|
- 80112dc: 2b05 cmp r3, #5
|
|
|
- 80112de: d802 bhi.n 80112e6 <tfp_format+0xc6>
|
|
|
+ 8011250: f1a1 0361 sub.w r3, r1, #97 ; 0x61
|
|
|
+ 8011254: 2b05 cmp r3, #5
|
|
|
+ 8011256: d802 bhi.n 801125e <tfp_format+0xc6>
|
|
|
return ch - 'a' + 10;
|
|
|
- 80112e0: f1a1 0357 sub.w r3, r1, #87 ; 0x57
|
|
|
- 80112e4: e1b5 b.n 8011652 <tfp_format+0x432>
|
|
|
+ 8011258: f1a1 0357 sub.w r3, r1, #87 ; 0x57
|
|
|
+ 801125c: e1b5 b.n 80115ca <tfp_format+0x432>
|
|
|
else if (ch >= 'A' && ch <= 'F')
|
|
|
- 80112e6: f1a1 0341 sub.w r3, r1, #65 ; 0x41
|
|
|
- 80112ea: 2b05 cmp r3, #5
|
|
|
- 80112ec: d802 bhi.n 80112f4 <tfp_format+0xd4>
|
|
|
+ 801125e: f1a1 0341 sub.w r3, r1, #65 ; 0x41
|
|
|
+ 8011262: 2b05 cmp r3, #5
|
|
|
+ 8011264: d802 bhi.n 801126c <tfp_format+0xd4>
|
|
|
return ch - 'A' + 10;
|
|
|
- 80112ee: f1a1 0337 sub.w r3, r1, #55 ; 0x37
|
|
|
- 80112f2: e1ae b.n 8011652 <tfp_format+0x432>
|
|
|
+ 8011266: f1a1 0337 sub.w r3, r1, #55 ; 0x37
|
|
|
+ 801126a: e1ae b.n 80115ca <tfp_format+0x432>
|
|
|
break;
|
|
|
num = num * base + digit;
|
|
|
ch = *p++;
|
|
|
}
|
|
|
*src = p;
|
|
|
*nump = num;
|
|
|
- 80112f4: 920b str r2, [sp, #44] ; 0x2c
|
|
|
+ 801126c: 920b str r2, [sp, #44] ; 0x2c
|
|
|
}
|
|
|
|
|
|
/* We accept 'x.y' format but don't support it completely:
|
|
|
* we ignore the 'y' digit => this ignores 0-fill
|
|
|
* size and makes it == width (ie. 'x') */
|
|
|
if (ch == '.') {
|
|
|
- 80112f6: 292e cmp r1, #46 ; 0x2e
|
|
|
- 80112f8: d10e bne.n 8011318 <tfp_format+0xf8>
|
|
|
+ 801126e: 292e cmp r1, #46 ; 0x2e
|
|
|
+ 8011270: d10e bne.n 8011290 <tfp_format+0xf8>
|
|
|
//p.lz = 1; /* zero-padding */
|
|
|
/* ignore actual 0-fill size: */
|
|
|
ch = *(fmt++);
|
|
|
if (ch >= '0' && ch <= '9')
|
|
|
- 80112fa: 783a ldrb r2, [r7, #0]
|
|
|
- 80112fc: 3a30 subs r2, #48 ; 0x30
|
|
|
- 80112fe: b2d2 uxtb r2, r2
|
|
|
+ 8011272: 783a ldrb r2, [r7, #0]
|
|
|
+ 8011274: 3a30 subs r2, #48 ; 0x30
|
|
|
+ 8011276: b2d2 uxtb r2, r2
|
|
|
* we ignore the 'y' digit => this ignores 0-fill
|
|
|
* size and makes it == width (ie. 'x') */
|
|
|
if (ch == '.') {
|
|
|
//p.lz = 1; /* zero-padding */
|
|
|
/* ignore actual 0-fill size: */
|
|
|
ch = *(fmt++);
|
|
|
- 8011300: 1c7b adds r3, r7, #1
|
|
|
+ 8011278: 1c7b adds r3, r7, #1
|
|
|
if (ch >= '0' && ch <= '9')
|
|
|
- 8011302: 2a09 cmp r2, #9
|
|
|
+ 801127a: 2a09 cmp r2, #9
|
|
|
p.prec = ch - '0';
|
|
|
- 8011304: bf98 it ls
|
|
|
- 8011306: f88d 203c strbls.w r2, [sp, #60] ; 0x3c
|
|
|
+ 801127c: bf98 it ls
|
|
|
+ 801127e: f88d 203c strbls.w r2, [sp, #60] ; 0x3c
|
|
|
do
|
|
|
{
|
|
|
ch = *(fmt++);
|
|
|
- 801130a: f813 1b01 ldrb.w r1, [r3], #1
|
|
|
+ 8011282: f813 1b01 ldrb.w r1, [r3], #1
|
|
|
} while (ch >= '0' && ch <= '9');
|
|
|
- 801130e: f1a1 0230 sub.w r2, r1, #48 ; 0x30
|
|
|
- 8011312: 2a09 cmp r2, #9
|
|
|
+ 8011286: f1a1 0230 sub.w r2, r1, #48 ; 0x30
|
|
|
+ 801128a: 2a09 cmp r2, #9
|
|
|
ch = *(fmt++);
|
|
|
if (ch >= '0' && ch <= '9')
|
|
|
p.prec = ch - '0';
|
|
|
do
|
|
|
{
|
|
|
ch = *(fmt++);
|
|
|
- 8011314: 461f mov r7, r3
|
|
|
+ 801128c: 461f mov r7, r3
|
|
|
} while (ch >= '0' && ch <= '9');
|
|
|
- 8011316: d9f8 bls.n 801130a <tfp_format+0xea>
|
|
|
+ 801128e: d9f8 bls.n 8011282 <tfp_format+0xea>
|
|
|
|
|
|
}
|
|
|
|
|
|
#ifdef PRINTF_SIZE_T_SUPPORT
|
|
|
# ifdef PRINTF_LONG_SUPPORT
|
|
|
if (ch == 'z') {
|
|
|
- 8011318: 297a cmp r1, #122 ; 0x7a
|
|
|
- 801131a: d102 bne.n 8011322 <tfp_format+0x102>
|
|
|
+ 8011290: 297a cmp r1, #122 ; 0x7a
|
|
|
+ 8011292: d102 bne.n 801129a <tfp_format+0x102>
|
|
|
ch = *(fmt++);
|
|
|
- 801131c: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
- 8011320: e005 b.n 801132e <tfp_format+0x10e>
|
|
|
+ 8011294: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
+ 8011298: e005 b.n 80112a6 <tfp_format+0x10e>
|
|
|
} else
|
|
|
# endif
|
|
|
#endif
|
|
|
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
if (ch == 'l') {
|
|
|
- 8011322: 296c cmp r1, #108 ; 0x6c
|
|
|
- 8011324: d109 bne.n 801133a <tfp_format+0x11a>
|
|
|
+ 801129a: 296c cmp r1, #108 ; 0x6c
|
|
|
+ 801129c: d109 bne.n 80112b2 <tfp_format+0x11a>
|
|
|
ch = *(fmt++);
|
|
|
- 8011326: 7839 ldrb r1, [r7, #0]
|
|
|
+ 801129e: 7839 ldrb r1, [r7, #0]
|
|
|
lng = 1;
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (ch == 'l') {
|
|
|
- 8011328: 296c cmp r1, #108 ; 0x6c
|
|
|
- 801132a: d002 beq.n 8011332 <tfp_format+0x112>
|
|
|
+ 80112a0: 296c cmp r1, #108 ; 0x6c
|
|
|
+ 80112a2: d002 beq.n 80112aa <tfp_format+0x112>
|
|
|
# endif
|
|
|
#endif
|
|
|
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
if (ch == 'l') {
|
|
|
ch = *(fmt++);
|
|
|
- 801132c: 3701 adds r7, #1
|
|
|
+ 80112a4: 3701 adds r7, #1
|
|
|
lng = 1;
|
|
|
- 801132e: 2301 movs r3, #1
|
|
|
- 8011330: e004 b.n 801133c <tfp_format+0x11c>
|
|
|
+ 80112a6: 2301 movs r3, #1
|
|
|
+ 80112a8: e004 b.n 80112b4 <tfp_format+0x11c>
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (ch == 'l') {
|
|
|
ch = *(fmt++);
|
|
|
- 8011332: 7879 ldrb r1, [r7, #1]
|
|
|
+ 80112aa: 7879 ldrb r1, [r7, #1]
|
|
|
lng = 2;
|
|
|
- 8011334: 2302 movs r3, #2
|
|
|
+ 80112ac: 2302 movs r3, #2
|
|
|
if (ch == 'l') {
|
|
|
ch = *(fmt++);
|
|
|
lng = 1;
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (ch == 'l') {
|
|
|
ch = *(fmt++);
|
|
|
- 8011336: 3702 adds r7, #2
|
|
|
- 8011338: e000 b.n 801133c <tfp_format+0x11c>
|
|
|
+ 80112ae: 3702 adds r7, #2
|
|
|
+ 80112b0: e000 b.n 80112b4 <tfp_format+0x11c>
|
|
|
while ((ch = *(fmt++))) {
|
|
|
if (ch != '%') {
|
|
|
putf(putp, ch);
|
|
|
} else {
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
char lng = 0; /* 1 for long, 2 for long long */
|
|
|
- 801133a: 2300 movs r3, #0
|
|
|
+ 80112b2: 2300 movs r3, #0
|
|
|
lng = 2;
|
|
|
}
|
|
|
#endif
|
|
|
}
|
|
|
#endif
|
|
|
switch (ch) {
|
|
|
- 801133c: 2969 cmp r1, #105 ; 0x69
|
|
|
- 801133e: d036 beq.n 80113ae <tfp_format+0x18e>
|
|
|
- 8011340: d816 bhi.n 8011370 <tfp_format+0x150>
|
|
|
- 8011342: 2963 cmp r1, #99 ; 0x63
|
|
|
- 8011344: f000 80a1 beq.w 801148a <tfp_format+0x26a>
|
|
|
- 8011348: d80c bhi.n 8011364 <tfp_format+0x144>
|
|
|
- 801134a: 2946 cmp r1, #70 ; 0x46
|
|
|
- 801134c: f000 80b3 beq.w 80114b6 <tfp_format+0x296>
|
|
|
- 8011350: d806 bhi.n 8011360 <tfp_format+0x140>
|
|
|
- 8011352: 2900 cmp r1, #0
|
|
|
- 8011354: f000 8181 beq.w 801165a <tfp_format+0x43a>
|
|
|
- 8011358: 2925 cmp r1, #37 ; 0x25
|
|
|
- 801135a: f040 8174 bne.w 8011646 <tfp_format+0x426>
|
|
|
- 801135e: e0a7 b.n 80114b0 <tfp_format+0x290>
|
|
|
- 8011360: 2958 cmp r1, #88 ; 0x58
|
|
|
- 8011362: e012 b.n 801138a <tfp_format+0x16a>
|
|
|
- 8011364: 2964 cmp r1, #100 ; 0x64
|
|
|
- 8011366: d022 beq.n 80113ae <tfp_format+0x18e>
|
|
|
- 8011368: 2966 cmp r1, #102 ; 0x66
|
|
|
- 801136a: f040 816c bne.w 8011646 <tfp_format+0x426>
|
|
|
- 801136e: e0a2 b.n 80114b6 <tfp_format+0x296>
|
|
|
- 8011370: 2973 cmp r1, #115 ; 0x73
|
|
|
- 8011372: f000 8090 beq.w 8011496 <tfp_format+0x276>
|
|
|
- 8011376: d805 bhi.n 8011384 <tfp_format+0x164>
|
|
|
- 8011378: 296f cmp r1, #111 ; 0x6f
|
|
|
- 801137a: d078 beq.n 801146e <tfp_format+0x24e>
|
|
|
- 801137c: 2970 cmp r1, #112 ; 0x70
|
|
|
- 801137e: f040 8162 bne.w 8011646 <tfp_format+0x426>
|
|
|
- 8011382: e040 b.n 8011406 <tfp_format+0x1e6>
|
|
|
- 8011384: 2975 cmp r1, #117 ; 0x75
|
|
|
- 8011386: d003 beq.n 8011390 <tfp_format+0x170>
|
|
|
- 8011388: 2978 cmp r1, #120 ; 0x78
|
|
|
- 801138a: f040 815c bne.w 8011646 <tfp_format+0x426>
|
|
|
- 801138e: e041 b.n 8011414 <tfp_format+0x1f4>
|
|
|
+ 80112b4: 2969 cmp r1, #105 ; 0x69
|
|
|
+ 80112b6: d036 beq.n 8011326 <tfp_format+0x18e>
|
|
|
+ 80112b8: d816 bhi.n 80112e8 <tfp_format+0x150>
|
|
|
+ 80112ba: 2963 cmp r1, #99 ; 0x63
|
|
|
+ 80112bc: f000 80a1 beq.w 8011402 <tfp_format+0x26a>
|
|
|
+ 80112c0: d80c bhi.n 80112dc <tfp_format+0x144>
|
|
|
+ 80112c2: 2946 cmp r1, #70 ; 0x46
|
|
|
+ 80112c4: f000 80b3 beq.w 801142e <tfp_format+0x296>
|
|
|
+ 80112c8: d806 bhi.n 80112d8 <tfp_format+0x140>
|
|
|
+ 80112ca: 2900 cmp r1, #0
|
|
|
+ 80112cc: f000 8181 beq.w 80115d2 <tfp_format+0x43a>
|
|
|
+ 80112d0: 2925 cmp r1, #37 ; 0x25
|
|
|
+ 80112d2: f040 8174 bne.w 80115be <tfp_format+0x426>
|
|
|
+ 80112d6: e0a7 b.n 8011428 <tfp_format+0x290>
|
|
|
+ 80112d8: 2958 cmp r1, #88 ; 0x58
|
|
|
+ 80112da: e012 b.n 8011302 <tfp_format+0x16a>
|
|
|
+ 80112dc: 2964 cmp r1, #100 ; 0x64
|
|
|
+ 80112de: d022 beq.n 8011326 <tfp_format+0x18e>
|
|
|
+ 80112e0: 2966 cmp r1, #102 ; 0x66
|
|
|
+ 80112e2: f040 816c bne.w 80115be <tfp_format+0x426>
|
|
|
+ 80112e6: e0a2 b.n 801142e <tfp_format+0x296>
|
|
|
+ 80112e8: 2973 cmp r1, #115 ; 0x73
|
|
|
+ 80112ea: f000 8090 beq.w 801140e <tfp_format+0x276>
|
|
|
+ 80112ee: d805 bhi.n 80112fc <tfp_format+0x164>
|
|
|
+ 80112f0: 296f cmp r1, #111 ; 0x6f
|
|
|
+ 80112f2: d078 beq.n 80113e6 <tfp_format+0x24e>
|
|
|
+ 80112f4: 2970 cmp r1, #112 ; 0x70
|
|
|
+ 80112f6: f040 8162 bne.w 80115be <tfp_format+0x426>
|
|
|
+ 80112fa: e040 b.n 801137e <tfp_format+0x1e6>
|
|
|
+ 80112fc: 2975 cmp r1, #117 ; 0x75
|
|
|
+ 80112fe: d003 beq.n 8011308 <tfp_format+0x170>
|
|
|
+ 8011300: 2978 cmp r1, #120 ; 0x78
|
|
|
+ 8011302: f040 815c bne.w 80115be <tfp_format+0x426>
|
|
|
+ 8011306: e041 b.n 801138c <tfp_format+0x1f4>
|
|
|
case 0:
|
|
|
goto abort;
|
|
|
case 'u':
|
|
|
p.base = 10;
|
|
|
- 8011390: 220a movs r2, #10
|
|
|
+ 8011308: 220a movs r2, #10
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 8011392: 2b02 cmp r3, #2
|
|
|
+ 801130a: 2b02 cmp r3, #2
|
|
|
#endif
|
|
|
switch (ch) {
|
|
|
case 0:
|
|
|
goto abort;
|
|
|
case 'u':
|
|
|
p.base = 10;
|
|
|
- 8011394: 920d str r2, [sp, #52] ; 0x34
|
|
|
+ 801130c: 920d str r2, [sp, #52] ; 0x34
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 8011396: d107 bne.n 80113a8 <tfp_format+0x188>
|
|
|
+ 801130e: d107 bne.n 8011320 <tfp_format+0x188>
|
|
|
ulli2a(va_arg(va, unsigned long long int), &p);
|
|
|
- 8011398: 3407 adds r4, #7
|
|
|
- 801139a: f024 0307 bic.w r3, r4, #7
|
|
|
- 801139e: f103 0408 add.w r4, r3, #8
|
|
|
- 80113a2: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
- 80113a6: e017 b.n 80113d8 <tfp_format+0x1b8>
|
|
|
+ 8011310: 3407 adds r4, #7
|
|
|
+ 8011312: f024 0307 bic.w r3, r4, #7
|
|
|
+ 8011316: f103 0408 add.w r4, r3, #8
|
|
|
+ 801131a: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
+ 801131e: e017 b.n 8011350 <tfp_format+0x1b8>
|
|
|
else
|
|
|
#endif
|
|
|
if (1 == lng)
|
|
|
uli2a(va_arg(va, unsigned long int), &p);
|
|
|
- 80113a8: 6820 ldr r0, [r4, #0]
|
|
|
- 80113aa: a90a add r1, sp, #40 ; 0x28
|
|
|
- 80113ac: e04f b.n 801144e <tfp_format+0x22e>
|
|
|
+ 8011320: 6820 ldr r0, [r4, #0]
|
|
|
+ 8011322: a90a add r1, sp, #40 ; 0x28
|
|
|
+ 8011324: e04f b.n 80113c6 <tfp_format+0x22e>
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
putchw(putp, putf, &p);
|
|
|
break;
|
|
|
case 'd':
|
|
|
case 'i':
|
|
|
p.base = 10;
|
|
|
- 80113ae: 220a movs r2, #10
|
|
|
+ 8011326: 220a movs r2, #10
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 80113b0: 2b02 cmp r3, #2
|
|
|
+ 8011328: 2b02 cmp r3, #2
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
putchw(putp, putf, &p);
|
|
|
break;
|
|
|
case 'd':
|
|
|
case 'i':
|
|
|
p.base = 10;
|
|
|
- 80113b2: 920d str r2, [sp, #52] ; 0x34
|
|
|
+ 801132a: 920d str r2, [sp, #52] ; 0x34
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 80113b4: d112 bne.n 80113dc <tfp_format+0x1bc>
|
|
|
+ 801132c: d112 bne.n 8011354 <tfp_format+0x1bc>
|
|
|
lli2a(va_arg(va, long long int), &p);
|
|
|
- 80113b6: 3407 adds r4, #7
|
|
|
- 80113b8: f024 0307 bic.w r3, r4, #7
|
|
|
- 80113bc: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
- 80113c0: f103 0408 add.w r4, r3, #8
|
|
|
+ 801132e: 3407 adds r4, #7
|
|
|
+ 8011330: f024 0307 bic.w r3, r4, #7
|
|
|
+ 8011334: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
+ 8011338: f103 0408 add.w r4, r3, #8
|
|
|
*bf = 0;
|
|
|
}
|
|
|
|
|
|
static void lli2a(long long int num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
- 80113c4: 2800 cmp r0, #0
|
|
|
- 80113c6: f171 0300 sbcs.w r3, r1, #0
|
|
|
- 80113ca: da05 bge.n 80113d8 <tfp_format+0x1b8>
|
|
|
+ 801133c: 2800 cmp r0, #0
|
|
|
+ 801133e: f171 0300 sbcs.w r3, r1, #0
|
|
|
+ 8011342: da05 bge.n 8011350 <tfp_format+0x1b8>
|
|
|
num = -num;
|
|
|
p->sign = '-';
|
|
|
- 80113cc: 232d movs r3, #45 ; 0x2d
|
|
|
+ 8011344: 232d movs r3, #45 ; 0x2d
|
|
|
}
|
|
|
|
|
|
static void lli2a(long long int num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
num = -num;
|
|
|
- 80113ce: 4240 negs r0, r0
|
|
|
- 80113d0: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
|
+ 8011346: 4240 negs r0, r0
|
|
|
+ 8011348: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
|
p->sign = '-';
|
|
|
- 80113d4: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
+ 801134c: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
}
|
|
|
ulli2a(num, p);
|
|
|
- 80113d8: aa0a add r2, sp, #40 ; 0x28
|
|
|
- 80113da: e033 b.n 8011444 <tfp_format+0x224>
|
|
|
+ 8011350: aa0a add r2, sp, #40 ; 0x28
|
|
|
+ 8011352: e033 b.n 80113bc <tfp_format+0x224>
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
lli2a(va_arg(va, long long int), &p);
|
|
|
else
|
|
|
#endif
|
|
|
if (1 == lng)
|
|
|
- 80113dc: 2b01 cmp r3, #1
|
|
|
+ 8011354: 2b01 cmp r3, #1
|
|
|
li2a(va_arg(va, long int), &p);
|
|
|
- 80113de: 6820 ldr r0, [r4, #0]
|
|
|
- 80113e0: f104 0804 add.w r8, r4, #4
|
|
|
+ 8011356: 6820 ldr r0, [r4, #0]
|
|
|
+ 8011358: f104 0804 add.w r8, r4, #4
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
lli2a(va_arg(va, long long int), &p);
|
|
|
else
|
|
|
#endif
|
|
|
if (1 == lng)
|
|
|
- 80113e4: d107 bne.n 80113f6 <tfp_format+0x1d6>
|
|
|
+ 801135c: d107 bne.n 801136e <tfp_format+0x1d6>
|
|
|
*bf = 0;
|
|
|
}
|
|
|
|
|
|
static void li2a(long num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
- 80113e6: 2800 cmp r0, #0
|
|
|
- 80113e8: da03 bge.n 80113f2 <tfp_format+0x1d2>
|
|
|
+ 801135e: 2800 cmp r0, #0
|
|
|
+ 8011360: da03 bge.n 801136a <tfp_format+0x1d2>
|
|
|
num = -num;
|
|
|
p->sign = '-';
|
|
|
- 80113ea: 232d movs r3, #45 ; 0x2d
|
|
|
+ 8011362: 232d movs r3, #45 ; 0x2d
|
|
|
}
|
|
|
|
|
|
static void li2a(long num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
num = -num;
|
|
|
- 80113ec: 4240 negs r0, r0
|
|
|
+ 8011364: 4240 negs r0, r0
|
|
|
p->sign = '-';
|
|
|
- 80113ee: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
+ 8011366: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
}
|
|
|
uli2a(num, p);
|
|
|
- 80113f2: a90a add r1, sp, #40 ; 0x28
|
|
|
- 80113f4: e02f b.n 8011456 <tfp_format+0x236>
|
|
|
+ 801136a: a90a add r1, sp, #40 ; 0x28
|
|
|
+ 801136c: e02f b.n 80113ce <tfp_format+0x236>
|
|
|
*bf = 0;
|
|
|
}
|
|
|
|
|
|
static void i2a(int num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
- 80113f6: 2800 cmp r0, #0
|
|
|
- 80113f8: da03 bge.n 8011402 <tfp_format+0x1e2>
|
|
|
+ 801136e: 2800 cmp r0, #0
|
|
|
+ 8011370: da03 bge.n 801137a <tfp_format+0x1e2>
|
|
|
num = -num;
|
|
|
p->sign = '-';
|
|
|
- 80113fa: 232d movs r3, #45 ; 0x2d
|
|
|
+ 8011372: 232d movs r3, #45 ; 0x2d
|
|
|
}
|
|
|
|
|
|
static void i2a(int num, struct param *p)
|
|
|
{
|
|
|
if (num < 0) {
|
|
|
num = -num;
|
|
|
- 80113fc: 4240 negs r0, r0
|
|
|
+ 8011374: 4240 negs r0, r0
|
|
|
p->sign = '-';
|
|
|
- 80113fe: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
+ 8011376: f88d 3030 strb.w r3, [sp, #48] ; 0x30
|
|
|
}
|
|
|
ui2a(num, p);
|
|
|
- 8011402: a90a add r1, sp, #40 ; 0x28
|
|
|
- 8011404: e02a b.n 801145c <tfp_format+0x23c>
|
|
|
+ 801137a: a90a add r1, sp, #40 ; 0x28
|
|
|
+ 801137c: e02a b.n 80113d4 <tfp_format+0x23c>
|
|
|
i2a(va_arg(va, int), &p);
|
|
|
putchw(putp, putf, &p);
|
|
|
break;
|
|
|
#ifdef SIZEOF_POINTER
|
|
|
case 'p':
|
|
|
p.alt = 1;
|
|
|
- 8011406: f89d 3028 ldrb.w r3, [sp, #40] ; 0x28
|
|
|
- 801140a: f043 0302 orr.w r3, r3, #2
|
|
|
- 801140e: f88d 3028 strb.w r3, [sp, #40] ; 0x28
|
|
|
+ 801137e: f89d 3028 ldrb.w r3, [sp, #40] ; 0x28
|
|
|
+ 8011382: f043 0302 orr.w r3, r3, #2
|
|
|
+ 8011386: f88d 3028 strb.w r3, [sp, #40] ; 0x28
|
|
|
# if defined(SIZEOF_INT) && SIZEOF_POINTER <= SIZEOF_INT
|
|
|
lng = 0;
|
|
|
- 8011412: 2300 movs r3, #0
|
|
|
+ 801138a: 2300 movs r3, #0
|
|
|
lng = 2;
|
|
|
# endif
|
|
|
#endif
|
|
|
case 'x':
|
|
|
case 'X':
|
|
|
p.base = 16;
|
|
|
- 8011414: 2210 movs r2, #16
|
|
|
+ 801138c: 2210 movs r2, #16
|
|
|
p.uc = (ch == 'X')?1:0;
|
|
|
- 8011416: f1b1 0e58 subs.w lr, r1, #88 ; 0x58
|
|
|
- 801141a: f1de 0100 rsbs r1, lr, #0
|
|
|
- 801141e: f89d 0028 ldrb.w r0, [sp, #40] ; 0x28
|
|
|
+ 801138e: f1b1 0e58 subs.w lr, r1, #88 ; 0x58
|
|
|
+ 8011392: f1de 0100 rsbs r1, lr, #0
|
|
|
+ 8011396: f89d 0028 ldrb.w r0, [sp, #40] ; 0x28
|
|
|
lng = 2;
|
|
|
# endif
|
|
|
#endif
|
|
|
case 'x':
|
|
|
case 'X':
|
|
|
p.base = 16;
|
|
|
- 8011422: 920d str r2, [sp, #52] ; 0x34
|
|
|
+ 801139a: 920d str r2, [sp, #52] ; 0x34
|
|
|
p.uc = (ch == 'X')?1:0;
|
|
|
- 8011424: eb51 010e adcs.w r1, r1, lr
|
|
|
- 8011428: aa1a add r2, sp, #104 ; 0x68
|
|
|
- 801142a: f361 0082 bfi r0, r1, #2, #1
|
|
|
+ 801139c: eb51 010e adcs.w r1, r1, lr
|
|
|
+ 80113a0: aa1a add r2, sp, #104 ; 0x68
|
|
|
+ 80113a2: f361 0082 bfi r0, r1, #2, #1
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 801142e: 2b02 cmp r3, #2
|
|
|
+ 80113a6: 2b02 cmp r3, #2
|
|
|
# endif
|
|
|
#endif
|
|
|
case 'x':
|
|
|
case 'X':
|
|
|
p.base = 16;
|
|
|
p.uc = (ch == 'X')?1:0;
|
|
|
- 8011430: f802 0d40 strb.w r0, [r2, #-64]!
|
|
|
+ 80113a8: f802 0d40 strb.w r0, [r2, #-64]!
|
|
|
#ifdef PRINTF_LONG_SUPPORT
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
- 8011434: d109 bne.n 801144a <tfp_format+0x22a>
|
|
|
+ 80113ac: d109 bne.n 80113c2 <tfp_format+0x22a>
|
|
|
ulli2a(va_arg(va, unsigned long long int), &p);
|
|
|
- 8011436: 3407 adds r4, #7
|
|
|
- 8011438: f024 0307 bic.w r3, r4, #7
|
|
|
- 801143c: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
- 8011440: f103 0408 add.w r4, r3, #8
|
|
|
- 8011444: f7ff fdc8 bl 8010fd8 <ulli2a>
|
|
|
- 8011448: e00b b.n 8011462 <tfp_format+0x242>
|
|
|
+ 80113ae: 3407 adds r4, #7
|
|
|
+ 80113b0: f024 0307 bic.w r3, r4, #7
|
|
|
+ 80113b4: e9d3 0100 ldrd r0, r1, [r3]
|
|
|
+ 80113b8: f103 0408 add.w r4, r3, #8
|
|
|
+ 80113bc: f7ff fdc8 bl 8010f50 <ulli2a>
|
|
|
+ 80113c0: e00b b.n 80113da <tfp_format+0x242>
|
|
|
else
|
|
|
#endif
|
|
|
if (1 == lng)
|
|
|
uli2a(va_arg(va, unsigned long int), &p);
|
|
|
- 801144a: 6820 ldr r0, [r4, #0]
|
|
|
- 801144c: 4611 mov r1, r2
|
|
|
+ 80113c2: 6820 ldr r0, [r4, #0]
|
|
|
+ 80113c4: 4611 mov r1, r2
|
|
|
#ifdef PRINTF_LONG_LONG_SUPPORT
|
|
|
if (2 == lng)
|
|
|
ulli2a(va_arg(va, unsigned long long int), &p);
|
|
|
else
|
|
|
#endif
|
|
|
if (1 == lng)
|
|
|
- 801144e: 2b01 cmp r3, #1
|
|
|
- 8011450: f104 0804 add.w r8, r4, #4
|
|
|
- 8011454: d102 bne.n 801145c <tfp_format+0x23c>
|
|
|
+ 80113c6: 2b01 cmp r3, #1
|
|
|
+ 80113c8: f104 0804 add.w r8, r4, #4
|
|
|
+ 80113cc: d102 bne.n 80113d4 <tfp_format+0x23c>
|
|
|
uli2a(va_arg(va, unsigned long int), &p);
|
|
|
- 8011456: f7ff fe15 bl 8011084 <uli2a>
|
|
|
- 801145a: e001 b.n 8011460 <tfp_format+0x240>
|
|
|
+ 80113ce: f7ff fe15 bl 8010ffc <uli2a>
|
|
|
+ 80113d2: e001 b.n 80113d8 <tfp_format+0x240>
|
|
|
else
|
|
|
#endif
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
- 801145c: f7ff fe3d bl 80110da <ui2a>
|
|
|
- 8011460: 4644 mov r4, r8
|
|
|
+ 80113d4: f7ff fe3d bl 8011052 <ui2a>
|
|
|
+ 80113d8: 4644 mov r4, r8
|
|
|
putchw(putp, putf, &p);
|
|
|
- 8011462: 4628 mov r0, r5
|
|
|
- 8011464: 4631 mov r1, r6
|
|
|
- 8011466: aa0a add r2, sp, #40 ; 0x28
|
|
|
- 8011468: f7ff fe62 bl 8011130 <putchw>
|
|
|
+ 80113da: 4628 mov r0, r5
|
|
|
+ 80113dc: 4631 mov r1, r6
|
|
|
+ 80113de: aa0a add r2, sp, #40 ; 0x28
|
|
|
+ 80113e0: f7ff fe62 bl 80110a8 <putchw>
|
|
|
break;
|
|
|
- 801146c: e0eb b.n 8011646 <tfp_format+0x426>
|
|
|
+ 80113e4: e0eb b.n 80115be <tfp_format+0x426>
|
|
|
case 'o':
|
|
|
p.base = 8;
|
|
|
- 801146e: 2308 movs r3, #8
|
|
|
+ 80113e6: 2308 movs r3, #8
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
- 8011470: 6820 ldr r0, [r4, #0]
|
|
|
+ 80113e8: 6820 ldr r0, [r4, #0]
|
|
|
#endif
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
putchw(putp, putf, &p);
|
|
|
break;
|
|
|
case 'o':
|
|
|
p.base = 8;
|
|
|
- 8011472: 930d str r3, [sp, #52] ; 0x34
|
|
|
+ 80113ea: 930d str r3, [sp, #52] ; 0x34
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
- 8011474: a90a add r1, sp, #40 ; 0x28
|
|
|
- 8011476: f7ff fe30 bl 80110da <ui2a>
|
|
|
+ 80113ec: a90a add r1, sp, #40 ; 0x28
|
|
|
+ 80113ee: f7ff fe30 bl 8011052 <ui2a>
|
|
|
putchw(putp, putf, &p);
|
|
|
- 801147a: 4628 mov r0, r5
|
|
|
- 801147c: 4631 mov r1, r6
|
|
|
- 801147e: aa0a add r2, sp, #40 ; 0x28
|
|
|
+ 80113f2: 4628 mov r0, r5
|
|
|
+ 80113f4: 4631 mov r1, r6
|
|
|
+ 80113f6: aa0a add r2, sp, #40 ; 0x28
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
putchw(putp, putf, &p);
|
|
|
break;
|
|
|
case 'o':
|
|
|
p.base = 8;
|
|
|
ui2a(va_arg(va, unsigned int), &p);
|
|
|
- 8011480: f104 0804 add.w r8, r4, #4
|
|
|
+ 80113f8: f104 0804 add.w r8, r4, #4
|
|
|
putchw(putp, putf, &p);
|
|
|
- 8011484: f7ff fe54 bl 8011130 <putchw>
|
|
|
- 8011488: e010 b.n 80114ac <tfp_format+0x28c>
|
|
|
+ 80113fc: f7ff fe54 bl 80110a8 <putchw>
|
|
|
+ 8011400: e010 b.n 8011424 <tfp_format+0x28c>
|
|
|
break;
|
|
|
case 'c':
|
|
|
putf(putp, (char)(va_arg(va, int)));
|
|
|
- 801148a: 4628 mov r0, r5
|
|
|
- 801148c: 7821 ldrb r1, [r4, #0]
|
|
|
- 801148e: f104 0804 add.w r8, r4, #4
|
|
|
- 8011492: 47b0 blx r6
|
|
|
- 8011494: e00a b.n 80114ac <tfp_format+0x28c>
|
|
|
+ 8011402: 4628 mov r0, r5
|
|
|
+ 8011404: 7821 ldrb r1, [r4, #0]
|
|
|
+ 8011406: f104 0804 add.w r8, r4, #4
|
|
|
+ 801140a: 47b0 blx r6
|
|
|
+ 801140c: e00a b.n 8011424 <tfp_format+0x28c>
|
|
|
break;
|
|
|
case 's':
|
|
|
p.bf = va_arg(va, char *);
|
|
|
- 8011496: 6823 ldr r3, [r4, #0]
|
|
|
+ 801140e: 6823 ldr r3, [r4, #0]
|
|
|
putchw(putp, putf, &p);
|
|
|
- 8011498: aa0a add r2, sp, #40 ; 0x28
|
|
|
- 801149a: 4628 mov r0, r5
|
|
|
- 801149c: 4631 mov r1, r6
|
|
|
+ 8011410: aa0a add r2, sp, #40 ; 0x28
|
|
|
+ 8011412: 4628 mov r0, r5
|
|
|
+ 8011414: 4631 mov r1, r6
|
|
|
break;
|
|
|
case 'c':
|
|
|
putf(putp, (char)(va_arg(va, int)));
|
|
|
break;
|
|
|
case 's':
|
|
|
p.bf = va_arg(va, char *);
|
|
|
- 801149e: 930e str r3, [sp, #56] ; 0x38
|
|
|
+ 8011416: 930e str r3, [sp, #56] ; 0x38
|
|
|
putchw(putp, putf, &p);
|
|
|
- 80114a0: f7ff fe46 bl 8011130 <putchw>
|
|
|
+ 8011418: f7ff fe46 bl 80110a8 <putchw>
|
|
|
p.bf = bf;
|
|
|
- 80114a4: aa04 add r2, sp, #16
|
|
|
+ 801141c: aa04 add r2, sp, #16
|
|
|
break;
|
|
|
case 'c':
|
|
|
putf(putp, (char)(va_arg(va, int)));
|
|
|
break;
|
|
|
case 's':
|
|
|
p.bf = va_arg(va, char *);
|
|
|
- 80114a6: f104 0804 add.w r8, r4, #4
|
|
|
+ 801141e: f104 0804 add.w r8, r4, #4
|
|
|
putchw(putp, putf, &p);
|
|
|
p.bf = bf;
|
|
|
- 80114aa: 920e str r2, [sp, #56] ; 0x38
|
|
|
+ 8011422: 920e str r2, [sp, #56] ; 0x38
|
|
|
break;
|
|
|
case 'c':
|
|
|
putf(putp, (char)(va_arg(va, int)));
|
|
|
break;
|
|
|
case 's':
|
|
|
p.bf = va_arg(va, char *);
|
|
|
- 80114ac: 4644 mov r4, r8
|
|
|
+ 8011424: 4644 mov r4, r8
|
|
|
putchw(putp, putf, &p);
|
|
|
p.bf = bf;
|
|
|
break;
|
|
|
- 80114ae: e0ca b.n 8011646 <tfp_format+0x426>
|
|
|
+ 8011426: e0ca b.n 80115be <tfp_format+0x426>
|
|
|
case '%':
|
|
|
putf(putp, ch);
|
|
|
- 80114b0: 4628 mov r0, r5
|
|
|
- 80114b2: 47b0 blx r6
|
|
|
+ 8011428: 4628 mov r0, r5
|
|
|
+ 801142a: 47b0 blx r6
|
|
|
break;
|
|
|
- 80114b4: e0c7 b.n 8011646 <tfp_format+0x426>
|
|
|
+ 801142c: e0c7 b.n 80115be <tfp_format+0x426>
|
|
|
case 'f':
|
|
|
case 'F':
|
|
|
fval = va_arg(va, double);
|
|
|
- 80114b6: 3407 adds r4, #7
|
|
|
- 80114b8: f024 0307 bic.w r3, r4, #7
|
|
|
- 80114bc: f103 0408 add.w r4, r3, #8
|
|
|
- 80114c0: e893 0404 ldmia.w r3, {r2, sl}
|
|
|
- 80114c4: 9200 str r2, [sp, #0]
|
|
|
+ 801142e: 3407 adds r4, #7
|
|
|
+ 8011430: f024 0307 bic.w r3, r4, #7
|
|
|
+ 8011434: f103 0408 add.w r4, r3, #8
|
|
|
+ 8011438: e893 0404 ldmia.w r3, {r2, sl}
|
|
|
+ 801143c: 9200 str r2, [sp, #0]
|
|
|
sign = 0;
|
|
|
if (fval < 0)
|
|
|
- 80114c6: 4610 mov r0, r2
|
|
|
- 80114c8: 4651 mov r1, sl
|
|
|
- 80114ca: 2200 movs r2, #0
|
|
|
- 80114cc: 2300 movs r3, #0
|
|
|
- 80114ce: f7f7 fa25 bl 800891c <__aeabi_dcmplt>
|
|
|
- 80114d2: b138 cbz r0, 80114e4 <tfp_format+0x2c4>
|
|
|
+ 801143e: 4610 mov r0, r2
|
|
|
+ 8011440: 4651 mov r1, sl
|
|
|
+ 8011442: 2200 movs r2, #0
|
|
|
+ 8011444: 2300 movs r3, #0
|
|
|
+ 8011446: f7f7 fa69 bl 800891c <__aeabi_dcmplt>
|
|
|
+ 801144a: b138 cbz r0, 801145c <tfp_format+0x2c4>
|
|
|
{
|
|
|
sign = 1;
|
|
|
p.width--;
|
|
|
- 80114d4: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
- 80114d6: 3b01 subs r3, #1
|
|
|
- 80114d8: 930b str r3, [sp, #44] ; 0x2c
|
|
|
+ 801144c: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
+ 801144e: 3b01 subs r3, #1
|
|
|
+ 8011450: 930b str r3, [sp, #44] ; 0x2c
|
|
|
fval = - fval;
|
|
|
- 80114da: f10a 4a00 add.w sl, sl, #2147483648 ; 0x80000000
|
|
|
+ 8011452: f10a 4a00 add.w sl, sl, #2147483648 ; 0x80000000
|
|
|
case 'F':
|
|
|
fval = va_arg(va, double);
|
|
|
sign = 0;
|
|
|
if (fval < 0)
|
|
|
{
|
|
|
sign = 1;
|
|
|
- 80114de: f04f 0b01 mov.w fp, #1
|
|
|
- 80114e2: e009 b.n 80114f8 <tfp_format+0x2d8>
|
|
|
+ 8011456: f04f 0b01 mov.w fp, #1
|
|
|
+ 801145a: e009 b.n 8011470 <tfp_format+0x2d8>
|
|
|
p.width--;
|
|
|
fval = - fval;
|
|
|
}
|
|
|
else if (p.sign) {
|
|
|
- 80114e4: f89d 3030 ldrb.w r3, [sp, #48] ; 0x30
|
|
|
- 80114e8: b12b cbz r3, 80114f6 <tfp_format+0x2d6>
|
|
|
+ 801145c: f89d 3030 ldrb.w r3, [sp, #48] ; 0x30
|
|
|
+ 8011460: b12b cbz r3, 801146e <tfp_format+0x2d6>
|
|
|
sign = 2;
|
|
|
p.width--;
|
|
|
- 80114ea: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
- 80114ec: 3b01 subs r3, #1
|
|
|
- 80114ee: 930b str r3, [sp, #44] ; 0x2c
|
|
|
+ 8011462: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
+ 8011464: 3b01 subs r3, #1
|
|
|
+ 8011466: 930b str r3, [sp, #44] ; 0x2c
|
|
|
sign = 1;
|
|
|
p.width--;
|
|
|
fval = - fval;
|
|
|
}
|
|
|
else if (p.sign) {
|
|
|
sign = 2;
|
|
|
- 80114f0: f04f 0b02 mov.w fp, #2
|
|
|
- 80114f4: e000 b.n 80114f8 <tfp_format+0x2d8>
|
|
|
+ 8011468: f04f 0b02 mov.w fp, #2
|
|
|
+ 801146c: e000 b.n 8011470 <tfp_format+0x2d8>
|
|
|
putf(putp, ch);
|
|
|
break;
|
|
|
case 'f':
|
|
|
case 'F':
|
|
|
fval = va_arg(va, double);
|
|
|
sign = 0;
|
|
|
- 80114f6: 469b mov fp, r3
|
|
|
+ 801146e: 469b mov fp, r3
|
|
|
else if (p.sign) {
|
|
|
sign = 2;
|
|
|
p.width--;
|
|
|
}
|
|
|
|
|
|
fpart = (int)fval;
|
|
|
- 80114f8: 4651 mov r1, sl
|
|
|
- 80114fa: 9800 ldr r0, [sp, #0]
|
|
|
- 80114fc: f7f7 fa36 bl 800896c <__aeabi_d2iz>
|
|
|
+ 8011470: 4651 mov r1, sl
|
|
|
+ 8011472: 9800 ldr r0, [sp, #0]
|
|
|
+ 8011474: f7f7 fa7a bl 800896c <__aeabi_d2iz>
|
|
|
|
|
|
fiter = 0;
|
|
|
- 8011500: 2200 movs r2, #0
|
|
|
+ 8011478: 2200 movs r2, #0
|
|
|
else if (p.sign) {
|
|
|
sign = 2;
|
|
|
p.width--;
|
|
|
}
|
|
|
|
|
|
fpart = (int)fval;
|
|
|
- 8011502: 9001 str r0, [sp, #4]
|
|
|
- 8011504: 4680 mov r8, r0
|
|
|
+ 801147a: 9001 str r0, [sp, #4]
|
|
|
+ 801147c: 4680 mov r8, r0
|
|
|
|
|
|
fiter = 0;
|
|
|
while (fpart != 0)
|
|
|
{
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
- 8011506: 210a movs r1, #10
|
|
|
+ 801147e: 210a movs r1, #10
|
|
|
}
|
|
|
|
|
|
fpart = (int)fval;
|
|
|
|
|
|
fiter = 0;
|
|
|
while (fpart != 0)
|
|
|
- 8011508: e008 b.n 801151c <tfp_format+0x2fc>
|
|
|
+ 8011480: e008 b.n 8011494 <tfp_format+0x2fc>
|
|
|
{
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
- 801150a: fb98 f0f1 sdiv r0, r8, r1
|
|
|
- 801150e: ab10 add r3, sp, #64 ; 0x40
|
|
|
- 8011510: fb01 8810 mls r8, r1, r0, r8
|
|
|
- 8011514: f843 8022 str.w r8, [r3, r2, lsl #2]
|
|
|
- 8011518: 3201 adds r2, #1
|
|
|
+ 8011482: fb98 f0f1 sdiv r0, r8, r1
|
|
|
+ 8011486: ab10 add r3, sp, #64 ; 0x40
|
|
|
+ 8011488: fb01 8810 mls r8, r1, r0, r8
|
|
|
+ 801148c: f843 8022 str.w r8, [r3, r2, lsl #2]
|
|
|
+ 8011490: 3201 adds r2, #1
|
|
|
fpart = fpart / 10;
|
|
|
- 801151a: 4680 mov r8, r0
|
|
|
+ 8011492: 4680 mov r8, r0
|
|
|
}
|
|
|
|
|
|
fpart = (int)fval;
|
|
|
|
|
|
fiter = 0;
|
|
|
while (fpart != 0)
|
|
|
- 801151c: f1b8 0f00 cmp.w r8, #0
|
|
|
- 8011520: d1f3 bne.n 801150a <tfp_format+0x2ea>
|
|
|
+ 8011494: f1b8 0f00 cmp.w r8, #0
|
|
|
+ 8011498: d1f3 bne.n 8011482 <tfp_format+0x2ea>
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
fpart = fpart / 10;
|
|
|
|
|
|
}
|
|
|
fiter--;
|
|
|
if (fiter == -1)
|
|
|
- 8011522: f102 39ff add.w r9, r2, #4294967295
|
|
|
- 8011526: b912 cbnz r2, 801152e <tfp_format+0x30e>
|
|
|
+ 801149a: f102 39ff add.w r9, r2, #4294967295
|
|
|
+ 801149e: b912 cbnz r2, 80114a6 <tfp_format+0x30e>
|
|
|
p.width--;
|
|
|
- 8011528: 9a0b ldr r2, [sp, #44] ; 0x2c
|
|
|
- 801152a: 3a01 subs r2, #1
|
|
|
- 801152c: 920b str r2, [sp, #44] ; 0x2c
|
|
|
+ 80114a0: 9a0b ldr r2, [sp, #44] ; 0x2c
|
|
|
+ 80114a2: 3a01 subs r2, #1
|
|
|
+ 80114a4: 920b str r2, [sp, #44] ; 0x2c
|
|
|
/* Leading zeros */
|
|
|
if (p.lz) {
|
|
|
- 801152e: f89d 2028 ldrb.w r2, [sp, #40] ; 0x28
|
|
|
- 8011532: 07d0 lsls r0, r2, #31
|
|
|
- 8011534: d51b bpl.n 801156e <tfp_format+0x34e>
|
|
|
+ 80114a6: f89d 2028 ldrb.w r2, [sp, #40] ; 0x28
|
|
|
+ 80114aa: 07d0 lsls r0, r2, #31
|
|
|
+ 80114ac: d51b bpl.n 80114e6 <tfp_format+0x34e>
|
|
|
|
|
|
if (sign == 1)
|
|
|
- 8011536: f1bb 0f01 cmp.w fp, #1
|
|
|
- 801153a: d102 bne.n 8011542 <tfp_format+0x322>
|
|
|
+ 80114ae: f1bb 0f01 cmp.w fp, #1
|
|
|
+ 80114b2: d102 bne.n 80114ba <tfp_format+0x322>
|
|
|
putf(putp, '-');
|
|
|
- 801153c: 4628 mov r0, r5
|
|
|
- 801153e: 212d movs r1, #45 ; 0x2d
|
|
|
- 8011540: e007 b.n 8011552 <tfp_format+0x332>
|
|
|
+ 80114b4: 4628 mov r0, r5
|
|
|
+ 80114b6: 212d movs r1, #45 ; 0x2d
|
|
|
+ 80114b8: e007 b.n 80114ca <tfp_format+0x332>
|
|
|
else if (sign == 2)
|
|
|
- 8011542: f1bb 0f02 cmp.w fp, #2
|
|
|
- 8011546: d105 bne.n 8011554 <tfp_format+0x334>
|
|
|
+ 80114ba: f1bb 0f02 cmp.w fp, #2
|
|
|
+ 80114be: d105 bne.n 80114cc <tfp_format+0x334>
|
|
|
putf(putp, '+');
|
|
|
- 8011548: 4628 mov r0, r5
|
|
|
- 801154a: 212b movs r1, #43 ; 0x2b
|
|
|
- 801154c: e001 b.n 8011552 <tfp_format+0x332>
|
|
|
+ 80114c0: 4628 mov r0, r5
|
|
|
+ 80114c2: 212b movs r1, #43 ; 0x2b
|
|
|
+ 80114c4: e001 b.n 80114ca <tfp_format+0x332>
|
|
|
|
|
|
while (p.width-- > p.prec + fiter + 2)
|
|
|
{
|
|
|
putf(putp, '0');
|
|
|
- 801154e: 4628 mov r0, r5
|
|
|
- 8011550: 2130 movs r1, #48 ; 0x30
|
|
|
- 8011552: 47b0 blx r6
|
|
|
+ 80114c6: 4628 mov r0, r5
|
|
|
+ 80114c8: 2130 movs r1, #48 ; 0x30
|
|
|
+ 80114ca: 47b0 blx r6
|
|
|
if (sign == 1)
|
|
|
putf(putp, '-');
|
|
|
else if (sign == 2)
|
|
|
putf(putp, '+');
|
|
|
|
|
|
while (p.width-- > p.prec + fiter + 2)
|
|
|
- 8011554: f89d 203c ldrb.w r2, [sp, #60] ; 0x3c
|
|
|
- 8011558: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
- 801155a: 444a add r2, r9
|
|
|
- 801155c: 3202 adds r2, #2
|
|
|
- 801155e: 1e59 subs r1, r3, #1
|
|
|
- 8011560: 4293 cmp r3, r2
|
|
|
- 8011562: 910b str r1, [sp, #44] ; 0x2c
|
|
|
- 8011564: dcf3 bgt.n 801154e <tfp_format+0x32e>
|
|
|
- 8011566: e017 b.n 8011598 <tfp_format+0x378>
|
|
|
+ 80114cc: f89d 203c ldrb.w r2, [sp, #60] ; 0x3c
|
|
|
+ 80114d0: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
|
+ 80114d2: 444a add r2, r9
|
|
|
+ 80114d4: 3202 adds r2, #2
|
|
|
+ 80114d6: 1e59 subs r1, r3, #1
|
|
|
+ 80114d8: 4293 cmp r3, r2
|
|
|
+ 80114da: 910b str r1, [sp, #44] ; 0x2c
|
|
|
+ 80114dc: dcf3 bgt.n 80114c6 <tfp_format+0x32e>
|
|
|
+ 80114de: e017 b.n 8011510 <tfp_format+0x378>
|
|
|
else
|
|
|
{
|
|
|
|
|
|
while (p.width-- > p.prec + fiter + 2)
|
|
|
{
|
|
|
putf(putp, ' ');
|
|
|
- 8011568: 4628 mov r0, r5
|
|
|
- 801156a: 2120 movs r1, #32
|
|
|
- 801156c: 47b0 blx r6
|
|
|
+ 80114e0: 4628 mov r0, r5
|
|
|
+ 80114e2: 2120 movs r1, #32
|
|
|
+ 80114e4: 47b0 blx r6
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
|
|
|
while (p.width-- > p.prec + fiter + 2)
|
|
|
- 801156e: f89d 103c ldrb.w r1, [sp, #60] ; 0x3c
|
|
|
- 8011572: 9a0b ldr r2, [sp, #44] ; 0x2c
|
|
|
- 8011574: 4449 add r1, r9
|
|
|
- 8011576: 3102 adds r1, #2
|
|
|
- 8011578: 1e50 subs r0, r2, #1
|
|
|
- 801157a: 428a cmp r2, r1
|
|
|
- 801157c: 900b str r0, [sp, #44] ; 0x2c
|
|
|
- 801157e: dcf3 bgt.n 8011568 <tfp_format+0x348>
|
|
|
+ 80114e6: f89d 103c ldrb.w r1, [sp, #60] ; 0x3c
|
|
|
+ 80114ea: 9a0b ldr r2, [sp, #44] ; 0x2c
|
|
|
+ 80114ec: 4449 add r1, r9
|
|
|
+ 80114ee: 3102 adds r1, #2
|
|
|
+ 80114f0: 1e50 subs r0, r2, #1
|
|
|
+ 80114f2: 428a cmp r2, r1
|
|
|
+ 80114f4: 900b str r0, [sp, #44] ; 0x2c
|
|
|
+ 80114f6: dcf3 bgt.n 80114e0 <tfp_format+0x348>
|
|
|
{
|
|
|
putf(putp, ' ');
|
|
|
}
|
|
|
|
|
|
if (sign == 1)
|
|
|
- 8011580: f1bb 0f01 cmp.w fp, #1
|
|
|
- 8011584: d102 bne.n 801158c <tfp_format+0x36c>
|
|
|
+ 80114f8: f1bb 0f01 cmp.w fp, #1
|
|
|
+ 80114fc: d102 bne.n 8011504 <tfp_format+0x36c>
|
|
|
putf(putp, '-');
|
|
|
- 8011586: 4628 mov r0, r5
|
|
|
- 8011588: 212d movs r1, #45 ; 0x2d
|
|
|
- 801158a: e004 b.n 8011596 <tfp_format+0x376>
|
|
|
+ 80114fe: 4628 mov r0, r5
|
|
|
+ 8011500: 212d movs r1, #45 ; 0x2d
|
|
|
+ 8011502: e004 b.n 801150e <tfp_format+0x376>
|
|
|
else if (sign == 2)
|
|
|
- 801158c: f1bb 0f02 cmp.w fp, #2
|
|
|
- 8011590: d102 bne.n 8011598 <tfp_format+0x378>
|
|
|
+ 8011504: f1bb 0f02 cmp.w fp, #2
|
|
|
+ 8011508: d102 bne.n 8011510 <tfp_format+0x378>
|
|
|
putf(putp, '+');
|
|
|
- 8011592: 4628 mov r0, r5
|
|
|
- 8011594: 212b movs r1, #43 ; 0x2b
|
|
|
- 8011596: 47b0 blx r6
|
|
|
+ 801150a: 4628 mov r0, r5
|
|
|
+ 801150c: 212b movs r1, #43 ; 0x2b
|
|
|
+ 801150e: 47b0 blx r6
|
|
|
|
|
|
}
|
|
|
|
|
|
if (fiter == -1)
|
|
|
- 8011598: f1b9 3fff cmp.w r9, #4294967295
|
|
|
- 801159c: d102 bne.n 80115a4 <tfp_format+0x384>
|
|
|
+ 8011510: f1b9 3fff cmp.w r9, #4294967295
|
|
|
+ 8011514: d102 bne.n 801151c <tfp_format+0x384>
|
|
|
putf(putp, '0');
|
|
|
- 801159e: 4628 mov r0, r5
|
|
|
- 80115a0: 2130 movs r1, #48 ; 0x30
|
|
|
- 80115a2: e007 b.n 80115b4 <tfp_format+0x394>
|
|
|
+ 8011516: 4628 mov r0, r5
|
|
|
+ 8011518: 2130 movs r1, #48 ; 0x30
|
|
|
+ 801151a: e007 b.n 801152c <tfp_format+0x394>
|
|
|
while (fiter > -1)
|
|
|
{
|
|
|
putf(putp, '0' + (temp_buffer[fiter--]));
|
|
|
- 80115a4: ab10 add r3, sp, #64 ; 0x40
|
|
|
- 80115a6: 4628 mov r0, r5
|
|
|
- 80115a8: f853 1029 ldr.w r1, [r3, r9, lsl #2]
|
|
|
- 80115ac: 3130 adds r1, #48 ; 0x30
|
|
|
- 80115ae: f109 39ff add.w r9, r9, #4294967295
|
|
|
- 80115b2: b2c9 uxtb r1, r1
|
|
|
- 80115b4: 47b0 blx r6
|
|
|
+ 801151c: ab10 add r3, sp, #64 ; 0x40
|
|
|
+ 801151e: 4628 mov r0, r5
|
|
|
+ 8011520: f853 1029 ldr.w r1, [r3, r9, lsl #2]
|
|
|
+ 8011524: 3130 adds r1, #48 ; 0x30
|
|
|
+ 8011526: f109 39ff add.w r9, r9, #4294967295
|
|
|
+ 801152a: b2c9 uxtb r1, r1
|
|
|
+ 801152c: 47b0 blx r6
|
|
|
|
|
|
}
|
|
|
|
|
|
if (fiter == -1)
|
|
|
putf(putp, '0');
|
|
|
while (fiter > -1)
|
|
|
- 80115b6: f1b9 3fff cmp.w r9, #4294967295
|
|
|
- 80115ba: d1f3 bne.n 80115a4 <tfp_format+0x384>
|
|
|
+ 801152e: f1b9 3fff cmp.w r9, #4294967295
|
|
|
+ 8011532: d1f3 bne.n 801151c <tfp_format+0x384>
|
|
|
{
|
|
|
putf(putp, '0' + (temp_buffer[fiter--]));
|
|
|
}
|
|
|
|
|
|
putf(putp, '.');
|
|
|
- 80115bc: 4628 mov r0, r5
|
|
|
- 80115be: 212e movs r1, #46 ; 0x2e
|
|
|
- 80115c0: 47b0 blx r6
|
|
|
+ 8011534: 4628 mov r0, r5
|
|
|
+ 8011536: 212e movs r1, #46 ; 0x2e
|
|
|
+ 8011538: 47b0 blx r6
|
|
|
ffactor = 1;
|
|
|
- 80115c2: f04f 0901 mov.w r9, #1
|
|
|
+ 801153a: f04f 0901 mov.w r9, #1
|
|
|
while (p.prec-- > 0)
|
|
|
- 80115c6: e01d b.n 8011604 <tfp_format+0x3e4>
|
|
|
+ 801153e: e01d b.n 801157c <tfp_format+0x3e4>
|
|
|
{
|
|
|
ffactor *= 10;
|
|
|
- 80115c8: 230a movs r3, #10
|
|
|
+ 8011540: 230a movs r3, #10
|
|
|
fpart = (int)((fval - (int)fval)*ffactor);
|
|
|
- 80115ca: 9801 ldr r0, [sp, #4]
|
|
|
+ 8011542: 9801 ldr r0, [sp, #4]
|
|
|
|
|
|
putf(putp, '.');
|
|
|
ffactor = 1;
|
|
|
while (p.prec-- > 0)
|
|
|
{
|
|
|
ffactor *= 10;
|
|
|
- 80115cc: fb03 f909 mul.w r9, r3, r9
|
|
|
+ 8011544: fb03 f909 mul.w r9, r3, r9
|
|
|
fpart = (int)((fval - (int)fval)*ffactor);
|
|
|
- 80115d0: f7f6 fecc bl 800836c <__aeabi_i2d>
|
|
|
- 80115d4: 4602 mov r2, r0
|
|
|
- 80115d6: 460b mov r3, r1
|
|
|
- 80115d8: 9800 ldr r0, [sp, #0]
|
|
|
- 80115da: 4651 mov r1, sl
|
|
|
- 80115dc: f7f6 fd78 bl 80080d0 <__aeabi_dsub>
|
|
|
- 80115e0: e9cd 0102 strd r0, r1, [sp, #8]
|
|
|
- 80115e4: 4648 mov r0, r9
|
|
|
- 80115e6: f7f6 fec1 bl 800836c <__aeabi_i2d>
|
|
|
- 80115ea: 4602 mov r2, r0
|
|
|
- 80115ec: 460b mov r3, r1
|
|
|
- 80115ee: e9dd 0102 ldrd r0, r1, [sp, #8]
|
|
|
- 80115f2: f7f6 ff21 bl 8008438 <__aeabi_dmul>
|
|
|
- 80115f6: f7f7 f9b9 bl 800896c <__aeabi_d2iz>
|
|
|
+ 8011548: f7f6 ff10 bl 800836c <__aeabi_i2d>
|
|
|
+ 801154c: 4602 mov r2, r0
|
|
|
+ 801154e: 460b mov r3, r1
|
|
|
+ 8011550: 9800 ldr r0, [sp, #0]
|
|
|
+ 8011552: 4651 mov r1, sl
|
|
|
+ 8011554: f7f6 fdbc bl 80080d0 <__aeabi_dsub>
|
|
|
+ 8011558: e9cd 0102 strd r0, r1, [sp, #8]
|
|
|
+ 801155c: 4648 mov r0, r9
|
|
|
+ 801155e: f7f6 ff05 bl 800836c <__aeabi_i2d>
|
|
|
+ 8011562: 4602 mov r2, r0
|
|
|
+ 8011564: 460b mov r3, r1
|
|
|
+ 8011566: e9dd 0102 ldrd r0, r1, [sp, #8]
|
|
|
+ 801156a: f7f6 ff65 bl 8008438 <__aeabi_dmul>
|
|
|
+ 801156e: f7f7 f9fd bl 800896c <__aeabi_d2iz>
|
|
|
if (fpart == 0)
|
|
|
- 80115fa: 4680 mov r8, r0
|
|
|
- 80115fc: b910 cbnz r0, 8011604 <tfp_format+0x3e4>
|
|
|
+ 8011572: 4680 mov r8, r0
|
|
|
+ 8011574: b910 cbnz r0, 801157c <tfp_format+0x3e4>
|
|
|
putf(putp, '0');
|
|
|
- 80115fe: 4628 mov r0, r5
|
|
|
- 8011600: 2130 movs r1, #48 ; 0x30
|
|
|
- 8011602: 47b0 blx r6
|
|
|
+ 8011576: 4628 mov r0, r5
|
|
|
+ 8011578: 2130 movs r1, #48 ; 0x30
|
|
|
+ 801157a: 47b0 blx r6
|
|
|
putf(putp, '0' + (temp_buffer[fiter--]));
|
|
|
}
|
|
|
|
|
|
putf(putp, '.');
|
|
|
ffactor = 1;
|
|
|
while (p.prec-- > 0)
|
|
|
- 8011604: f89d 303c ldrb.w r3, [sp, #60] ; 0x3c
|
|
|
- 8011608: 1e5a subs r2, r3, #1
|
|
|
- 801160a: f88d 203c strb.w r2, [sp, #60] ; 0x3c
|
|
|
- 801160e: 2b00 cmp r3, #0
|
|
|
- 8011610: d1da bne.n 80115c8 <tfp_format+0x3a8>
|
|
|
+ 801157c: f89d 303c ldrb.w r3, [sp, #60] ; 0x3c
|
|
|
+ 8011580: 1e5a subs r2, r3, #1
|
|
|
+ 8011582: f88d 203c strb.w r2, [sp, #60] ; 0x3c
|
|
|
+ 8011586: 2b00 cmp r3, #0
|
|
|
+ 8011588: d1da bne.n 8011540 <tfp_format+0x3a8>
|
|
|
putf(putp, '0');
|
|
|
}
|
|
|
fiter = 0;
|
|
|
while (fpart != 0)
|
|
|
{
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
- 8011612: 220a movs r2, #10
|
|
|
- 8011614: e008 b.n 8011628 <tfp_format+0x408>
|
|
|
- 8011616: fb98 f1f2 sdiv r1, r8, r2
|
|
|
- 801161a: a810 add r0, sp, #64 ; 0x40
|
|
|
- 801161c: fb02 8811 mls r8, r2, r1, r8
|
|
|
- 8011620: f840 8023 str.w r8, [r0, r3, lsl #2]
|
|
|
- 8011624: 3301 adds r3, #1
|
|
|
+ 801158a: 220a movs r2, #10
|
|
|
+ 801158c: e008 b.n 80115a0 <tfp_format+0x408>
|
|
|
+ 801158e: fb98 f1f2 sdiv r1, r8, r2
|
|
|
+ 8011592: a810 add r0, sp, #64 ; 0x40
|
|
|
+ 8011594: fb02 8811 mls r8, r2, r1, r8
|
|
|
+ 8011598: f840 8023 str.w r8, [r0, r3, lsl #2]
|
|
|
+ 801159c: 3301 adds r3, #1
|
|
|
fpart = fpart / 10;
|
|
|
- 8011626: 4688 mov r8, r1
|
|
|
+ 801159e: 4688 mov r8, r1
|
|
|
fpart = (int)((fval - (int)fval)*ffactor);
|
|
|
if (fpart == 0)
|
|
|
putf(putp, '0');
|
|
|
}
|
|
|
fiter = 0;
|
|
|
while (fpart != 0)
|
|
|
- 8011628: f1b8 0f00 cmp.w r8, #0
|
|
|
- 801162c: d1f3 bne.n 8011616 <tfp_format+0x3f6>
|
|
|
- 801162e: 4698 mov r8, r3
|
|
|
+ 80115a0: f1b8 0f00 cmp.w r8, #0
|
|
|
+ 80115a4: d1f3 bne.n 801158e <tfp_format+0x3f6>
|
|
|
+ 80115a6: 4698 mov r8, r3
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
fpart = fpart / 10;
|
|
|
|
|
|
}
|
|
|
fiter--;
|
|
|
while (fiter > -1)
|
|
|
- 8011630: e006 b.n 8011640 <tfp_format+0x420>
|
|
|
+ 80115a8: e006 b.n 80115b8 <tfp_format+0x420>
|
|
|
{
|
|
|
putf(putp, '0' + (temp_buffer[fiter--]));
|
|
|
- 8011632: ab10 add r3, sp, #64 ; 0x40
|
|
|
- 8011634: 4628 mov r0, r5
|
|
|
- 8011636: f853 1028 ldr.w r1, [r3, r8, lsl #2]
|
|
|
- 801163a: 3130 adds r1, #48 ; 0x30
|
|
|
- 801163c: b2c9 uxtb r1, r1
|
|
|
- 801163e: 47b0 blx r6
|
|
|
+ 80115aa: ab10 add r3, sp, #64 ; 0x40
|
|
|
+ 80115ac: 4628 mov r0, r5
|
|
|
+ 80115ae: f853 1028 ldr.w r1, [r3, r8, lsl #2]
|
|
|
+ 80115b2: 3130 adds r1, #48 ; 0x30
|
|
|
+ 80115b4: b2c9 uxtb r1, r1
|
|
|
+ 80115b6: 47b0 blx r6
|
|
|
temp_buffer[fiter++] = fpart % 10;
|
|
|
fpart = fpart / 10;
|
|
|
|
|
|
}
|
|
|
fiter--;
|
|
|
while (fiter > -1)
|
|
|
- 8011640: f118 38ff adds.w r8, r8, #4294967295
|
|
|
- 8011644: d2f5 bcs.n 8011632 <tfp_format+0x412>
|
|
|
+ 80115b8: f118 38ff adds.w r8, r8, #4294967295
|
|
|
+ 80115bc: d2f5 bcs.n 80115aa <tfp_format+0x412>
|
|
|
char bf[12]; /* int = 32b on some architectures */
|
|
|
#endif
|
|
|
char ch;
|
|
|
p.bf = bf;
|
|
|
|
|
|
while ((ch = *(fmt++))) {
|
|
|
- 8011646: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
- 801164a: 2900 cmp r1, #0
|
|
|
- 801164c: f47f adf2 bne.w 8011234 <tfp_format+0x14>
|
|
|
- 8011650: e003 b.n 801165a <tfp_format+0x43a>
|
|
|
+ 80115be: f817 1b01 ldrb.w r1, [r7], #1
|
|
|
+ 80115c2: 2900 cmp r1, #0
|
|
|
+ 80115c4: f47f adf2 bne.w 80111ac <tfp_format+0x14>
|
|
|
+ 80115c8: e003 b.n 80115d2 <tfp_format+0x43a>
|
|
|
{
|
|
|
const char *p = *src;
|
|
|
unsigned int num = 0;
|
|
|
int digit;
|
|
|
while ((digit = a2d(ch)) >= 0) {
|
|
|
if (digit > base)
|
|
|
- 8011652: 2b0a cmp r3, #10
|
|
|
- 8011654: f77f ae32 ble.w 80112bc <tfp_format+0x9c>
|
|
|
- 8011658: e64c b.n 80112f4 <tfp_format+0xd4>
|
|
|
+ 80115ca: 2b0a cmp r3, #10
|
|
|
+ 80115cc: f77f ae32 ble.w 8011234 <tfp_format+0x9c>
|
|
|
+ 80115d0: e64c b.n 801126c <tfp_format+0xd4>
|
|
|
break;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
abort:;
|
|
|
}
|
|
|
- 801165a: b01b add sp, #108 ; 0x6c
|
|
|
- 801165c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
+ 80115d2: b01b add sp, #108 ; 0x6c
|
|
|
+ 80115d4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
|
|
|
-08011660 <init_printf>:
|
|
|
+080115d8 <init_printf>:
|
|
|
static putcf stdout_putf;
|
|
|
static void *stdout_putp;
|
|
|
|
|
|
void init_printf(void *putp, putcf putf)
|
|
|
{
|
|
|
stdout_putf = putf;
|
|
|
- 8011660: 4b02 ldr r3, [pc, #8] ; (801166c <init_printf+0xc>)
|
|
|
- 8011662: 6019 str r1, [r3, #0]
|
|
|
+ 80115d8: 4b02 ldr r3, [pc, #8] ; (80115e4 <init_printf+0xc>)
|
|
|
+ 80115da: 6019 str r1, [r3, #0]
|
|
|
stdout_putp = putp;
|
|
|
- 8011664: 4b02 ldr r3, [pc, #8] ; (8011670 <init_printf+0x10>)
|
|
|
- 8011666: 6018 str r0, [r3, #0]
|
|
|
- 8011668: 4770 bx lr
|
|
|
- 801166a: bf00 nop
|
|
|
- 801166c: 20006dc8 .word 0x20006dc8
|
|
|
- 8011670: 20006dcc .word 0x20006dcc
|
|
|
-
|
|
|
-08011674 <tfp_printf>:
|
|
|
+ 80115dc: 4b02 ldr r3, [pc, #8] ; (80115e8 <init_printf+0x10>)
|
|
|
+ 80115de: 6018 str r0, [r3, #0]
|
|
|
+ 80115e0: 4770 bx lr
|
|
|
+ 80115e2: bf00 nop
|
|
|
+ 80115e4: 20006dc8 .word 0x20006dc8
|
|
|
+ 80115e8: 20006dcc .word 0x20006dcc
|
|
|
+
|
|
|
+080115ec <tfp_printf>:
|
|
|
}
|
|
|
|
|
|
void tfp_printf(char *fmt, ...)
|
|
|
{
|
|
|
- 8011674: b40f push {r0, r1, r2, r3}
|
|
|
- 8011676: b507 push {r0, r1, r2, lr}
|
|
|
+ 80115ec: b40f push {r0, r1, r2, r3}
|
|
|
+ 80115ee: b507 push {r0, r1, r2, lr}
|
|
|
va_list va;
|
|
|
va_start(va, fmt);
|
|
|
tfp_format(stdout_putp, stdout_putf, fmt, va);
|
|
|
- 8011678: 4906 ldr r1, [pc, #24] ; (8011694 <tfp_printf+0x20>)
|
|
|
+ 80115f0: 4906 ldr r1, [pc, #24] ; (801160c <tfp_printf+0x20>)
|
|
|
stdout_putf = putf;
|
|
|
stdout_putp = putp;
|
|
|
}
|
|
|
|
|
|
void tfp_printf(char *fmt, ...)
|
|
|
{
|
|
|
- 801167a: ab04 add r3, sp, #16
|
|
|
+ 80115f2: ab04 add r3, sp, #16
|
|
|
va_list va;
|
|
|
va_start(va, fmt);
|
|
|
tfp_format(stdout_putp, stdout_putf, fmt, va);
|
|
|
- 801167c: 6808 ldr r0, [r1, #0]
|
|
|
- 801167e: 4906 ldr r1, [pc, #24] ; (8011698 <tfp_printf+0x24>)
|
|
|
+ 80115f4: 6808 ldr r0, [r1, #0]
|
|
|
+ 80115f6: 4906 ldr r1, [pc, #24] ; (8011610 <tfp_printf+0x24>)
|
|
|
stdout_putf = putf;
|
|
|
stdout_putp = putp;
|
|
|
}
|
|
|
|
|
|
void tfp_printf(char *fmt, ...)
|
|
|
{
|
|
|
- 8011680: f853 2b04 ldr.w r2, [r3], #4
|
|
|
+ 80115f8: f853 2b04 ldr.w r2, [r3], #4
|
|
|
va_list va;
|
|
|
va_start(va, fmt);
|
|
|
tfp_format(stdout_putp, stdout_putf, fmt, va);
|
|
|
- 8011684: 6809 ldr r1, [r1, #0]
|
|
|
+ 80115fc: 6809 ldr r1, [r1, #0]
|
|
|
}
|
|
|
|
|
|
void tfp_printf(char *fmt, ...)
|
|
|
{
|
|
|
va_list va;
|
|
|
va_start(va, fmt);
|
|
|
- 8011686: 9301 str r3, [sp, #4]
|
|
|
+ 80115fe: 9301 str r3, [sp, #4]
|
|
|
tfp_format(stdout_putp, stdout_putf, fmt, va);
|
|
|
- 8011688: f7ff fdca bl 8011220 <tfp_format>
|
|
|
+ 8011600: f7ff fdca bl 8011198 <tfp_format>
|
|
|
va_end(va);
|
|
|
}
|
|
|
- 801168c: e8bd 400e ldmia.w sp!, {r1, r2, r3, lr}
|
|
|
- 8011690: b004 add sp, #16
|
|
|
- 8011692: 4770 bx lr
|
|
|
- 8011694: 20006dcc .word 0x20006dcc
|
|
|
- 8011698: 20006dc8 .word 0x20006dc8
|
|
|
+ 8011604: e8bd 400e ldmia.w sp!, {r1, r2, r3, lr}
|
|
|
+ 8011608: b004 add sp, #16
|
|
|
+ 801160a: 4770 bx lr
|
|
|
+ 801160c: 20006dcc .word 0x20006dcc
|
|
|
+ 8011610: 20006dc8 .word 0x20006dc8
|
|
|
|
|
|
-0801169c <tfp_vsprintf>:
|
|
|
+08011614 <tfp_vsprintf>:
|
|
|
struct _vsprintf_putcf_data *data = (struct _vsprintf_putcf_data*)p;
|
|
|
data->dest[data->num_chars++] = c;
|
|
|
}
|
|
|
|
|
|
int tfp_vsprintf(char *str, const char *format, va_list ap)
|
|
|
{
|
|
|
- 801169c: b537 push {r0, r1, r2, r4, r5, lr}
|
|
|
- 801169e: 460d mov r5, r1
|
|
|
- 80116a0: 4613 mov r3, r2
|
|
|
+ 8011614: b537 push {r0, r1, r2, r4, r5, lr}
|
|
|
+ 8011616: 460d mov r5, r1
|
|
|
+ 8011618: 4613 mov r3, r2
|
|
|
struct _vsprintf_putcf_data data;
|
|
|
data.dest = str;
|
|
|
- 80116a2: 9000 str r0, [sp, #0]
|
|
|
+ 801161a: 9000 str r0, [sp, #0]
|
|
|
data.num_chars = 0;
|
|
|
- 80116a4: 2400 movs r4, #0
|
|
|
+ 801161c: 2400 movs r4, #0
|
|
|
tfp_format(&data, _vsprintf_putcf, format, ap);
|
|
|
- 80116a6: 4668 mov r0, sp
|
|
|
- 80116a8: 462a mov r2, r5
|
|
|
- 80116aa: 4904 ldr r1, [pc, #16] ; (80116bc <tfp_vsprintf+0x20>)
|
|
|
+ 801161e: 4668 mov r0, sp
|
|
|
+ 8011620: 462a mov r2, r5
|
|
|
+ 8011622: 4904 ldr r1, [pc, #16] ; (8011634 <tfp_vsprintf+0x20>)
|
|
|
|
|
|
int tfp_vsprintf(char *str, const char *format, va_list ap)
|
|
|
{
|
|
|
struct _vsprintf_putcf_data data;
|
|
|
data.dest = str;
|
|
|
data.num_chars = 0;
|
|
|
- 80116ac: 9401 str r4, [sp, #4]
|
|
|
+ 8011624: 9401 str r4, [sp, #4]
|
|
|
tfp_format(&data, _vsprintf_putcf, format, ap);
|
|
|
- 80116ae: f7ff fdb7 bl 8011220 <tfp_format>
|
|
|
+ 8011626: f7ff fdb7 bl 8011198 <tfp_format>
|
|
|
data.dest[data.num_chars] = '\0';
|
|
|
- 80116b2: e89d 000c ldmia.w sp, {r2, r3}
|
|
|
- 80116b6: 54d4 strb r4, [r2, r3]
|
|
|
+ 801162a: e89d 000c ldmia.w sp, {r2, r3}
|
|
|
+ 801162e: 54d4 strb r4, [r2, r3]
|
|
|
return data.num_chars;
|
|
|
}
|
|
|
- 80116b8: 9801 ldr r0, [sp, #4]
|
|
|
- 80116ba: bd3e pop {r1, r2, r3, r4, r5, pc}
|
|
|
- 80116bc: 08011215 .word 0x08011215
|
|
|
+ 8011630: 9801 ldr r0, [sp, #4]
|
|
|
+ 8011632: bd3e pop {r1, r2, r3, r4, r5, pc}
|
|
|
+ 8011634: 0801118d .word 0x0801118d
|
|
|
|
|
|
-080116c0 <tfp_sprintf>:
|
|
|
+08011638 <tfp_sprintf>:
|
|
|
|
|
|
int tfp_sprintf(char *str, const char *format, ...)
|
|
|
{
|
|
|
- 80116c0: b40e push {r1, r2, r3}
|
|
|
- 80116c2: b503 push {r0, r1, lr}
|
|
|
- 80116c4: aa03 add r2, sp, #12
|
|
|
- 80116c6: f852 1b04 ldr.w r1, [r2], #4
|
|
|
+ 8011638: b40e push {r1, r2, r3}
|
|
|
+ 801163a: b503 push {r0, r1, lr}
|
|
|
+ 801163c: aa03 add r2, sp, #12
|
|
|
+ 801163e: f852 1b04 ldr.w r1, [r2], #4
|
|
|
va_list ap;
|
|
|
int retval;
|
|
|
|
|
|
va_start(ap, format);
|
|
|
- 80116ca: 9201 str r2, [sp, #4]
|
|
|
+ 8011642: 9201 str r2, [sp, #4]
|
|
|
retval = tfp_vsprintf(str, format, ap);
|
|
|
- 80116cc: f7ff ffe6 bl 801169c <tfp_vsprintf>
|
|
|
+ 8011644: f7ff ffe6 bl 8011614 <tfp_vsprintf>
|
|
|
va_end(ap);
|
|
|
return retval;
|
|
|
}
|
|
|
- 80116d0: e8bd 400c ldmia.w sp!, {r2, r3, lr}
|
|
|
- 80116d4: b003 add sp, #12
|
|
|
- 80116d6: 4770 bx lr
|
|
|
+ 8011648: e8bd 400c ldmia.w sp!, {r2, r3, lr}
|
|
|
+ 801164c: b003 add sp, #12
|
|
|
+ 801164e: 4770 bx lr
|
|
|
|
|
|
-080116d8 <Reset_Handler>:
|
|
|
+08011650 <Reset_Handler>:
|
|
|
.weak Reset_Handler
|
|
|
.type Reset_Handler, %function
|
|
|
Reset_Handler:
|
|
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
|
movs r1, #0
|
|
|
- 80116d8: 2100 movs r1, #0
|
|
|
+ 8011650: 2100 movs r1, #0
|
|
|
b LoopCopyDataInit
|
|
|
- 80116da: f000 b804 b.w 80116e6 <LoopCopyDataInit>
|
|
|
+ 8011652: f000 b804 b.w 801165e <LoopCopyDataInit>
|
|
|
|
|
|
-080116de <CopyDataInit>:
|
|
|
+08011656 <CopyDataInit>:
|
|
|
|
|
|
CopyDataInit:
|
|
|
ldr r3, =_sidata
|
|
|
- 80116de: 4b0d ldr r3, [pc, #52] ; (8011714 <LoopFillZerobss+0x16>)
|
|
|
+ 8011656: 4b0d ldr r3, [pc, #52] ; (801168c <LoopFillZerobss+0x16>)
|
|
|
ldr r3, [r3, r1]
|
|
|
- 80116e0: 585b ldr r3, [r3, r1]
|
|
|
+ 8011658: 585b ldr r3, [r3, r1]
|
|
|
str r3, [r0, r1]
|
|
|
- 80116e2: 5043 str r3, [r0, r1]
|
|
|
+ 801165a: 5043 str r3, [r0, r1]
|
|
|
adds r1, r1, #4
|
|
|
- 80116e4: 3104 adds r1, #4
|
|
|
+ 801165c: 3104 adds r1, #4
|
|
|
|
|
|
-080116e6 <LoopCopyDataInit>:
|
|
|
+0801165e <LoopCopyDataInit>:
|
|
|
|
|
|
LoopCopyDataInit:
|
|
|
ldr r0, =_sdata
|
|
|
- 80116e6: 480c ldr r0, [pc, #48] ; (8011718 <LoopFillZerobss+0x1a>)
|
|
|
+ 801165e: 480c ldr r0, [pc, #48] ; (8011690 <LoopFillZerobss+0x1a>)
|
|
|
ldr r3, =_edata
|
|
|
- 80116e8: 4b0c ldr r3, [pc, #48] ; (801171c <LoopFillZerobss+0x1e>)
|
|
|
+ 8011660: 4b0c ldr r3, [pc, #48] ; (8011694 <LoopFillZerobss+0x1e>)
|
|
|
adds r2, r0, r1
|
|
|
- 80116ea: 1842 adds r2, r0, r1
|
|
|
+ 8011662: 1842 adds r2, r0, r1
|
|
|
cmp r2, r3
|
|
|
- 80116ec: 429a cmp r2, r3
|
|
|
+ 8011664: 429a cmp r2, r3
|
|
|
bcc CopyDataInit
|
|
|
- 80116ee: f4ff aff6 bcc.w 80116de <CopyDataInit>
|
|
|
+ 8011666: f4ff aff6 bcc.w 8011656 <CopyDataInit>
|
|
|
ldr r2, =_sbss
|
|
|
- 80116f2: 4a0b ldr r2, [pc, #44] ; (8011720 <LoopFillZerobss+0x22>)
|
|
|
+ 801166a: 4a0b ldr r2, [pc, #44] ; (8011698 <LoopFillZerobss+0x22>)
|
|
|
b LoopFillZerobss
|
|
|
- 80116f4: f000 b803 b.w 80116fe <LoopFillZerobss>
|
|
|
+ 801166c: f000 b803 b.w 8011676 <LoopFillZerobss>
|
|
|
|
|
|
-080116f8 <FillZerobss>:
|
|
|
+08011670 <FillZerobss>:
|
|
|
/* Zero fill the bss segment. */
|
|
|
FillZerobss:
|
|
|
movs r3, #0
|
|
|
- 80116f8: 2300 movs r3, #0
|
|
|
+ 8011670: 2300 movs r3, #0
|
|
|
str r3, [r2], #4
|
|
|
- 80116fa: f842 3b04 str.w r3, [r2], #4
|
|
|
+ 8011672: f842 3b04 str.w r3, [r2], #4
|
|
|
|
|
|
-080116fe <LoopFillZerobss>:
|
|
|
+08011676 <LoopFillZerobss>:
|
|
|
|
|
|
LoopFillZerobss:
|
|
|
ldr r3, = _ebss
|
|
|
- 80116fe: 4b09 ldr r3, [pc, #36] ; (8011724 <LoopFillZerobss+0x26>)
|
|
|
+ 8011676: 4b09 ldr r3, [pc, #36] ; (801169c <LoopFillZerobss+0x26>)
|
|
|
cmp r2, r3
|
|
|
- 8011700: 429a cmp r2, r3
|
|
|
+ 8011678: 429a cmp r2, r3
|
|
|
bcc FillZerobss
|
|
|
- 8011702: f4ff aff9 bcc.w 80116f8 <FillZerobss>
|
|
|
+ 801167a: f4ff aff9 bcc.w 8011670 <FillZerobss>
|
|
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
|
bl SystemInit
|
|
|
- 8011706: f7f8 fa21 bl 8009b4c <SystemInit>
|
|
|
+ 801167e: f7f8 fa65 bl 8009b4c <SystemInit>
|
|
|
/* Call static constructors */
|
|
|
bl __libc_init_array
|
|
|
- 801170a: f7f7 fe1d bl 8009348 <__libc_init_array>
|
|
|
+ 8011682: f7f7 fe61 bl 8009348 <__libc_init_array>
|
|
|
/* Call the application's entry point.*/
|
|
|
bl main
|
|
|
- 801170e: f7ff fb45 bl 8010d9c <main>
|
|
|
+ 8011686: f7ff fb45 bl 8010d14 <main>
|
|
|
bx lr
|
|
|
- 8011712: 4770 bx lr
|
|
|
+ 801168a: 4770 bx lr
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
|
movs r1, #0
|
|
|
b LoopCopyDataInit
|
|
|
|
|
|
CopyDataInit:
|
|
|
ldr r3, =_sidata
|
|
|
- 8011714: 08013698 .word 0x08013698
|
|
|
+ 801168c: 080135f8 .word 0x080135f8
|
|
|
ldr r3, [r3, r1]
|
|
|
str r3, [r0, r1]
|
|
|
adds r1, r1, #4
|
|
|
|
|
|
LoopCopyDataInit:
|
|
|
ldr r0, =_sdata
|
|
|
- 8011718: 20000000 .word 0x20000000
|
|
|
+ 8011690: 20000000 .word 0x20000000
|
|
|
ldr r3, =_edata
|
|
|
- 801171c: 20000118 .word 0x20000118
|
|
|
+ 8011694: 20000118 .word 0x20000118
|
|
|
adds r2, r0, r1
|
|
|
cmp r2, r3
|
|
|
bcc CopyDataInit
|
|
|
ldr r2, =_sbss
|
|
|
- 8011720: 20000118 .word 0x20000118
|
|
|
+ 8011698: 20000118 .word 0x20000118
|
|
|
FillZerobss:
|
|
|
movs r3, #0
|
|
|
str r3, [r2], #4
|
|
|
|
|
|
LoopFillZerobss:
|
|
|
ldr r3, = _ebss
|
|
|
- 8011724: 2000c99c .word 0x2000c99c
|
|
|
+ 801169c: 2000c7d8 .word 0x2000c7d8
|
|
|
|
|
|
-08011728 <ADC_IRQHandler>:
|
|
|
+080116a0 <ADC_IRQHandler>:
|
|
|
* @retval None
|
|
|
*/
|
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
|
Default_Handler:
|
|
|
Infinite_Loop:
|
|
|
b Infinite_Loop
|
|
|
- 8011728: f7ff bffe b.w 8011728 <ADC_IRQHandler>
|
|
|
-
|
|
|
-0801172c <_ctype_>:
|
|
|
- 801172c: 2000 2020 2020 2020 2020 2828 2828 2028 . (((((
|
|
|
- 801173c: 2020 2020 2020 2020 2020 2020 2020 2020
|
|
|
- 801174c: 8820 1010 1010 1010 1010 1010 1010 1010 ...............
|
|
|
- 801175c: 0410 0404 0404 0404 0404 1004 1010 1010 ................
|
|
|
- 801176c: 1010 4141 4141 4141 0101 0101 0101 0101 ..AAAAAA........
|
|
|
- 801177c: 0101 0101 0101 0101 0101 0101 1010 1010 ................
|
|
|
- 801178c: 1010 4242 4242 4242 0202 0202 0202 0202 ..BBBBBB........
|
|
|
- 801179c: 0202 0202 0202 0202 0202 0202 1010 1010 ................
|
|
|
- 80117ac: 0020 0000 0000 0000 0000 0000 0000 0000 ...............
|
|
|
- 80117bc: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 80117cc: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 80117dc: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 80117ec: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 80117fc: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 801180c: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 801181c: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
- 801182c: 0000 0000 ....
|
|
|
-
|
|
|
-08011830 <memp_num>:
|
|
|
- 8011830: 0004 0006 000a 0005 0019 0005 000f 000a ................
|
|
|
- 8011840: 0032 000f 2...
|
|
|
-
|
|
|
-08011844 <memp_sizes>:
|
|
|
- 8011844: 001c 0020 0094 001c 0010 0020 0018 0010 .. ....... .....
|
|
|
- 8011854: 0010 0614 ....
|
|
|
-
|
|
|
-08011858 <tcp_pcb_lists>:
|
|
|
- 8011858: 8344 2000 834c 2000 833c 2000 8350 2000 D.. L.. <.. P..
|
|
|
-
|
|
|
-08011868 <tcp_backoff>:
|
|
|
- 8011868: 0201 0403 0605 0707 0707 0707 0307 .............
|
|
|
-
|
|
|
-08011875 <tcp_persist_backoff>:
|
|
|
- 8011875: 0603 180c 6030 ff78 ....0`x
|
|
|
-
|
|
|
-0801187c <ip_addr_broadcast>:
|
|
|
- 801187c: ffff ffff ....
|
|
|
-
|
|
|
-08011880 <ip_addr_any>:
|
|
|
- 8011880: 0000 0000 ....
|
|
|
-
|
|
|
-08011884 <ethbroadcast>:
|
|
|
- 8011884: ffff ffff ffff ......
|
|
|
-
|
|
|
-0801188a <ethzero>:
|
|
|
- 801188a: 0000 0000 0000 3931 2e32 3631 2e38 2e31 ......192.168.1.
|
|
|
- 801189a: 0032 3931 2e32 3631 2e38 2e31 0031 3532 2.192.168.1.1.25
|
|
|
- 80118aa: 2e35 3532 2e35 3532 2e35 0030 7570 6c62 5.255.255.0.publ
|
|
|
- 80118ba: 6369 4200 2d54 3736 3130 3000 302e 302e ic.BT-6701.0.0.0
|
|
|
- 80118ca: 302e 3000 2e39 3031 322e 3130 0035 4345 .0.09.10.2015.EC
|
|
|
- 80118da: 342d 2d43 4434 302d 2d30 3030 302d 0041 -4C-4D-00-00-0A.
|
|
|
- 80118ea: 4e4b 302d 2d33 3030 3030 0033 0d0a 4149 KN-03-00003...IA
|
|
|
- 80118fa: 3a50 4220 6461 6320 6972 6974 6163 206c P: Bad critical
|
|
|
- 801190a: 6573 7474 6e69 7367 7320 6365 6f74 2072 settings sector
|
|
|
- 801191a: 5243 2e43 4620 6361 6f74 7972 6420 6665 CRC. Factory def
|
|
|
- 801192a: 7561 746c 2073 6572 7473 726f 6465 0a2e aults restored..
|
|
|
- 801193a: 000d ..
|
|
|
-
|
|
|
-0801193c <data__upload_css>:
|
|
|
- 801193c: 752f 6c70 616f 2e64 7363 0073 5448 5054 /upload.css.HTTP
|
|
|
- 801194c: 312f 302e 3220 3030 4f20 0d4b 530a 7265 /1.0 200 OK..Ser
|
|
|
- 801195c: 6576 3a72 6c20 4977 2f50 2e31 2e33 2031 ver: lwIP/1.3.1
|
|
|
- 801196c: 6828 7474 3a70 2f2f 6173 6176 6e6e 6861 (http://savannah
|
|
|
- 801197c: 6e2e 6e6f 6e67 2e75 726f 2f67 7270 6a6f .nongnu.org/proj
|
|
|
- 801198c: 6365 7374 6c2f 6977 2970 0a0d 6f43 746e ects/lwip)..Cont
|
|
|
- 801199c: 6e65 2d74 7974 6570 203a 6574 7478 632f ent-type: text/c
|
|
|
- 80119ac: 7373 0a0d 6f43 746e 6e65 2d74 6e45 6f63 ss..Content-Enco
|
|
|
- 80119bc: 6964 676e 203a 7a67 7069 0a0d 0a0d 8b1f ding: gzip......
|
|
|
- 80119cc: 0008 0000 0000 0b04 58b5 6f5b 38a4 fe16 .........X[o.8..
|
|
|
- 80119dc: ac2b 96a2 2d3a a9a0 54aa 012a 6b75 4667 +...:-...T*.ukgF
|
|
|
- 80119ec: d23d bb48 3b6f 514f 0c1e f018 6c06 4d84 =.H.o;OQ.....l.M
|
|
|
- 80119fc: d2a5 ff0c 8f7d e06f a2aa 912a ab46 44ee ....}.o...*.F..D
|
|
|
- 8011a0c: f8e4 f9f6 f39c 8b9d 7ebf 87f9 5947 a0d7 .........~..GY..
|
|
|
- 8011a1c: fc9a 61c4 b9c6 dfb7 5184 f6b8 f2fe fdfe ...a.....Q......
|
|
|
- 8011a2c: 7fc7 7fbc 0c91 8e53 afe1 8892 b090 d3af ......S.........
|
|
|
- 8011a3c: ef5c d7cb 7e2f f2ca a1b7 5d41 6849 8d1c \.../~....A]Ih..
|
|
|
- 8011a4c: fc5f 971a e698 80be d5ff a2d0 273c 84b4 _...........<'..
|
|
|
- 8011a5c: b081 3520 b3fe 19ad fdca a290 8a7d 3f3a .. 5........}.:?
|
|
|
- 8011a6c: d5ec 41df 8701 bcfb e14f 1da7 c65a 2089 ...A....O...Z..
|
|
|
- 8011a7c: c68c ae1d 2091 3c7b 64de a7ac 6722 d4af ..... {<.d.."g..
|
|
|
- 8011a8c: 530f 0741 0f81 0022 25b0 018d c099 48dd .SA..."..%.....H
|
|
|
- 8011a9c: d29a 3b9c aca4 71cb 0707 a256 87a9 5182 ...;...q..V....Q
|
|
|
- 8011aac: 1411 21a8 5bf5 11cc 01e5 1dc7 9229 15e0 ...!.[......)...
|
|
|
- 8011abc: 2fa7 0444 276a b70e 500e dffe 8b9e 1578 ./D.j'...P....x.
|
|
|
- 8011acc: 9f45 a092 17e1 5246 bd94 1d94 c9a0 8c83 E.....FR........
|
|
|
- 8011adc: acd5 6f8b 3c7e f8fc f7f5 d255 1a10 9854 ...o~<....U...T.
|
|
|
- 8011aec: 9594 7788 a8eb 8c3d 2b4a ce66 b366 5119 ...w..=.J+f.f..Q
|
|
|
- 8011afc: 4827 6356 711f 6392 c73f 9102 fb9a 2905 'HVc.q.c?......)
|
|
|
- 8011b0c: d433 dbca cfca c3be c17e 5c18 afc8 8230 3.......~..\..0.
|
|
|
- 8011b1c: f85b 3c95 f5ac 441b dfa8 da60 a0fb 9f38 [..<...D..`...8.
|
|
|
- 8011b2c: 4ce3 e0ad 037d 7f6a 721b dbc2 bd1a 69c5 .L..}.j..r.....i
|
|
|
- 8011b3c: b2cd 1197 39f5 7e61 e886 711e edbf d958 .....9a~...q..X.
|
|
|
- 8011b4c: ce61 3dfd ca9c 99a6 d684 e284 2d40 f648 a..=........@-H.
|
|
|
- 8011b5c: 4258 b543 68d1 388a a396 a37a 3298 f9f1 XBC..h.8..z..2..
|
|
|
- 8011b6c: 0329 762d e6ac b7cf 16d3 5194 989c 471b ).-v.......Q...G
|
|
|
- 8011b7c: 53e3 f245 d31c 5f67 06e0 08b0 347c 446f .SE...g_....|4oD
|
|
|
- 8011b8c: 99c3 44e2 d607 5168 f607 511b e08c 7b46 ...D..hQ...Q..F{
|
|
|
- 8011b9c: 4e50 315c 3380 5eb0 0848 4460 a694 93dd PN\1.3.^H.`D....
|
|
|
- 8011bac: a220 cfc6 b2c6 ca41 6084 bc4d 0f6a 0e5e .....A..`M.j.^.
|
|
|
- 8011bbc: 389f 531f b59f 6b42 038a 5a4e b36a 1abf .8.S..Bk..NZj...
|
|
|
- 8011bcc: 447b 98d1 5417 b8cb ab78 4c71 7804 364f {D...T..x.qL.xO6
|
|
|
- 8011bdc: 2b56 0423 8807 b8d7 4119 2f9d 3183 145a V+#......A./.1Z.
|
|
|
- 8011bec: c945 3a8c 29be f00a f061 e53e 4182 688e E..:.)..a.>..A.h
|
|
|
- 8011bfc: bb89 e0d0 7296 b223 5157 b6a2 d223 4742 .....r#.WQ..#.BG
|
|
|
- 8011c0c: 8cd3 9a6c 5ac7 bf4c 7987 5ac7 e0e9 6081 ..l..ZL..y.Z...`
|
|
|
- 8011c1c: 5965 6763 3f43 3cbc ecc3 6ae5 0e17 312c eYcgC?.<...j..,1
|
|
|
- 8011c2c: 0d58 c80c d081 0186 c5d2 87e3 d3e8 4968 X.............hI
|
|
|
- 8011c3c: 78a6 a4a1 edbb 44a7 8379 e635 8745 e490 .x.....Dy.5.E...
|
|
|
- 8011c4c: ac14 838d 0b70 82ba c09d ca22 4114 56b8 ....p....."..A.V
|
|
|
- 8011c5c: 7d92 dca9 ee25 87c0 076f c969 66a2 b1af .}..%...o.i..f..
|
|
|
- 8011c6c: 8df6 3b51 8db8 2b14 78dc 9277 5528 4c37 ..Q;...+.xw.(U7L
|
|
|
- 8011c7c: 5b27 a65a 10ec 3800 3819 eba4 8f81 d580 '[Z....8.8......
|
|
|
- 8011c8c: c00f f64b 7e53 8d2c 8b2d 16c7 2528 0e49 ..K.S~,.-...(%I.
|
|
|
- 8011c9c: 868e 4466 17a8 cc6c 1018 25f1 81cd d824 ..fD..l....%..$.
|
|
|
- 8011cac: a8e7 8f69 4582 28c3 ff03 b0cc 7d3f b325 ..i..E.(....?}%.
|
|
|
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|
- 80132dd: d099 972a 38e5 f6a0 f70f 711b f6e7 bd95 ..*..8.....q....
|
|
|
- 80132ed: cf74 a5ed f1bd bfbf 85b8 125d b3f7 e25d t.........]...].
|
|
|
- 80132fd: 15c7 973e 75a4 71b8 6ee7 5ee1 33ba 3bf7 ..>..u.q.n.^.3.;
|
|
|
- 801330d: 111e 3874 37b3 8976 ff56 26be 0af6 406f ..t8.7v.V..&..o@
|
|
|
- 801331d: f77f bddc dbc0 ddae 2ed9 2996 e618 fb41 ...........)..A.
|
|
|
- 801332d: fb6b 930a b85c 0f85 d85c 3e77 7f9f 1a62 k...\...\.w>..b.
|
|
|
- 801333d: a4ee d7ac d28f 35dd cf59 1e0e 323f f266 .......5Y...?2f.
|
|
|
- 801334d: 7e14 a1ac bb32 8d3f 118b 32fe 2705 aee4 .~..2.?....2.'..
|
|
|
- 801335d: a769 fa6b 3b12 853b df67 3fa6 3080 3d01 i.k..;;.g..?.0.=
|
|
|
- 801336d: a290 95d4 4dce 63ec 8306 8827 75a5 f58f .....M.c..'..u..
|
|
|
- 801337d: 5404 1f40 183e 88d0 bd47 7bfe 0543 0b2a .T@.>...G..{C.*.
|
|
|
- 801338d: 7f42 33b4 32d5 bc23 d280 a204 f3c3 bc77 B..3.2#.......w.
|
|
|
- 801339d: 1990 e037 ce99 1975 d8ac bc66 9da3 6f6a ..7...u...f...jo
|
|
|
- 80133ad: e036 6fc3 18f8 2a02 a4d5 2b36 fa12 f889 6..o...*..6+....
|
|
|
- 80133bd: 8d3c 500b 3343 c44a 66e6 a7d3 a58c e287 <..PC3J..f......
|
|
|
- 80133cd: 0228 dbd6 644e d01e 165c 6d80 62ca 9b33 (...Nd..\..m.b3.
|
|
|
- 80133dd: 7840 478a ff7d 8fe7 36ab 6c38 d5f5 a340 @x.G}....68l..@.
|
|
|
- 80133ed: cff6 2ba6 bec4 4821 85fb b6bd dd6f f139 ...+..!H....o.9.
|
|
|
- 80133fd: fadc bed6 93c1 f8d7 20dc 9f08 c225 1e44 ......... ..%.D.
|
|
|
- 801340d: be72 f5be 7fb0 2b14 eac4 e7d3 7d8c 628f r......+.....}.b
|
|
|
- 801341d: d996 98d7 17cf 9e10 4c62 ba3f b417 422a ........bL?...*B
|
|
|
- 801342d: 8a11 5782 b795 ffb1 dd3c 24a4 1593 0b4f ...W....<..$..O.
|
|
|
- 801343d: 68c8 9692 8fc0 78e7 0f71 443e 57fd 9483 .h.....xq.>D.W..
|
|
|
- 801344d: cdd0 431c 6856 4751 f617 8a2d 6fe8 8b2f ...CVhQG..-..o/.
|
|
|
- 801345d: ac88 72d4 7ee6 1145 c4ae 1689 e294 9795 ...r.~E.........
|
|
|
- 801346d: 3bd9 e054 58ba 417b 6230 9189 78ff 121d .;T..X{A0b...x..
|
|
|
- 801347d: e514 a572 af30 05ea 758a 1781 917b f4a2 ..r.0....u..{...
|
|
|
- 801348d: cbdc 721d 3988 56ef 0089 908e de9e 7cf6 ...r.9.V.......|
|
|
|
- 801349d: 70de ebdb 3dcf 4647 418e 26d7 9db9 ad4f .p...=GF.A.&..O.
|
|
|
- 80134ad: bac6 60ae a7ac 3ac0 2f03 e00a a0e5 0e71 ...`...:./....q.
|
|
|
- 80134bd: a0da 6a30 183f 896e adb5 8313 a1db d89d ..0j?.n.........
|
|
|
- 80134cd: 80ce b8e2 c6e0 5e40 c19b 293f 04f9 af19 ......@^..?)....
|
|
|
- 80134dd: accc 1880 9d59 7c14 68c6 ab8a 98e4 9efa ....Y..|.h......
|
|
|
- 80134ed: eedc 8fa4 dd3a 047a 8861 e30b b833 ce1f ....:.z.a...3...
|
|
|
- 80134fd: ed57 4bbf a300 7bfb e24f 2a54 749a aa9b W..K...{O.T*.t..
|
|
|
- 801350d: 2895 38a4 96ee 59ca 2e07 de8d c157 57ff .(.8...Y....W..W
|
|
|
- 801351d: 88e4 9eaa 9a14 7b67 6146 08b1 c46c f0d5 ......g{Fa..l...
|
|
|
- 801352d: 134e 9b6e c1f4 6f12 bd03 31a2 d512 035d N.n....o...1..].
|
|
|
- 801353d: 2333 3559 b533 ff56 f93c 5417 58c3 1a63 3#Y53.V.<..T.Xc.
|
|
|
- 801354d: 0006 4400 ...
|
|
|
-
|
|
|
-08013550 <file__success_html>:
|
|
|
- 8013550: 2244 0801 2d7f 0801 2d8f 0801 03be 0000 D"...-...-......
|
|
|
- 8013560: 0001 0000 4547 2054 002f 4547 2054 752f ....GET /.GET /u
|
|
|
- 8013570: 6c70 616f 2e64 7363 0073 4547 2054 752f pload.css.GET /u
|
|
|
- 8013580: 6c70 616f 2e64 736a 4700 5445 2f20 6f67 pload.js.GET /go
|
|
|
- 8013590: 6162 6b63 632e 6967 4700 5445 2f20 6166 back.cgi.GET /fa
|
|
|
- 80135a0: 6976 6f63 2e6e 6369 006f 692f 646e 7865 vicon.ico./index
|
|
|
- 80135b0: 682e 6d74 006c 4f50 5453 2f20 7075 6f6c .html.POST /uplo
|
|
|
- 80135c0: 6461 632e 6967 6600 6c69 6e65 6d61 3d65 ad.cgi.filename=
|
|
|
- 80135d0: 2f00 7075 6f6c 6461 682e 6d74 006c 6946 ./upload.html.Fi
|
|
|
- 80135e0: 656c 203a 7325 0d0a 2500 2064 7962 6574 le: %s...%d byte
|
|
|
- 80135f0: 2073 0d0a 2f00 7573 6363 7365 2e73 7468 s .../success.ht
|
|
|
- 8013600: 6c6d 2f00 7265 6f72 2e72 7468 6c6d 0000 ml./error.html..
|
|
|
-
|
|
|
-08013610 <file__upload_css>:
|
|
|
- 8013610: 3550 0801 193c 0801 1948 0801 08e9 0000 P5..<...H.......
|
|
|
- 8013620: 0001 0000 3931 2e32 3631 2e38 3431 342e ....192.168.14.4
|
|
|
- 8013630: 0038 3931 2e32 3631 2e38 3431 312e 6c00 8.192.168.14.1.l
|
|
|
- 8013640: 616f 4d64 646f 3a65 2520 0d64 620a 6f6f oadMode: %d..boo
|
|
|
- 8013650: 5474 7972 203a 6425 0a0d 5200 6e75 6d20 tTry: %d...Run m
|
|
|
- 8013660: 6961 206e 5746 0d0a 0000 0000 0043 0000 ain FW......C...
|
|
|
-
|
|
|
-08013670 <_init>:
|
|
|
- 8013670: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
- 8013672: bf00 nop
|
|
|
- 8013674: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
- 8013676: bc08 pop {r3}
|
|
|
- 8013678: 469e mov lr, r3
|
|
|
- 801367a: 4770 bx lr
|
|
|
-
|
|
|
-0801367c <_fini>:
|
|
|
- 801367c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
- 801367e: bf00 nop
|
|
|
- 8013680: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
- 8013682: bc08 pop {r3}
|
|
|
- 8013684: 469e mov lr, r3
|
|
|
- 8013686: 4770 bx lr
|
|
|
+ 80116a0: f7ff bffe b.w 80116a0 <ADC_IRQHandler>
|
|
|
+
|
|
|
+080116a4 <_ctype_>:
|
|
|
+ 80116a4: 2000 2020 2020 2020 2020 2828 2828 2028 . (((((
|
|
|
+ 80116b4: 2020 2020 2020 2020 2020 2020 2020 2020
|
|
|
+ 80116c4: 8820 1010 1010 1010 1010 1010 1010 1010 ...............
|
|
|
+ 80116d4: 0410 0404 0404 0404 0404 1004 1010 1010 ................
|
|
|
+ 80116e4: 1010 4141 4141 4141 0101 0101 0101 0101 ..AAAAAA........
|
|
|
+ 80116f4: 0101 0101 0101 0101 0101 0101 1010 1010 ................
|
|
|
+ 8011704: 1010 4242 4242 4242 0202 0202 0202 0202 ..BBBBBB........
|
|
|
+ 8011714: 0202 0202 0202 0202 0202 0202 1010 1010 ................
|
|
|
+ 8011724: 0020 0000 0000 0000 0000 0000 0000 0000 ...............
|
|
|
+ 8011734: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011744: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011754: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011764: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011774: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011784: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 8011794: 0000 0000 0000 0000 0000 0000 0000 0000 ................
|
|
|
+ 80117a4: 0000 0000 ....
|
|
|
+
|
|
|
+080117a8 <memp_num>:
|
|
|
+ 80117a8: 0004 0006 000a 0005 0019 0005 000f 000a ................
|
|
|
+ 80117b8: 0032 000f 2...
|
|
|
+
|
|
|
+080117bc <memp_sizes>:
|
|
|
+ 80117bc: 001c 0020 0094 001c 0010 0020 0018 0010 .. ....... .....
|
|
|
+ 80117cc: 0010 0614 ....
|
|
|
+
|
|
|
+080117d0 <tcp_pcb_lists>:
|
|
|
+ 80117d0: 8344 2000 834c 2000 833c 2000 8350 2000 D.. L.. <.. P..
|
|
|
+
|
|
|
+080117e0 <tcp_backoff>:
|
|
|
+ 80117e0: 0201 0403 0605 0707 0707 0707 0307 .............
|
|
|
+
|
|
|
+080117ed <tcp_persist_backoff>:
|
|
|
+ 80117ed: 0603 180c 6030 ff78 ....0`x
|
|
|
+
|
|
|
+080117f4 <ip_addr_broadcast>:
|
|
|
+ 80117f4: ffff ffff ....
|
|
|
+
|
|
|
+080117f8 <ip_addr_any>:
|
|
|
+ 80117f8: 0000 0000 ....
|
|
|
+
|
|
|
+080117fc <ethbroadcast>:
|
|
|
+ 80117fc: ffff ffff ffff ......
|
|
|
+
|
|
|
+08011802 <ethzero>:
|
|
|
+ 8011802: 0000 0000 0000 3931 2e32 3631 2e38 2e31 ......192.168.1.
|
|
|
+ 8011812: 0032 3931 2e32 3631 2e38 2e31 0031 3532 2.192.168.1.1.25
|
|
|
+ 8011822: 2e35 3532 2e35 3532 2e35 0030 3930 312e 5.255.255.0.09.1
|
|
|
+ 8011832: 2e30 3032 3531 4500 2d43 4334 342d 2d44 0.2015.EC-4C-4D-
|
|
|
+ 8011842: 3030 302d 2d30 4130 4b00 2d4e 3330 302d 00-00-0A.KN-03-0
|
|
|
+ 8011852: 3030 3330 0a00 490d 5041 203a 6142 2064 0003...IAP: Bad
|
|
|
+ 8011862: 7263 7469 6369 6c61 7320 7465 6974 676e critical setting
|
|
|
+ 8011872: 2073 6573 7463 726f 4320 4352 202e 6146 s sector CRC. Fa
|
|
|
+ 8011882: 7463 726f 2079 6564 6166 6c75 7374 7220 ctory defaults r
|
|
|
+ 8011892: 7365 6f74 6572 2e64 0d0a 2f00 estored....
|
|
|
+
|
|
|
+0801189d <data__upload_css>:
|
|
|
+ 801189d: 752f 6c70 616f 2e64 7363 0073 5448 5054 /upload.css.HTTP
|
|
|
+ 80118ad: 312f 302e 3220 3030 4f20 0d4b 530a 7265 /1.0 200 OK..Ser
|
|
|
+ 80118bd: 6576 3a72 6c20 4977 2f50 2e31 2e33 2031 ver: lwIP/1.3.1
|
|
|
+ 80118cd: 6828 7474 3a70 2f2f 6173 6176 6e6e 6861 (http://savannah
|
|
|
+ 80118dd: 6e2e 6e6f 6e67 2e75 726f 2f67 7270 6a6f .nongnu.org/proj
|
|
|
+ 80118ed: 6365 7374 6c2f 6977 2970 0a0d 6f43 746e ects/lwip)..Cont
|
|
|
+ 80118fd: 6e65 2d74 7974 6570 203a 6574 7478 632f ent-type: text/c
|
|
|
+ 801190d: 7373 0a0d 6f43 746e 6e65 2d74 6e45 6f63 ss..Content-Enco
|
|
|
+ 801191d: 6964 676e 203a 7a67 7069 0a0d 0a0d 8b1f ding: gzip......
|
|
|
+ 801192d: 0008 0000 0000 0b04 58b5 6f5b 38a4 fe16 .........X[o.8..
|
|
|
+ 801193d: ac2b 96a2 2d3a a9a0 54aa 012a 6b75 4667 +...:-...T*.ukgF
|
|
|
+ 801194d: d23d bb48 3b6f 514f 0c1e f018 6c06 4d84 =.H.o;OQ.....l.M
|
|
|
+ 801195d: d2a5 ff0c 8f7d e06f a2aa 912a ab46 44ee ....}.o...*.F..D
|
|
|
+ 801196d: f8e4 f9f6 f39c 8b9d 7ebf 87f9 5947 a0d7 .........~..GY..
|
|
|
+ 801197d: fc9a 61c4 b9c6 dfb7 5184 f6b8 f2fe fdfe ...a.....Q......
|
|
|
+ 801198d: 7fc7 7fbc 0c91 8e53 afe1 8892 b090 d3af ......S.........
|
|
|
+ 801199d: ef5c d7cb 7e2f f2ca a1b7 5d41 6849 8d1c \.../~....A]Ih..
|
|
|
+ 80119ad: fc5f 971a e698 80be d5ff a2d0 273c 84b4 _...........<'..
|
|
|
+ 80119bd: b081 3520 b3fe 19ad fdca a290 8a7d 3f3a .. 5........}.:?
|
|
|
+ 80119cd: d5ec 41df 8701 bcfb e14f 1da7 c65a 2089 ...A....O...Z..
|
|
|
+ 80119dd: c68c ae1d 2091 3c7b 64de a7ac 6722 d4af ..... {<.d.."g..
|
|
|
+ 80119ed: 530f 0741 0f81 0022 25b0 018d c099 48dd .SA..."..%.....H
|
|
|
+ 80119fd: d29a 3b9c aca4 71cb 0707 a256 87a9 5182 ...;...q..V....Q
|
|
|
+ 8011a0d: 1411 21a8 5bf5 11cc 01e5 1dc7 9229 15e0 ...!.[......)...
|
|
|
+ 8011a1d: 2fa7 0444 276a b70e 500e dffe 8b9e 1578 ./D.j'...P....x.
|
|
|
+ 8011a2d: 9f45 a092 17e1 5246 bd94 1d94 c9a0 8c83 E.....FR........
|
|
|
+ 8011a3d: acd5 6f8b 3c7e f8fc f7f5 d255 1a10 9854 ...o~<....U...T.
|
|
|
+ 8011a4d: 9594 7788 a8eb 8c3d 2b4a ce66 b366 5119 ...w..=.J+f.f..Q
|
|
|
+ 8011a5d: 4827 6356 711f 6392 c73f 9102 fb9a 2905 'HVc.q.c?......)
|
|
|
+ 8011a6d: d433 dbca cfca c3be c17e 5c18 afc8 8230 3.......~..\..0.
|
|
|
+ 8011a7d: f85b 3c95 f5ac 441b dfa8 da60 a0fb 9f38 [..<...D..`...8.
|
|
|
+ 8011a8d: 4ce3 e0ad 037d 7f6a 721b dbc2 bd1a 69c5 .L..}.j..r.....i
|
|
|
+ 8011a9d: b2cd 1197 39f5 7e61 e886 711e edbf d958 .....9a~...q..X.
|
|
|
+ 8011aad: ce61 3dfd ca9c 99a6 d684 e284 2d40 f648 a..=........@-H.
|
|
|
+ 8011abd: 4258 b543 68d1 388a a396 a37a 3298 f9f1 XBC..h.8..z..2..
|
|
|
+ 8011acd: 0329 762d e6ac b7cf 16d3 5194 989c 471b ).-v.......Q...G
|
|
|
+ 8011add: 53e3 f245 d31c 5f67 06e0 08b0 347c 446f .SE...g_....|4oD
|
|
|
+ 8011aed: 99c3 44e2 d607 5168 f607 511b e08c 7b46 ...D..hQ...Q..F{
|
|
|
+ 8011afd: 4e50 315c 3380 5eb0 0848 4460 a694 93dd PN\1.3.^H.`D....
|
|
|
+ 8011b0d: a220 cfc6 b2c6 ca41 6084 bc4d 0f6a 0e5e .....A..`M.j.^.
|
|
|
+ 8011b1d: 389f 531f b59f 6b42 038a 5a4e b36a 1abf .8.S..Bk..NZj...
|
|
|
+ 8011b2d: 447b 98d1 5417 b8cb ab78 4c71 7804 364f {D...T..x.qL.xO6
|
|
|
+ 8011b3d: 2b56 0423 8807 b8d7 4119 2f9d 3183 145a V+#......A./.1Z.
|
|
|
+ 8011b4d: c945 3a8c 29be f00a f061 e53e 4182 688e E..:.)..a.>..A.h
|
|
|
+ 8011b5d: bb89 e0d0 7296 b223 5157 b6a2 d223 4742 .....r#.WQ..#.BG
|
|
|
+ 8011b6d: 8cd3 9a6c 5ac7 bf4c 7987 5ac7 e0e9 6081 ..l..ZL..y.Z...`
|
|
|
+ 8011b7d: 5965 6763 3f43 3cbc ecc3 6ae5 0e17 312c eYcgC?.<...j..,1
|
|
|
+ 8011b8d: 0d58 c80c d081 0186 c5d2 87e3 d3e8 4968 X.............hI
|
|
|
+ 8011b9d: 78a6 a4a1 edbb 44a7 8379 e635 8745 e490 .x.....Dy.5.E...
|
|
|
+ 8011bad: ac14 838d 0b70 82ba c09d ca22 4114 56b8 ....p....."..A.V
|
|
|
+ 8011bbd: 7d92 dca9 ee25 87c0 076f c969 66a2 b1af .}..%...o.i..f..
|
|
|
+ 8011bcd: 8df6 3b51 8db8 2b14 78dc 9277 5528 4c37 ..Q;...+.xw.(U7L
|
|
|
+ 8011bdd: 5b27 a65a 10ec 3800 3819 eba4 8f81 d580 '[Z....8.8......
|
|
|
+ 8011bed: c00f f64b 7e53 8d2c 8b2d 16c7 2528 0e49 ..K.S~,.-...(%I.
|
|
|
+ 8011bfd: 868e 4466 17a8 cc6c 1018 25f1 81cd d824 ..fD..l....%..$.
|
|
|
+ 8011c0d: a8e7 8f69 4582 28c3 ff03 b0cc 7d3f b325 ..i..E.(....?}%.
|
|
|
+ 8011c1d: 00d2 98fd 70f6 ea79 da13 c2f6 4071 035c .....py.....q@\.
|
|
|
+ 8011c2d: e73d 6d33 5460 638b 2b42 3f88 d122 663e =.3m`T.cB+.?".>f
|
|
|
+ 8011c3d: d2fe 656e d19d ed78 781d 3ead 8661 27bd ..ne..x..x.>a..'
|
|
|
+ 8011c4d: a49c b635 0327 e14f 1d28 150d 649d d518 ..5.'.O.(....d..
|
|
|
+ 8011c5d: 37a6 64d8 f408 c014 f127 e2d6 5a6f acfc .7.d....'...oZ..
|
|
|
+ 8011c6d: 6b31 4411 2c07 248e d860 8886 c1e7 031a 1k.D.,.$`.......
|
|
|
+ 8011c7d: 2db5 c046 0cd6 7ac7 927d 1df5 d887 32d7 .-F....z}......2
|
|
|
+ 8011c8d: 82a2 96af 413e 4218 2e80 f67f 639d e127 ....>A.B.....c'.
|
|
|
+ 8011c9d: 1660 b8e5 7d40 462d 5507 e156 05ec 77ec `...@}-F.UV....w
|
|
|
+ 8011cad: a284 1043 66c6 8e10 7579 5f80 0874 6867 ..C..f..yu._t.gh
|
|
|
+ 8011cbd: c179 8e9c f39c df69 b8a4 8e7b 7b63 4263 y.....i...{.c{cB
|
|
|
+ 8011ccd: ee29 de02 4c42 8a37 36bc 821b f1d5 eb6c )...BL7..6....l.
|
|
|
+ 8011cdd: cacf 9ccb 1c95 98d4 8b55 fa77 5e7b a53e ........U.w.{^>.
|
|
|
+ 8011ced: c733 d254 0be9 eb82 d5dc 41b4 df30 0b54 3.T........A0.T.
|
|
|
+ 8011cfd: c802 1916 17ae 7b2e 4169 338e 41d6 6672 .......{iA.3.Arf
|
|
|
+ 8011d0d: c974 544d 51f4 8387 4d6f 4025 81b8 e120 t.MT.Q..oM%@.. .
|
|
|
+ 8011d1d: f785 5632 e178 7e0e 9627 de1c 3dba 2624 ..2Vx..~'....=$&
|
|
|
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|
+ 801334d: cff6 2ba6 bec4 4821 85fb b6bd dd6f f139 ...+..!H....o.9.
|
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|
+ 801335d: fadc bed6 93c1 f8d7 20dc 9f08 c225 1e44 ......... ..%.D.
|
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|
+ 801336d: be72 f5be 7fb0 2b14 eac4 e7d3 7d8c 628f r......+.....}.b
|
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|
+ 801337d: d996 98d7 17cf 9e10 4c62 ba3f b417 422a ........bL?...*B
|
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|
+ 801338d: 8a11 5782 b795 ffb1 dd3c 24a4 1593 0b4f ...W....<..$..O.
|
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|
+ 801339d: 68c8 9692 8fc0 78e7 0f71 443e 57fd 9483 .h.....xq.>D.W..
|
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|
+ 80133ad: cdd0 431c 6856 4751 f617 8a2d 6fe8 8b2f ...CVhQG..-..o/.
|
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|
+ 80133bd: ac88 72d4 7ee6 1145 c4ae 1689 e294 9795 ...r.~E.........
|
|
|
+ 80133cd: 3bd9 e054 58ba 417b 6230 9189 78ff 121d .;T..X{A0b...x..
|
|
|
+ 80133dd: e514 a572 af30 05ea 758a 1781 917b f4a2 ..r.0....u..{...
|
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|
+ 80133ed: cbdc 721d 3988 56ef 0089 908e de9e 7cf6 ...r.9.V.......|
|
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|
+ 80133fd: 70de ebdb 3dcf 4647 418e 26d7 9db9 ad4f .p...=GF.A.&..O.
|
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|
+ 801340d: bac6 60ae a7ac 3ac0 2f03 e00a a0e5 0e71 ...`...:./....q.
|
|
|
+ 801341d: a0da 6a30 183f 896e adb5 8313 a1db d89d ..0j?.n.........
|
|
|
+ 801342d: 80ce b8e2 c6e0 5e40 c19b 293f 04f9 af19 ......@^..?)....
|
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|
+ 801343d: accc 1880 9d59 7c14 68c6 ab8a 98e4 9efa ....Y..|.h......
|
|
|
+ 801344d: eedc 8fa4 dd3a 047a 8861 e30b b833 ce1f ....:.z.a...3...
|
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|
+ 801345d: ed57 4bbf a300 7bfb e24f 2a54 749a aa9b W..K...{O.T*.t..
|
|
|
+ 801346d: 2895 38a4 96ee 59ca 2e07 de8d c157 57ff .(.8...Y....W..W
|
|
|
+ 801347d: 88e4 9eaa 9a14 7b67 6146 08b1 c46c f0d5 ......g{Fa..l...
|
|
|
+ 801348d: 134e 9b6e c1f4 6f12 bd03 31a2 d512 035d N.n....o...1..].
|
|
|
+ 801349d: 2333 3559 b533 ff56 f93c 5417 58c3 1a63 3#Y53.V.<..T.Xc.
|
|
|
+ 80134ad: 0006 a400 ...
|
|
|
+
|
|
|
+080134b0 <file__success_html>:
|
|
|
+ 80134b0: 21a4 0801 2cdf 0801 2cef 0801 03be 0000 .!...,...,......
|
|
|
+ 80134c0: 0001 0000 4547 2054 002f 4547 2054 752f ....GET /.GET /u
|
|
|
+ 80134d0: 6c70 616f 2e64 7363 0073 4547 2054 752f pload.css.GET /u
|
|
|
+ 80134e0: 6c70 616f 2e64 736a 4700 5445 2f20 6f67 pload.js.GET /go
|
|
|
+ 80134f0: 6162 6b63 632e 6967 4700 5445 2f20 6166 back.cgi.GET /fa
|
|
|
+ 8013500: 6976 6f63 2e6e 6369 006f 692f 646e 7865 vicon.ico./index
|
|
|
+ 8013510: 682e 6d74 006c 4f50 5453 2f20 7075 6f6c .html.POST /uplo
|
|
|
+ 8013520: 6461 632e 6967 6600 6c69 6e65 6d61 3d65 ad.cgi.filename=
|
|
|
+ 8013530: 2f00 7075 6f6c 6461 682e 6d74 006c 6946 ./upload.html.Fi
|
|
|
+ 8013540: 656c 203a 7325 0d0a 2500 2064 7962 6574 le: %s...%d byte
|
|
|
+ 8013550: 2073 0d0a 2f00 7573 6363 7365 2e73 7468 s .../success.ht
|
|
|
+ 8013560: 6c6d 2f00 7265 6f72 2e72 7468 6c6d 0000 ml./error.html..
|
|
|
+
|
|
|
+08013570 <file__upload_css>:
|
|
|
+ 8013570: 34b0 0801 189d 0801 18a9 0801 08e9 0000 .4..............
|
|
|
+ 8013580: 0001 0000 3931 2e32 3631 2e38 3431 342e ....192.168.14.4
|
|
|
+ 8013590: 0038 3931 2e32 3631 2e38 3431 312e 6c00 8.192.168.14.1.l
|
|
|
+ 80135a0: 616f 4d64 646f 3a65 2520 0d64 620a 6f6f oadMode: %d..boo
|
|
|
+ 80135b0: 5474 7972 203a 6425 0a0d 5200 6e75 6d20 tTry: %d...Run m
|
|
|
+ 80135c0: 6961 206e 5746 0d0a 0000 0000 0043 0000 ain FW......C...
|
|
|
+
|
|
|
+080135d0 <_init>:
|
|
|
+ 80135d0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
+ 80135d2: bf00 nop
|
|
|
+ 80135d4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
+ 80135d6: bc08 pop {r3}
|
|
|
+ 80135d8: 469e mov lr, r3
|
|
|
+ 80135da: 4770 bx lr
|
|
|
+
|
|
|
+080135dc <_fini>:
|
|
|
+ 80135dc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
+ 80135de: bf00 nop
|
|
|
+ 80135e0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
+ 80135e2: bc08 pop {r3}
|
|
|
+ 80135e4: 469e mov lr, r3
|
|
|
+ 80135e6: 4770 bx lr
|
balbekova