stm32g0xx_ll_usb.c 40 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32g0xx_ll_usb.c
  4. * @author MCD Application Team
  5. * @brief USB Low Layer HAL module driver.
  6. *
  7. * This file provides firmware functions to manage the following
  8. * functionalities of the USB Peripheral Controller:
  9. * + Initialization/de-initialization functions
  10. * + I/O operation functions
  11. * + Peripheral Control functions
  12. * + Peripheral State functions
  13. *
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * Copyright (c) 2018 STMicroelectronics.
  18. * All rights reserved.
  19. *
  20. * This software is licensed under terms that can be found in the LICENSE file
  21. * in the root directory of this software component.
  22. * If no LICENSE file comes with this software, it is provided AS-IS.
  23. *
  24. ******************************************************************************
  25. @verbatim
  26. ==============================================================================
  27. ##### How to use this driver #####
  28. ==============================================================================
  29. [..]
  30. (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
  31. (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
  32. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
  33. @endverbatim
  34. ******************************************************************************
  35. */
  36. /* Includes ------------------------------------------------------------------*/
  37. #include "stm32g0xx_hal.h"
  38. /** @addtogroup STM32G0xx_LL_USB_DRIVER
  39. * @{
  40. */
  41. #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
  42. #if defined (USB_DRD_FS)
  43. /* Private typedef -----------------------------------------------------------*/
  44. /* Private define ------------------------------------------------------------*/
  45. /* Private macro -------------------------------------------------------------*/
  46. /* Private variables ---------------------------------------------------------*/
  47. /* Private function prototypes -----------------------------------------------*/
  48. /* Private functions ---------------------------------------------------------*/
  49. static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx);
  50. #if (USE_USB_DOUBLE_BUFFER == 1U)
  51. static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx,
  52. USB_DRD_HCTypeDef *hc,
  53. uint32_t ch_reg,
  54. uint32_t *len);
  55. static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx,
  56. USB_DRD_HCTypeDef *hc,
  57. uint32_t len);
  58. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  59. /**
  60. * @brief Reset the USB Core (needed after USB clock settings change)
  61. * @param USBx Selected device
  62. * @retval HAL status
  63. */
  64. static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx)
  65. {
  66. /* Disable Host Mode */
  67. USBx->CNTR &= ~USB_CNTR_HOST;
  68. /* Force Reset IP */
  69. USBx->CNTR |= USB_CNTR_USBRST;
  70. return HAL_OK;
  71. }
  72. /**
  73. * @brief Initializes the USB Core
  74. * @param USBx USB Instance
  75. * @param cfg pointer to a USB_CfgTypeDef structure that contains
  76. * the configuration information for the specified USBx peripheral.
  77. * @retval HAL status
  78. */
  79. HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
  80. {
  81. HAL_StatusTypeDef ret;
  82. UNUSED(cfg);
  83. if (USBx == NULL)
  84. {
  85. return HAL_ERROR;
  86. }
  87. /* Reset after a PHY select */
  88. ret = USB_CoreReset(USBx);
  89. /* Clear pending interrupts */
  90. USBx->ISTR = 0U;
  91. return ret;
  92. }
  93. /**
  94. * @brief USB_EnableGlobalInt
  95. * Enables the controller's Global Int in the AHB Config reg
  96. * @param USBx Selected device
  97. * @retval HAL status
  98. */
  99. HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx)
  100. {
  101. uint32_t winterruptmask;
  102. /* Clear pending interrupts */
  103. USBx->ISTR = 0U;
  104. /* Set winterruptmask variable */
  105. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  106. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  107. USB_CNTR_SOFM | USB_CNTR_ESOFM |
  108. USB_CNTR_RESETM | USB_CNTR_L1REQM;
  109. /* Set interrupt mask */
  110. USBx->CNTR = winterruptmask;
  111. return HAL_OK;
  112. }
  113. /**
  114. * @brief USB_DisableGlobalInt
  115. * Disable the controller's Global Int in the AHB Config reg
  116. * @param USBx Selected device
  117. * @retval HAL status
  118. */
  119. HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx)
  120. {
  121. uint32_t winterruptmask;
  122. /* Set winterruptmask variable */
  123. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  124. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  125. USB_CNTR_SOFM | USB_CNTR_ESOFM |
  126. USB_CNTR_RESETM | USB_CNTR_L1REQM;
  127. /* Clear interrupt mask */
  128. USBx->CNTR &= ~winterruptmask;
  129. return HAL_OK;
  130. }
  131. /**
  132. * @brief USB_SetCurrentMode Set functional mode
  133. * @param USBx Selected device
  134. * @param mode current core mode
  135. * This parameter can be one of the these values:
  136. * @arg USB_DEVICE_MODE Peripheral mode
  137. * @retval HAL status
  138. */
  139. HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode)
  140. {
  141. if (mode == USB_DEVICE_MODE)
  142. {
  143. USBx->CNTR &= ~USB_CNTR_HOST;
  144. }
  145. else if (mode == USB_HOST_MODE)
  146. {
  147. USBx->CNTR |= USB_CNTR_HOST;
  148. }
  149. else
  150. {
  151. return HAL_ERROR;
  152. }
  153. return HAL_OK;
  154. }
  155. /**
  156. * @brief USB_DevInit Initializes the USB controller registers
  157. * for device mode
  158. * @param USBx Selected device
  159. * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains
  160. * the configuration information for the specified USBx peripheral.
  161. * @retval HAL status
  162. */
  163. HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
  164. {
  165. HAL_StatusTypeDef ret;
  166. /* Prevent unused argument(s) compilation warning */
  167. UNUSED(cfg);
  168. /* Force Reset */
  169. USBx->CNTR = USB_CNTR_USBRST;
  170. /* Release Reset */
  171. USBx->CNTR &= ~USB_CNTR_USBRST;
  172. /* Set the Device Mode */
  173. ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE);
  174. /* Clear pending interrupts */
  175. USBx->ISTR = 0U;
  176. return ret;
  177. }
  178. /**
  179. * @brief USB_FlushTxFifo : Flush a Tx FIFO
  180. * @param USBx : Selected device
  181. * @param num : FIFO number
  182. * This parameter can be a value from 1 to 15
  183. 15 means Flush all Tx FIFOs
  184. * @retval HAL status
  185. */
  186. HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num)
  187. {
  188. /* Prevent unused argument(s) compilation warning */
  189. UNUSED(USBx);
  190. UNUSED(num);
  191. /* NOTE : - This function is not required by USB Device FS peripheral, it is used
  192. only by USB OTG FS peripheral.
  193. - This function is added to ensure compatibility across platforms.
  194. */
  195. return HAL_OK;
  196. }
  197. /**
  198. * @brief USB_FlushRxFifo : Flush Rx FIFO
  199. * @param USBx : Selected device
  200. * @retval HAL status
  201. */
  202. HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx)
  203. {
  204. /* Prevent unused argument(s) compilation warning */
  205. UNUSED(USBx);
  206. /* NOTE : - This function is not required by USB Device FS peripheral, it is used
  207. only by USB OTG FS peripheral.
  208. - This function is added to ensure compatibility across platforms.
  209. */
  210. return HAL_OK;
  211. }
  212. #if defined (HAL_PCD_MODULE_ENABLED)
  213. /**
  214. * @brief Activate and configure an endpoint
  215. * @param USBx Selected device
  216. * @param ep pointer to endpoint structure
  217. * @retval HAL status
  218. */
  219. HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  220. {
  221. HAL_StatusTypeDef ret = HAL_OK;
  222. uint32_t wEpRegVal;
  223. wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
  224. /* initialize Endpoint */
  225. switch (ep->type)
  226. {
  227. case EP_TYPE_CTRL:
  228. wEpRegVal |= USB_EP_CONTROL;
  229. break;
  230. case EP_TYPE_BULK:
  231. wEpRegVal |= USB_EP_BULK;
  232. break;
  233. case EP_TYPE_INTR:
  234. wEpRegVal |= USB_EP_INTERRUPT;
  235. break;
  236. case EP_TYPE_ISOC:
  237. wEpRegVal |= USB_EP_ISOCHRONOUS;
  238. break;
  239. default:
  240. ret = HAL_ERROR;
  241. break;
  242. }
  243. PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_VTRX | USB_EP_VTTX));
  244. PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
  245. if (ep->doublebuffer == 0U)
  246. {
  247. if (ep->is_in != 0U)
  248. {
  249. /*Set the endpoint Transmit buffer address */
  250. PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
  251. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  252. if (ep->type != EP_TYPE_ISOC)
  253. {
  254. /* Configure NAK status for the Endpoint */
  255. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
  256. }
  257. else
  258. {
  259. /* Configure TX Endpoint to disabled state */
  260. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  261. }
  262. }
  263. else
  264. {
  265. /* Set the endpoint Receive buffer address */
  266. PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
  267. /* Set the endpoint Receive buffer counter */
  268. PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
  269. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  270. if (ep->num == 0U)
  271. {
  272. /* Configure VALID status for EP0 */
  273. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
  274. }
  275. else
  276. {
  277. /* Configure NAK status for OUT Endpoint */
  278. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
  279. }
  280. }
  281. }
  282. #if (USE_USB_DOUBLE_BUFFER == 1U)
  283. /* Double Buffer */
  284. else
  285. {
  286. if (ep->type == EP_TYPE_BULK)
  287. {
  288. /* Set bulk endpoint as double buffered */
  289. PCD_SET_BULK_EP_DBUF(USBx, ep->num);
  290. }
  291. else
  292. {
  293. /* Set the ISOC endpoint in double buffer mode */
  294. PCD_CLEAR_EP_KIND(USBx, ep->num);
  295. }
  296. /* Set buffer address for double buffered mode */
  297. PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
  298. if (ep->is_in == 0U)
  299. {
  300. /* Clear the data toggle bits for the endpoint IN/OUT */
  301. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  302. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  303. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
  304. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  305. }
  306. else
  307. {
  308. /* Clear the data toggle bits for the endpoint IN/OUT */
  309. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  310. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  311. if (ep->type != EP_TYPE_ISOC)
  312. {
  313. /* Configure NAK status for the Endpoint */
  314. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
  315. }
  316. else
  317. {
  318. /* Configure TX Endpoint to disabled state */
  319. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  320. }
  321. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
  322. }
  323. }
  324. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  325. return ret;
  326. }
  327. /**
  328. * @brief De-activate and de-initialize an endpoint
  329. * @param USBx Selected device
  330. * @param ep pointer to endpoint structure
  331. * @retval HAL status
  332. */
  333. HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  334. {
  335. if (ep->doublebuffer == 0U)
  336. {
  337. if (ep->is_in != 0U)
  338. {
  339. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  340. /* Configure DISABLE status for the Endpoint */
  341. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  342. }
  343. else
  344. {
  345. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  346. /* Configure DISABLE status for the Endpoint */
  347. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
  348. }
  349. }
  350. #if (USE_USB_DOUBLE_BUFFER == 1U)
  351. /* Double Buffer */
  352. else
  353. {
  354. if (ep->is_in == 0U)
  355. {
  356. /* Clear the data toggle bits for the endpoint IN/OUT*/
  357. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  358. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  359. /* Reset value of the data toggle bits for the endpoint out*/
  360. PCD_TX_DTOG(USBx, ep->num);
  361. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
  362. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  363. }
  364. else
  365. {
  366. /* Clear the data toggle bits for the endpoint IN/OUT*/
  367. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  368. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  369. PCD_RX_DTOG(USBx, ep->num);
  370. /* Configure DISABLE status for the Endpoint*/
  371. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  372. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
  373. }
  374. }
  375. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  376. return HAL_OK;
  377. }
  378. /**
  379. * @brief USB_EPStartXfer setup and starts a transfer over an EP
  380. * @param USBx Selected device
  381. * @param ep pointer to endpoint structure
  382. * @retval HAL status
  383. */
  384. HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  385. {
  386. uint32_t len;
  387. #if (USE_USB_DOUBLE_BUFFER == 1U)
  388. uint16_t pmabuffer;
  389. uint16_t wEPVal;
  390. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  391. /* IN endpoint */
  392. if (ep->is_in == 1U)
  393. {
  394. /*Multi packet transfer*/
  395. if (ep->xfer_len > ep->maxpacket)
  396. {
  397. len = ep->maxpacket;
  398. }
  399. else
  400. {
  401. len = ep->xfer_len;
  402. }
  403. /* configure and validate Tx endpoint */
  404. if (ep->doublebuffer == 0U)
  405. {
  406. USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
  407. PCD_SET_EP_TX_CNT(USBx, ep->num, len);
  408. }
  409. #if (USE_USB_DOUBLE_BUFFER == 1U)
  410. else
  411. {
  412. /* double buffer bulk management */
  413. if (ep->type == EP_TYPE_BULK)
  414. {
  415. if (ep->xfer_len_db > ep->maxpacket)
  416. {
  417. /* enable double buffer */
  418. PCD_SET_BULK_EP_DBUF(USBx, ep->num);
  419. /* each Time to write in PMA xfer_len_db will */
  420. ep->xfer_len_db -= len;
  421. /* Fill the two first buffer in the Buffer0 & Buffer1 */
  422. if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
  423. {
  424. /* Set the Double buffer counter for pmabuffer1 */
  425. PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
  426. pmabuffer = ep->pmaaddr1;
  427. /* Write the user buffer to USB PMA */
  428. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  429. ep->xfer_buff += len;
  430. if (ep->xfer_len_db > ep->maxpacket)
  431. {
  432. ep->xfer_len_db -= len;
  433. }
  434. else
  435. {
  436. len = ep->xfer_len_db;
  437. ep->xfer_len_db = 0U;
  438. }
  439. /* Set the Double buffer counter for pmabuffer0 */
  440. PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
  441. pmabuffer = ep->pmaaddr0;
  442. /* Write the user buffer to USB PMA */
  443. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  444. }
  445. else
  446. {
  447. /* Set the Double buffer counter for pmabuffer0 */
  448. PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
  449. pmabuffer = ep->pmaaddr0;
  450. /* Write the user buffer to USB PMA */
  451. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  452. ep->xfer_buff += len;
  453. if (ep->xfer_len_db > ep->maxpacket)
  454. {
  455. ep->xfer_len_db -= len;
  456. }
  457. else
  458. {
  459. len = ep->xfer_len_db;
  460. ep->xfer_len_db = 0U;
  461. }
  462. /* Set the Double buffer counter for pmabuffer1 */
  463. PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
  464. pmabuffer = ep->pmaaddr1;
  465. /* Write the user buffer to USB PMA */
  466. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  467. }
  468. }
  469. /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
  470. else
  471. {
  472. len = ep->xfer_len_db;
  473. /* disable double buffer mode for Bulk endpoint */
  474. PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num);
  475. /* Set Tx count with nbre of byte to be transmitted */
  476. PCD_SET_EP_TX_CNT(USBx, ep->num, len);
  477. pmabuffer = ep->pmaaddr0;
  478. /* Write the user buffer to USB PMA */
  479. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  480. }
  481. }
  482. else /* manage isochronous double buffer IN mode */
  483. {
  484. /* each Time to write in PMA xfer_len_db will */
  485. ep->xfer_len_db -= len;
  486. /* Fill the data buffer */
  487. if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
  488. {
  489. /* Set the Double buffer counter for pmabuffer1 */
  490. PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
  491. pmabuffer = ep->pmaaddr1;
  492. /* Write the user buffer to USB PMA */
  493. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  494. }
  495. else
  496. {
  497. /* Set the Double buffer counter for pmabuffer0 */
  498. PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
  499. pmabuffer = ep->pmaaddr0;
  500. /* Write the user buffer to USB PMA */
  501. USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
  502. }
  503. }
  504. }
  505. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  506. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
  507. }
  508. else /* OUT endpoint */
  509. {
  510. if (ep->doublebuffer == 0U)
  511. {
  512. /* Multi packet transfer */
  513. if (ep->xfer_len > ep->maxpacket)
  514. {
  515. len = ep->maxpacket;
  516. ep->xfer_len -= len;
  517. }
  518. else
  519. {
  520. len = ep->xfer_len;
  521. ep->xfer_len = 0U;
  522. }
  523. /* configure and validate Rx endpoint */
  524. PCD_SET_EP_RX_CNT(USBx, ep->num, len);
  525. }
  526. #if (USE_USB_DOUBLE_BUFFER == 1U)
  527. else
  528. {
  529. /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
  530. /* Set the Double buffer counter */
  531. if (ep->type == EP_TYPE_BULK)
  532. {
  533. PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
  534. /* Coming from ISR */
  535. if (ep->xfer_count != 0U)
  536. {
  537. /* update last value to check if there is blocking state */
  538. wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num);
  539. /*Blocking State */
  540. if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
  541. (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
  542. {
  543. PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
  544. }
  545. }
  546. }
  547. /* iso out double */
  548. else if (ep->type == EP_TYPE_ISOC)
  549. {
  550. /* Multi packet transfer */
  551. if (ep->xfer_len > ep->maxpacket)
  552. {
  553. len = ep->maxpacket;
  554. ep->xfer_len -= len;
  555. }
  556. else
  557. {
  558. len = ep->xfer_len;
  559. ep->xfer_len = 0U;
  560. }
  561. PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
  562. }
  563. else
  564. {
  565. return HAL_ERROR;
  566. }
  567. }
  568. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  569. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
  570. }
  571. return HAL_OK;
  572. }
  573. /**
  574. * @brief USB_EPSetStall set a stall condition over an EP
  575. * @param USBx Selected device
  576. * @param ep pointer to endpoint structure
  577. * @retval HAL status
  578. */
  579. HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  580. {
  581. if (ep->is_in != 0U)
  582. {
  583. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
  584. }
  585. else
  586. {
  587. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
  588. }
  589. return HAL_OK;
  590. }
  591. /**
  592. * @brief USB_EPClearStall Clear a stall condition over an EP
  593. * @param USBx Selected device
  594. * @param ep pointer to endpoint structure
  595. * @retval HAL status
  596. */
  597. HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  598. {
  599. if (ep->doublebuffer == 0U)
  600. {
  601. if (ep->is_in != 0U)
  602. {
  603. PCD_CLEAR_TX_DTOG(USBx, ep->num);
  604. if (ep->type != EP_TYPE_ISOC)
  605. {
  606. /* Configure NAK status for the Endpoint */
  607. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
  608. }
  609. }
  610. else
  611. {
  612. PCD_CLEAR_RX_DTOG(USBx, ep->num);
  613. /* Configure VALID status for the Endpoint */
  614. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
  615. }
  616. }
  617. return HAL_OK;
  618. }
  619. /**
  620. * @brief USB_EPStoptXfer Stop transfer on an EP
  621. * @param USBx usb device instance
  622. * @param ep pointer to endpoint structure
  623. * @retval HAL status
  624. */
  625. HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep)
  626. {
  627. /* IN endpoint */
  628. if (ep->is_in == 1U)
  629. {
  630. if (ep->doublebuffer == 0U)
  631. {
  632. if (ep->type != EP_TYPE_ISOC)
  633. {
  634. /* Configure NAK status for the Endpoint */
  635. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
  636. }
  637. else
  638. {
  639. /* Configure TX Endpoint to disabled state */
  640. PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
  641. }
  642. }
  643. }
  644. else /* OUT endpoint */
  645. {
  646. if (ep->doublebuffer == 0U)
  647. {
  648. if (ep->type != EP_TYPE_ISOC)
  649. {
  650. /* Configure NAK status for the Endpoint */
  651. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
  652. }
  653. else
  654. {
  655. /* Configure RX Endpoint to disabled state */
  656. PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
  657. }
  658. }
  659. }
  660. return HAL_OK;
  661. }
  662. #endif /* defined (HAL_PCD_MODULE_ENABLED) */
  663. /**
  664. * @brief USB_StopDevice Stop the usb device mode
  665. * @param USBx Selected device
  666. * @retval HAL status
  667. */
  668. HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx)
  669. {
  670. /* disable all interrupts and force USB reset */
  671. USBx->CNTR = USB_CNTR_USBRST;
  672. /* clear interrupt status register */
  673. USBx->ISTR = 0U;
  674. /* switch-off device */
  675. USBx->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN);
  676. return HAL_OK;
  677. }
  678. /**
  679. * @brief USB_SetDevAddress Stop the usb device mode
  680. * @param USBx Selected device
  681. * @param address new device address to be assigned
  682. * This parameter can be a value from 0 to 255
  683. * @retval HAL status
  684. */
  685. HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address)
  686. {
  687. if (address == 0U)
  688. {
  689. /* set device address and enable function */
  690. USBx->DADDR = USB_DADDR_EF;
  691. }
  692. return HAL_OK;
  693. }
  694. /**
  695. * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
  696. * @param USBx Selected device
  697. * @retval HAL status
  698. */
  699. HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx)
  700. {
  701. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  702. USBx->BCDR |= USB_BCDR_DPPU;
  703. return HAL_OK;
  704. }
  705. /**
  706. * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
  707. * @param USBx Selected device
  708. * @retval HAL status
  709. */
  710. HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx)
  711. {
  712. /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
  713. USBx->BCDR &= ~(USB_BCDR_DPPU);
  714. return HAL_OK;
  715. }
  716. /**
  717. * @brief USB_ReadInterrupts return the global USB interrupt status
  718. * @param USBx Selected device
  719. * @retval USB Global Interrupt status
  720. */
  721. uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx)
  722. {
  723. uint32_t tmpreg;
  724. tmpreg = USBx->ISTR;
  725. return tmpreg;
  726. }
  727. /**
  728. * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
  729. * @param USBx Selected device
  730. * @retval HAL status
  731. */
  732. HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx)
  733. {
  734. USBx->CNTR |= USB_CNTR_L2RES;
  735. return HAL_OK;
  736. }
  737. /**
  738. * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
  739. * @param USBx Selected device
  740. * @retval HAL status
  741. */
  742. HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx)
  743. {
  744. USBx->CNTR &= ~USB_CNTR_L2RES;
  745. return HAL_OK;
  746. }
  747. /**
  748. * @brief Copy a buffer from user memory area to packet memory area (PMA)
  749. * @param USBx USB peripheral instance register address.
  750. * @param pbUsrBuf pointer to user memory area.
  751. * @param wPMABufAddr address into PMA.
  752. * @param wNBytes no. of bytes to be copied.
  753. * @retval None
  754. */
  755. void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  756. {
  757. UNUSED(USBx);
  758. uint32_t WrVal;
  759. uint32_t count;
  760. __IO uint32_t *pdwVal;
  761. uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U;
  762. /* Due to the PMA access 32bit only so the last non word data should be processed alone */
  763. uint16_t remaining_bytes = wNBytes % 4U;
  764. uint8_t *pBuf = pbUsrBuf;
  765. /* Check if there is a remaining byte */
  766. if (remaining_bytes != 0U)
  767. {
  768. NbWords--;
  769. }
  770. /* Get the PMA Buffer pointer */
  771. pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr);
  772. /* Write the Calculated Word into the PMA related Buffer */
  773. for (count = NbWords; count != 0U; count--)
  774. {
  775. *pdwVal = __UNALIGNED_UINT32_READ(pBuf);
  776. pdwVal++;
  777. /* Increment pBuf 4 Time as Word Increment */
  778. pBuf++;
  779. pBuf++;
  780. pBuf++;
  781. pBuf++;
  782. }
  783. /* When Number of data is not word aligned, write the remaining Byte */
  784. if (remaining_bytes != 0U)
  785. {
  786. WrVal = 0U;
  787. do
  788. {
  789. WrVal |= (uint32_t)(*(uint8_t *)pBuf) << (8U * count);
  790. count++;
  791. pBuf++;
  792. remaining_bytes--;
  793. } while (remaining_bytes != 0U);
  794. *pdwVal = WrVal;
  795. }
  796. }
  797. /**
  798. * @brief Copy data from packet memory area (PMA) to user memory buffer
  799. * @param USBx USB peripheral instance register address.
  800. * @param pbUsrBuf pointer to user memory area.
  801. * @param wPMABufAddr address into PMA.
  802. * @param wNBytes no. of bytes to be copied.
  803. * @retval None
  804. */
  805. void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  806. {
  807. UNUSED(USBx);
  808. uint32_t count;
  809. uint32_t RdVal;
  810. __IO uint32_t *pdwVal;
  811. uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U;
  812. /*Due to the PMA access 32bit only so the last non word data should be processed alone */
  813. uint16_t remaining_bytes = wNBytes % 4U;
  814. uint8_t *pBuf = pbUsrBuf;
  815. /* Get the PMA Buffer pointer */
  816. pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr);
  817. /* if nbre of byte is not word aligned decrement the nbre of word*/
  818. if (remaining_bytes != 0U)
  819. {
  820. NbWords--;
  821. }
  822. /*Read the Calculated Word From the PMA related Buffer*/
  823. for (count = NbWords; count != 0U; count--)
  824. {
  825. __UNALIGNED_UINT32_WRITE(pBuf, *pdwVal);
  826. pdwVal++;
  827. pBuf++;
  828. pBuf++;
  829. pBuf++;
  830. pBuf++;
  831. }
  832. /*When Number of data is not word aligned, read the remaining byte*/
  833. if (remaining_bytes != 0U)
  834. {
  835. RdVal = *(__IO uint32_t *)pdwVal;
  836. do
  837. {
  838. *(uint8_t *)pBuf = (uint8_t)(RdVal >> (8U * (uint8_t)(count)));
  839. count++;
  840. pBuf++;
  841. remaining_bytes--;
  842. } while (remaining_bytes != 0U);
  843. }
  844. }
  845. /*------------------------------------------------------------------------*/
  846. /* HOST API */
  847. /*------------------------------------------------------------------------*/
  848. /**
  849. * @brief USB_HostInit Initializes the USB DRD controller registers
  850. * for Host mode
  851. * @param USBx Selected device
  852. * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains
  853. * the configuration information for the specified USBx peripheral.
  854. * @retval HAL status
  855. */
  856. HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg)
  857. {
  858. UNUSED(cfg);
  859. /* Clear All Pending Interrupt */
  860. USBx->ISTR = 0U;
  861. /* Disable all interrupts */
  862. USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM |
  863. USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON |
  864. USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM);
  865. /* Clear All Pending Interrupt */
  866. USBx->ISTR = 0U;
  867. /* Enable Global interrupt */
  868. USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM |
  869. USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON |
  870. USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM);
  871. /* Remove Reset */
  872. USBx->CNTR &= ~USB_CNTR_USBRST;
  873. return HAL_OK;
  874. }
  875. /**
  876. * @brief USB_DRD_ResetPort : Reset Host Port
  877. * @param USBx Selected device
  878. * @retval HAL status
  879. * @note (1)The application must wait at least 10 ms
  880. * before clearing the reset bit.
  881. */
  882. HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx)
  883. {
  884. /* Force USB Reset */
  885. USBx->CNTR |= USB_CNTR_USBRST;
  886. HAL_Delay(100);
  887. /* Release USB Reset */
  888. USBx->CNTR &= ~USB_CNTR_USBRST;
  889. HAL_Delay(30);
  890. return HAL_OK;
  891. }
  892. /**
  893. * @brief Return Host Core speed
  894. * @param USBx Selected device
  895. * @retval speed Host speed
  896. * This parameter can be one of these values
  897. * @arg USB_DRD_SPEED_FS Full speed mode
  898. * @arg USB_DRD_SPEED_LS Low speed mode
  899. */
  900. uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx)
  901. {
  902. if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U)
  903. {
  904. return USB_DRD_SPEED_LS;
  905. }
  906. else
  907. {
  908. return USB_DRD_SPEED_FS;
  909. }
  910. }
  911. /**
  912. * @brief Return Host Current Frame number
  913. * @param USBx Selected device
  914. * @retval current frame number
  915. */
  916. uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx)
  917. {
  918. return USBx->FNR & 0x7FFU;
  919. }
  920. /**
  921. * @brief Set the channel Kind (Single/double buffer mode)
  922. * @param USBx Selected device
  923. * @param phy_ch_num Selected device
  924. * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE
  925. * @retval HAL status
  926. */
  927. HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx,
  928. uint8_t phy_ch_num, uint8_t db_state)
  929. {
  930. uint32_t tmp;
  931. if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE))
  932. {
  933. tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK;
  934. }
  935. else
  936. {
  937. tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK;
  938. }
  939. /* Set the device speed in case using HUB FS with device LS */
  940. USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp);
  941. return HAL_OK;
  942. }
  943. /**
  944. * @brief Initialize a host channel
  945. * @param USBx Selected device
  946. * @param phy_ch_num Channel number
  947. * This parameter can be a value from 1 to 15
  948. * @param epnum Endpoint number
  949. * This parameter can be a value from 1 to 15
  950. * @param dev_address Current device address
  951. * This parameter can be a value from 0 to 255
  952. * @param speed Current device speed
  953. * This parameter can be one of these values:
  954. * @arg USB_DRD_SPEED_FULL Full speed mode
  955. * @arg USB_DRD_SPEED_LOW Low speed mode
  956. * @param ep_type Endpoint Type
  957. * This parameter can be one of these values:
  958. * @arg EP_TYPE_CTRL Control type
  959. * @arg EP_TYPE_ISOC Isochronous type
  960. * @arg EP_TYPE_BULK Bulk type
  961. * @arg EP_TYPE_INTR Interrupt type
  962. * @param mps Max Packet Size
  963. * This parameter can be a value from 0 to 32K
  964. * @retval HAL state
  965. */
  966. HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num,
  967. uint8_t epnum, uint8_t dev_address, uint8_t speed,
  968. uint8_t ep_type, uint16_t mps)
  969. {
  970. HAL_StatusTypeDef ret = HAL_OK;
  971. uint32_t wChRegVal;
  972. uint32_t HostCoreSpeed;
  973. UNUSED(mps);
  974. wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK;
  975. /* initialize host Channel */
  976. switch (ep_type)
  977. {
  978. case EP_TYPE_CTRL:
  979. wChRegVal |= USB_EP_CONTROL;
  980. break;
  981. case EP_TYPE_BULK:
  982. wChRegVal |= USB_EP_BULK;
  983. break;
  984. case EP_TYPE_INTR:
  985. wChRegVal |= USB_EP_INTERRUPT;
  986. break;
  987. case EP_TYPE_ISOC:
  988. wChRegVal |= USB_EP_ISOCHRONOUS;
  989. break;
  990. default:
  991. ret = HAL_ERROR;
  992. break;
  993. }
  994. wChRegVal &= ~USB_CHEP_DEVADDR;
  995. wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) |
  996. ((uint32_t)epnum & 0x0FU));
  997. /* Get Host core Speed */
  998. HostCoreSpeed = USB_GetHostSpeed(USBx);
  999. /* Set the device speed in case using HUB FS with device LS */
  1000. if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS))
  1001. {
  1002. wChRegVal |= USB_CHEP_LSEP;
  1003. }
  1004. /* Set the dev_address & ep type */
  1005. USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX));
  1006. return ret;
  1007. }
  1008. /**
  1009. * @brief Start a transfer over a host channel
  1010. * @param USBx Selected device
  1011. * @param hc pointer to host channel structure
  1012. * @retval HAL state
  1013. */
  1014. HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc)
  1015. {
  1016. uint32_t len;
  1017. uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
  1018. #if (USE_USB_DOUBLE_BUFFER == 1U)
  1019. uint32_t ch_reg = USB_DRD_GET_CHEP(USBx, phy_ch_num);
  1020. #endif /* USE_USB_DOUBLE_BUFFER */
  1021. if (hc->ch_dir == CH_IN_DIR) /* In Channel */
  1022. {
  1023. /* Multi packet transfer */
  1024. if (hc->xfer_len > hc->max_packet)
  1025. {
  1026. len = hc->max_packet;
  1027. }
  1028. else
  1029. {
  1030. len = hc->xfer_len;
  1031. }
  1032. if (hc->doublebuffer == 0U)
  1033. {
  1034. /* Set RX buffer count */
  1035. USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len);
  1036. }
  1037. #if (USE_USB_DOUBLE_BUFFER == 1U)
  1038. else if (hc->ep_type == EP_TYPE_BULK)
  1039. {
  1040. /* Double buffer activated */
  1041. if ((hc->xfer_len > hc->max_packet))
  1042. {
  1043. (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE);
  1044. /*Set the Double buffer counter*/
  1045. USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len);
  1046. USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len);
  1047. }
  1048. else /* switch to single buffer mode */
  1049. {
  1050. (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE);
  1051. /* Set RX buffer count */
  1052. USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len);
  1053. }
  1054. }
  1055. else /* isochronous */
  1056. {
  1057. /* Set the Double buffer counter */
  1058. USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len);
  1059. USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len);
  1060. }
  1061. #endif /* USE_USB_DOUBLE_BUFFER */
  1062. /*Enable host channel */
  1063. USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CHEP_RX_STRX);
  1064. }
  1065. else /* Out Channel */
  1066. {
  1067. /* Multi packet transfer*/
  1068. if (hc->xfer_len > hc->max_packet)
  1069. {
  1070. len = hc->max_packet;
  1071. }
  1072. else
  1073. {
  1074. len = hc->xfer_len;
  1075. }
  1076. /* configure and validate Tx endpoint */
  1077. if (hc->doublebuffer == 0U)
  1078. {
  1079. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len);
  1080. USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len);
  1081. /*SET PID SETUP */
  1082. if ((hc->data_pid) == HC_PID_SETUP)
  1083. {
  1084. USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num);
  1085. }
  1086. }
  1087. #if (USE_USB_DOUBLE_BUFFER == 1U)
  1088. else if (hc->ep_type == EP_TYPE_BULK)
  1089. {
  1090. (void)USB_HC_BULK_DB_StartXfer(USBx, hc, ch_reg, &len);
  1091. }
  1092. else
  1093. {
  1094. (void)USB_HC_ISO_DB_StartXfer(USBx, hc, len);
  1095. }
  1096. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  1097. /* Enable host channel */
  1098. USB_DRD_SET_CHEP_TX_STATUS(USBx, hc->phy_ch_num, USB_CH_TX_VALID);
  1099. }
  1100. return HAL_OK;
  1101. }
  1102. #if (USE_USB_DOUBLE_BUFFER == 1U)
  1103. /**
  1104. * @brief Start Transfer of Channel isochronous out double buffer
  1105. * @param USBx Selected device
  1106. * @param hc_num Host Channel number
  1107. * This parameter can be a value from 1 to 15
  1108. * @param len Transfer Length
  1109. * @retval HAL state
  1110. */
  1111. static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx,
  1112. USB_DRD_HCTypeDef *hc,
  1113. uint32_t len)
  1114. {
  1115. uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
  1116. /* check the DTOG_TX to determine in which buffer we should write */
  1117. if ((USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_DTOG_TX) != 0U)
  1118. {
  1119. USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, len);
  1120. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)len);
  1121. }
  1122. else
  1123. {
  1124. /* DTOGTX=0 */
  1125. /* Set the Double buffer counter for pmabuffer0 */
  1126. USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, len);
  1127. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)len);
  1128. }
  1129. return HAL_OK;
  1130. }
  1131. /**
  1132. * @brief Start Transfer of Channel bulk out double buffer
  1133. * @param USBx Selected device
  1134. * @param hc_num Host Channel number
  1135. * This parameter can be a value from 1 to 15
  1136. * @param ch_reg snapshot of the CHEPR register
  1137. * @param len Transfer Length
  1138. * @retval HAL state
  1139. */
  1140. static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx,
  1141. USB_DRD_HCTypeDef *hc,
  1142. uint32_t ch_reg,
  1143. uint32_t *len)
  1144. {
  1145. uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num;
  1146. /* -Double Buffer Mangement- */
  1147. if (hc->xfer_len_db > hc->max_packet)
  1148. {
  1149. /* enable double buffer mode */
  1150. (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE);
  1151. *len = hc->max_packet;
  1152. hc->xfer_len_db -= *len;
  1153. /* Prepare two buffer before enabling host */
  1154. if ((ch_reg & USB_CH_DTOG_TX) == 0U)
  1155. {
  1156. /* Write Buffer0 */
  1157. USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
  1158. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
  1159. }
  1160. else
  1161. {
  1162. /* Write Buffer1 */
  1163. USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
  1164. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len);
  1165. }
  1166. hc->xfer_buff += *len;
  1167. /* Multi packet transfer */
  1168. if (hc->xfer_len_db > hc->max_packet)
  1169. {
  1170. hc->xfer_len_db -= *len;
  1171. }
  1172. else
  1173. {
  1174. *len = hc->xfer_len_db;
  1175. hc->xfer_len_db = 0U;
  1176. }
  1177. if ((ch_reg & USB_CH_DTOG_TX) == 0U)
  1178. {
  1179. /* Write Buffer1 */
  1180. USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
  1181. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len);
  1182. }
  1183. else
  1184. {
  1185. /* Write Buffer0 */
  1186. USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len);
  1187. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
  1188. }
  1189. }
  1190. else
  1191. {
  1192. /* Disable bulk double buffer mode */
  1193. (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE);
  1194. USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len);
  1195. USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)*len);
  1196. }
  1197. return HAL_OK;
  1198. }
  1199. #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
  1200. /**
  1201. * @brief Halt a host channel in
  1202. * @param USBx Selected device
  1203. * @param hc_num Host Channel number
  1204. * This parameter can be a value from 1 to 15
  1205. * @retval HAL state
  1206. */
  1207. HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
  1208. {
  1209. /* Set disable to Channel */
  1210. USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS);
  1211. return HAL_OK;
  1212. }
  1213. /**
  1214. * @brief Halt a host channel out
  1215. * @param USBx Selected device
  1216. * @param hc_num Host Channel number
  1217. * This parameter can be a value from 1 to 15
  1218. * @retval HAL state
  1219. */
  1220. HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
  1221. {
  1222. /* Set disable to Channel */
  1223. USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS);
  1224. return HAL_OK;
  1225. }
  1226. /**
  1227. * @brief Stop Host Core
  1228. * @param USBx Selected device
  1229. * @retval HAL state
  1230. */
  1231. HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx)
  1232. {
  1233. USBx->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ |
  1234. USB_ISTR_ESOF | USB_ISTR_SOF |
  1235. USB_ISTR_RESET | USB_ISTR_DCON |
  1236. USB_ISTR_SUSP | USB_ISTR_WKUP |
  1237. USB_ISTR_ERR | USB_ISTR_PMAOVR |
  1238. USB_ISTR_CTR);
  1239. /* Set PowerDown */
  1240. USBx->CNTR |= USB_CNTR_PDWN;
  1241. /* Force a Reset */
  1242. USBx->CNTR |= USB_CNTR_USBRST;
  1243. return HAL_OK;
  1244. }
  1245. /**
  1246. * @}
  1247. */
  1248. /**
  1249. * @}
  1250. */
  1251. #endif /* defined (USB_DRD_FS) */
  1252. #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
  1253. /**
  1254. * @}
  1255. */