stm32g4xx_ll_pwr.h 50 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32g4xx_ll_pwr.h
  4. * @author MCD Application Team
  5. * @brief Header file of PWR LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2019 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32G4xx_LL_PWR_H
  20. #define STM32G4xx_LL_PWR_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32g4xx.h"
  26. /** @addtogroup STM32G4xx_LL_Driver
  27. * @{
  28. */
  29. #if defined(PWR)
  30. /** @defgroup PWR_LL PWR
  31. * @{
  32. */
  33. /* Private types -------------------------------------------------------------*/
  34. /* Private variables ---------------------------------------------------------*/
  35. /* Private constants ---------------------------------------------------------*/
  36. /* Private macros ------------------------------------------------------------*/
  37. /* Exported types ------------------------------------------------------------*/
  38. /* Exported constants --------------------------------------------------------*/
  39. /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
  40. * @{
  41. */
  42. /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
  43. * @brief Flags defines which can be used with LL_PWR_WriteReg function
  44. * @{
  45. */
  46. #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
  47. #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
  48. #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
  49. #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
  50. #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
  51. #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
  52. #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
  53. /**
  54. * @}
  55. */
  56. /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
  57. * @brief Flags defines which can be used with LL_PWR_ReadReg function
  58. * @{
  59. */
  60. #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
  61. #define LL_PWR_SR1_SBF PWR_SR1_SBF
  62. #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
  63. #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
  64. #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
  65. #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
  66. #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
  67. #if defined(PWR_SR2_PVMO4)
  68. #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
  69. #endif /* PWR_SR2_PVMO4 */
  70. #if defined(PWR_SR2_PVMO3)
  71. #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
  72. #endif /* PWR_SR2_PVMO3 */
  73. #if defined(PWR_SR2_PVMO2)
  74. #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
  75. #endif /* PWR_SR2_PVMO2 */
  76. #if defined(PWR_SR2_PVMO1)
  77. #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
  78. #endif /* PWR_SR2_PVMO1 */
  79. #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
  80. #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
  81. #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
  82. #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
  83. /**
  84. * @}
  85. */
  86. /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
  87. * @{
  88. */
  89. #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
  90. #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
  91. /**
  92. * @}
  93. */
  94. /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
  95. * @{
  96. */
  97. #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
  98. #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
  99. #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
  100. #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
  101. /**
  102. * @}
  103. */
  104. /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
  105. * @{
  106. */
  107. #if defined(PWR_CR2_PVME1)
  108. #define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
  109. #endif
  110. #if defined(PWR_CR2_PVME2)
  111. #define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
  112. #endif
  113. #if defined(PWR_CR2_PVME3)
  114. #define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
  115. #endif
  116. #if defined(PWR_CR2_PVME4)
  117. #define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
  118. #endif
  119. /**
  120. * @}
  121. */
  122. /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
  123. * @{
  124. */
  125. #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
  126. #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
  127. #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
  128. #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
  129. #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
  130. #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
  131. #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
  132. #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
  133. /**
  134. * @}
  135. */
  136. /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
  137. * @{
  138. */
  139. #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
  140. #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
  141. #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
  142. #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
  143. #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
  144. /**
  145. * @}
  146. */
  147. /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
  148. * @{
  149. */
  150. #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
  151. #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
  152. /**
  153. * @}
  154. */
  155. /** @defgroup PWR_LL_EC_GPIO GPIO
  156. * @{
  157. */
  158. #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
  159. #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
  160. #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
  161. #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
  162. #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
  163. #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
  164. #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
  165. /**
  166. * @}
  167. */
  168. /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
  169. * @{
  170. */
  171. #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
  172. #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
  173. #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
  174. #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
  175. #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
  176. #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
  177. #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
  178. #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
  179. #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
  180. #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
  181. #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
  182. #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
  183. #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
  184. #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
  185. #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
  186. #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
  187. /**
  188. * @}
  189. */
  190. /**
  191. * @}
  192. */
  193. /* Exported macro ------------------------------------------------------------*/
  194. /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
  195. * @{
  196. */
  197. /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
  198. * @{
  199. */
  200. /**
  201. * @brief Write a value in PWR register
  202. * @param __REG__ Register to be written
  203. * @param __VALUE__ Value to be written in the register
  204. * @retval None
  205. */
  206. #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
  207. /**
  208. * @brief Read a value in PWR register
  209. * @param __REG__ Register to be read
  210. * @retval Register value
  211. */
  212. #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
  213. /**
  214. * @}
  215. */
  216. /**
  217. * @}
  218. */
  219. /* Exported functions --------------------------------------------------------*/
  220. /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
  221. * @{
  222. */
  223. /** @defgroup PWR_LL_EF_Configuration Configuration
  224. * @{
  225. */
  226. /**
  227. * @brief Switch the regulator from main mode to low-power mode
  228. * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
  229. * @retval None
  230. */
  231. __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
  232. {
  233. SET_BIT(PWR->CR1, PWR_CR1_LPR);
  234. }
  235. /**
  236. * @brief Switch the regulator from low-power mode to main mode
  237. * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
  238. * @retval None
  239. */
  240. __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
  241. {
  242. CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
  243. }
  244. /**
  245. * @brief Check if the regulator is in low-power mode
  246. * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
  247. * @retval State of bit (1 or 0).
  248. */
  249. __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
  250. {
  251. uint32_t temp;
  252. temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
  253. return ((temp == (PWR_CR1_LPR))?1U:0U);
  254. }
  255. /**
  256. * @brief Switch from run main mode to run low-power mode.
  257. * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
  258. * @retval None
  259. */
  260. __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
  261. {
  262. LL_PWR_EnableLowPowerRunMode();
  263. }
  264. /**
  265. * @brief Switch from run main mode to low-power mode.
  266. * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
  267. * @retval None
  268. */
  269. __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
  270. {
  271. LL_PWR_DisableLowPowerRunMode();
  272. }
  273. /**
  274. * @brief Set the main internal regulator output voltage
  275. * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
  276. * @param VoltageScaling This parameter can be one of the following values:
  277. * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
  278. * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
  279. * @retval None
  280. */
  281. __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
  282. {
  283. MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
  284. }
  285. /**
  286. * @brief Get the main internal regulator output voltage
  287. * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
  288. * @retval Returned value can be one of the following values:
  289. * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
  290. * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
  291. */
  292. __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
  293. {
  294. return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
  295. }
  296. #if defined(PWR_CR5_R1MODE)
  297. /**
  298. * @brief Enable main regulator voltage range 1 boost mode
  299. * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
  300. * @retval None
  301. */
  302. __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
  303. {
  304. CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
  305. }
  306. /**
  307. * @brief Disable main regulator voltage range 1 boost mode
  308. * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
  309. * @retval None
  310. */
  311. __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
  312. {
  313. SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
  314. }
  315. /**
  316. * @brief Check if the main regulator voltage range 1 boost mode is enabled
  317. * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
  318. * @retval Inverted state of bit (0 or 1).
  319. */
  320. __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
  321. {
  322. uint32_t temp;
  323. temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
  324. return ((temp == (0U))?1U:0U);
  325. }
  326. #endif /* PWR_CR5_R1MODE */
  327. /**
  328. * @brief Enable access to the backup domain
  329. * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
  330. * @retval None
  331. */
  332. __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
  333. {
  334. SET_BIT(PWR->CR1, PWR_CR1_DBP);
  335. }
  336. /**
  337. * @brief Disable access to the backup domain
  338. * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
  339. * @retval None
  340. */
  341. __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
  342. {
  343. CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
  344. }
  345. /**
  346. * @brief Check if the backup domain is enabled
  347. * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
  348. * @retval State of bit (1 or 0).
  349. */
  350. __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
  351. {
  352. uint32_t temp;
  353. temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
  354. return ((temp == (PWR_CR1_DBP))?1U:0U);
  355. }
  356. /**
  357. * @brief Set Low-Power mode
  358. * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
  359. * @param LowPowerMode This parameter can be one of the following values:
  360. * @arg @ref LL_PWR_MODE_STOP0
  361. * @arg @ref LL_PWR_MODE_STOP1
  362. * @arg @ref LL_PWR_MODE_STANDBY
  363. * @arg @ref LL_PWR_MODE_SHUTDOWN
  364. * @retval None
  365. */
  366. __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
  367. {
  368. MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
  369. }
  370. /**
  371. * @brief Get Low-Power mode
  372. * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
  373. * @retval Returned value can be one of the following values:
  374. * @arg @ref LL_PWR_MODE_STOP0
  375. * @arg @ref LL_PWR_MODE_STOP1
  376. * @arg @ref LL_PWR_MODE_STANDBY
  377. * @arg @ref LL_PWR_MODE_SHUTDOWN
  378. */
  379. __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
  380. {
  381. return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
  382. }
  383. #if defined(PWR_CR3_UCPD_STDBY)
  384. /**
  385. * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
  386. * @note This function must be called just before entering Standby mode.
  387. * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
  388. * @retval None
  389. */
  390. __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
  391. {
  392. SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
  393. }
  394. /**
  395. * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
  396. * @note This function must be called after exiting Standby mode and before any
  397. * UCPD configuration update.
  398. * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
  399. * @retval None
  400. */
  401. __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
  402. {
  403. CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
  404. }
  405. /**
  406. * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
  407. * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
  408. * @retval State of bit (1 or 0).
  409. */
  410. __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
  411. {
  412. return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
  413. }
  414. #endif /* PWR_CR3_UCPD_STDBY */
  415. #if defined(PWR_CR3_UCPD_DBDIS)
  416. /**
  417. * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
  418. * on UCPD CC1 and CC2 pins.
  419. * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
  420. * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
  421. * to disable it in all cases, either to stop this pull-down or to hand over
  422. * control to the UCPD (which should therefore be initialized before doing the disable).
  423. * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
  424. * @retval None
  425. */
  426. __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
  427. {
  428. CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
  429. }
  430. /**
  431. * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
  432. * on UCPD CC1 and CC2 pins.
  433. * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
  434. * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
  435. * to disable it in all cases, either to stop this pull-down or to hand over
  436. * control to the UCPD (which should therefore be initialized before doing the disable).
  437. * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
  438. * @retval None
  439. */
  440. __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
  441. {
  442. SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
  443. }
  444. /**
  445. * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
  446. * on UCPD CC1 and CC2 pins.
  447. * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
  448. * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
  449. * to disable it in all cases, either to stop this pull-down or to hand over
  450. * control to the UCPD (which should therefore be initialized before doing the disable).
  451. * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
  452. * @retval State of feature (1 : enabled; 0 : disabled).
  453. */
  454. __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
  455. {
  456. return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
  457. }
  458. #endif /* PWR_CR3_UCPD_DBDIS */
  459. #if defined(PWR_CR2_USV)
  460. /**
  461. * @brief Enable VDDUSB supply
  462. * @rmtoll CR2 USV LL_PWR_EnableVddUSB
  463. * @retval None
  464. */
  465. __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
  466. {
  467. SET_BIT(PWR->CR2, PWR_CR2_USV);
  468. }
  469. /**
  470. * @brief Disable VDDUSB supply
  471. * @rmtoll CR2 USV LL_PWR_DisableVddUSB
  472. * @retval None
  473. */
  474. __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
  475. {
  476. CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
  477. }
  478. /**
  479. * @brief Check if VDDUSB supply is enabled
  480. * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
  481. * @retval State of bit (1 or 0).
  482. */
  483. __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
  484. {
  485. uint32_t temp;
  486. temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
  487. return ((temp == (PWR_CR2_USV))?1U:0U);
  488. }
  489. #endif
  490. #if defined(PWR_CR2_IOSV)
  491. /**
  492. * @brief Enable VDDIO2 supply
  493. * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
  494. * @retval None
  495. */
  496. __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
  497. {
  498. SET_BIT(PWR->CR2, PWR_CR2_IOSV);
  499. }
  500. /**
  501. * @brief Disable VDDIO2 supply
  502. * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
  503. * @retval None
  504. */
  505. __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
  506. {
  507. CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
  508. }
  509. /**
  510. * @brief Check if VDDIO2 supply is enabled
  511. * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
  512. * @retval State of bit (1 or 0).
  513. */
  514. __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
  515. {
  516. uint32_t temp;
  517. temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
  518. return ((temp == (PWR_CR2_IOSV))?1U:0U);
  519. }
  520. #endif
  521. /**
  522. * @brief Enable the Power Voltage Monitoring on a peripheral
  523. * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
  524. * CR2 PVME2 LL_PWR_EnablePVM\n
  525. * CR2 PVME3 LL_PWR_EnablePVM\n
  526. * CR2 PVME4 LL_PWR_EnablePVM
  527. * @param PeriphVoltage This parameter can be one of the following values:
  528. * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
  529. * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
  530. * @arg @ref LL_PWR_PVM_VDDA_ADC
  531. * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
  532. *
  533. * (*) value not defined in all devices
  534. * @retval None
  535. */
  536. __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
  537. {
  538. SET_BIT(PWR->CR2, PeriphVoltage);
  539. }
  540. /**
  541. * @brief Disable the Power Voltage Monitoring on a peripheral
  542. * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
  543. * CR2 PVME2 LL_PWR_DisablePVM\n
  544. * CR2 PVME3 LL_PWR_DisablePVM\n
  545. * CR2 PVME4 LL_PWR_DisablePVM
  546. * @param PeriphVoltage This parameter can be one of the following values:
  547. * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
  548. * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
  549. * @arg @ref LL_PWR_PVM_VDDA_ADC
  550. * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
  551. *
  552. * (*) value not defined in all devices
  553. * @retval None
  554. */
  555. __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
  556. {
  557. CLEAR_BIT(PWR->CR2, PeriphVoltage);
  558. }
  559. /**
  560. * @brief Check if Power Voltage Monitoring is enabled on a peripheral
  561. * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
  562. * CR2 PVME2 LL_PWR_IsEnabledPVM\n
  563. * CR2 PVME3 LL_PWR_IsEnabledPVM\n
  564. * CR2 PVME4 LL_PWR_IsEnabledPVM
  565. * @param PeriphVoltage This parameter can be one of the following values:
  566. * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
  567. * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
  568. * @arg @ref LL_PWR_PVM_VDDA_ADC
  569. * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
  570. *
  571. * (*) value not defined in all devices
  572. * @retval State of bit (1 or 0).
  573. */
  574. __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
  575. {
  576. uint32_t temp;
  577. temp = READ_BIT(PWR->CR2, PeriphVoltage);
  578. return ((temp == (PeriphVoltage))?1U:0U);
  579. }
  580. /**
  581. * @brief Configure the voltage threshold detected by the Power Voltage Detector
  582. * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
  583. * @param PVDLevel This parameter can be one of the following values:
  584. * @arg @ref LL_PWR_PVDLEVEL_0
  585. * @arg @ref LL_PWR_PVDLEVEL_1
  586. * @arg @ref LL_PWR_PVDLEVEL_2
  587. * @arg @ref LL_PWR_PVDLEVEL_3
  588. * @arg @ref LL_PWR_PVDLEVEL_4
  589. * @arg @ref LL_PWR_PVDLEVEL_5
  590. * @arg @ref LL_PWR_PVDLEVEL_6
  591. * @arg @ref LL_PWR_PVDLEVEL_7
  592. * @retval None
  593. */
  594. __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
  595. {
  596. MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
  597. }
  598. /**
  599. * @brief Get the voltage threshold detection
  600. * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
  601. * @retval Returned value can be one of the following values:
  602. * @arg @ref LL_PWR_PVDLEVEL_0
  603. * @arg @ref LL_PWR_PVDLEVEL_1
  604. * @arg @ref LL_PWR_PVDLEVEL_2
  605. * @arg @ref LL_PWR_PVDLEVEL_3
  606. * @arg @ref LL_PWR_PVDLEVEL_4
  607. * @arg @ref LL_PWR_PVDLEVEL_5
  608. * @arg @ref LL_PWR_PVDLEVEL_6
  609. * @arg @ref LL_PWR_PVDLEVEL_7
  610. */
  611. __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
  612. {
  613. return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
  614. }
  615. /**
  616. * @brief Enable Power Voltage Detector
  617. * @rmtoll CR2 PVDE LL_PWR_EnablePVD
  618. * @retval None
  619. */
  620. __STATIC_INLINE void LL_PWR_EnablePVD(void)
  621. {
  622. SET_BIT(PWR->CR2, PWR_CR2_PVDE);
  623. }
  624. /**
  625. * @brief Disable Power Voltage Detector
  626. * @rmtoll CR2 PVDE LL_PWR_DisablePVD
  627. * @retval None
  628. */
  629. __STATIC_INLINE void LL_PWR_DisablePVD(void)
  630. {
  631. CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
  632. }
  633. /**
  634. * @brief Check if Power Voltage Detector is enabled
  635. * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
  636. * @retval State of bit (1 or 0).
  637. */
  638. __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
  639. {
  640. uint32_t temp;
  641. temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
  642. return ((temp == (PWR_CR2_PVDE))?1U:0U);
  643. }
  644. /**
  645. * @brief Enable Internal Wake-up line
  646. * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
  647. * @retval None
  648. */
  649. __STATIC_INLINE void LL_PWR_EnableInternWU(void)
  650. {
  651. SET_BIT(PWR->CR3, PWR_CR3_EIWF);
  652. }
  653. /**
  654. * @brief Disable Internal Wake-up line
  655. * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
  656. * @retval None
  657. */
  658. __STATIC_INLINE void LL_PWR_DisableInternWU(void)
  659. {
  660. CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
  661. }
  662. /**
  663. * @brief Check if Internal Wake-up line is enabled
  664. * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
  665. * @retval State of bit (1 or 0).
  666. */
  667. __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
  668. {
  669. return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
  670. }
  671. /**
  672. * @brief Enable pull-up and pull-down configuration
  673. * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
  674. * @retval None
  675. */
  676. __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
  677. {
  678. SET_BIT(PWR->CR3, PWR_CR3_APC);
  679. }
  680. /**
  681. * @brief Disable pull-up and pull-down configuration
  682. * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
  683. * @retval None
  684. */
  685. __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
  686. {
  687. CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
  688. }
  689. /**
  690. * @brief Check if pull-up and pull-down configuration is enabled
  691. * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
  692. * @retval State of bit (1 or 0).
  693. */
  694. __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
  695. {
  696. uint32_t temp;
  697. temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
  698. return ((temp == (PWR_CR3_APC))?1U:0U);
  699. }
  700. #if defined(SRAM2_BASE)
  701. /**
  702. * @brief Enable SRAM2 content retention in Standby mode
  703. * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
  704. * @retval None
  705. */
  706. __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
  707. {
  708. SET_BIT(PWR->CR3, PWR_CR3_RRS);
  709. }
  710. /**
  711. * @brief Disable SRAM2 content retention in Standby mode
  712. * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
  713. * @retval None
  714. */
  715. __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
  716. {
  717. CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
  718. }
  719. /**
  720. * @brief Check if SRAM2 content retention in Standby mode is enabled
  721. * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
  722. * @retval State of bit (1 or 0).
  723. */
  724. __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
  725. {
  726. uint32_t temp;
  727. temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
  728. return ((temp == (PWR_CR3_RRS))?1U:0U);
  729. }
  730. #endif /* SRAM2_BASE */
  731. /**
  732. * @brief Enable the WakeUp PINx functionality
  733. * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
  734. * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
  735. * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
  736. * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
  737. * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
  738. * @param WakeUpPin This parameter can be one of the following values:
  739. * @arg @ref LL_PWR_WAKEUP_PIN1
  740. * @arg @ref LL_PWR_WAKEUP_PIN2
  741. * @arg @ref LL_PWR_WAKEUP_PIN3
  742. * @arg @ref LL_PWR_WAKEUP_PIN4
  743. * @arg @ref LL_PWR_WAKEUP_PIN5
  744. * @retval None
  745. */
  746. __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
  747. {
  748. SET_BIT(PWR->CR3, WakeUpPin);
  749. }
  750. /**
  751. * @brief Disable the WakeUp PINx functionality
  752. * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
  753. * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
  754. * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
  755. * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
  756. * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
  757. * @param WakeUpPin This parameter can be one of the following values:
  758. * @arg @ref LL_PWR_WAKEUP_PIN1
  759. * @arg @ref LL_PWR_WAKEUP_PIN2
  760. * @arg @ref LL_PWR_WAKEUP_PIN3
  761. * @arg @ref LL_PWR_WAKEUP_PIN4
  762. * @arg @ref LL_PWR_WAKEUP_PIN5
  763. * @retval None
  764. */
  765. __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
  766. {
  767. CLEAR_BIT(PWR->CR3, WakeUpPin);
  768. }
  769. /**
  770. * @brief Check if the WakeUp PINx functionality is enabled
  771. * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
  772. * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
  773. * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
  774. * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
  775. * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
  776. * @param WakeUpPin This parameter can be one of the following values:
  777. * @arg @ref LL_PWR_WAKEUP_PIN1
  778. * @arg @ref LL_PWR_WAKEUP_PIN2
  779. * @arg @ref LL_PWR_WAKEUP_PIN3
  780. * @arg @ref LL_PWR_WAKEUP_PIN4
  781. * @arg @ref LL_PWR_WAKEUP_PIN5
  782. * @retval State of bit (1 or 0).
  783. */
  784. __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
  785. {
  786. uint32_t temp;
  787. temp = READ_BIT(PWR->CR3, WakeUpPin);
  788. return ((temp == (WakeUpPin))?1U:0U);
  789. }
  790. /**
  791. * @brief Set the resistor impedance
  792. * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
  793. * @param Resistor This parameter can be one of the following values:
  794. * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
  795. * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
  796. * @retval None
  797. */
  798. __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
  799. {
  800. MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
  801. }
  802. /**
  803. * @brief Get the resistor impedance
  804. * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
  805. * @retval Returned value can be one of the following values:
  806. * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
  807. * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
  808. */
  809. __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
  810. {
  811. return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
  812. }
  813. /**
  814. * @brief Enable battery charging
  815. * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
  816. * @retval None
  817. */
  818. __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
  819. {
  820. SET_BIT(PWR->CR4, PWR_CR4_VBE);
  821. }
  822. /**
  823. * @brief Disable battery charging
  824. * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
  825. * @retval None
  826. */
  827. __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
  828. {
  829. CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
  830. }
  831. /**
  832. * @brief Check if battery charging is enabled
  833. * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
  834. * @retval State of bit (1 or 0).
  835. */
  836. __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
  837. {
  838. uint32_t temp;
  839. temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
  840. return ((temp == (PWR_CR4_VBE))?1U:0U);
  841. }
  842. /**
  843. * @brief Set the Wake-Up pin polarity low for the event detection
  844. * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
  845. * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
  846. * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
  847. * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
  848. * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
  849. * @param WakeUpPin This parameter can be one of the following values:
  850. * @arg @ref LL_PWR_WAKEUP_PIN1
  851. * @arg @ref LL_PWR_WAKEUP_PIN2
  852. * @arg @ref LL_PWR_WAKEUP_PIN3
  853. * @arg @ref LL_PWR_WAKEUP_PIN4
  854. * @arg @ref LL_PWR_WAKEUP_PIN5
  855. * @retval None
  856. */
  857. __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
  858. {
  859. SET_BIT(PWR->CR4, WakeUpPin);
  860. }
  861. /**
  862. * @brief Set the Wake-Up pin polarity high for the event detection
  863. * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
  864. * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
  865. * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
  866. * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
  867. * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
  868. * @param WakeUpPin This parameter can be one of the following values:
  869. * @arg @ref LL_PWR_WAKEUP_PIN1
  870. * @arg @ref LL_PWR_WAKEUP_PIN2
  871. * @arg @ref LL_PWR_WAKEUP_PIN3
  872. * @arg @ref LL_PWR_WAKEUP_PIN4
  873. * @arg @ref LL_PWR_WAKEUP_PIN5
  874. * @retval None
  875. */
  876. __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
  877. {
  878. CLEAR_BIT(PWR->CR4, WakeUpPin);
  879. }
  880. /**
  881. * @brief Get the Wake-Up pin polarity for the event detection
  882. * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
  883. * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
  884. * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
  885. * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
  886. * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
  887. * @param WakeUpPin This parameter can be one of the following values:
  888. * @arg @ref LL_PWR_WAKEUP_PIN1
  889. * @arg @ref LL_PWR_WAKEUP_PIN2
  890. * @arg @ref LL_PWR_WAKEUP_PIN3
  891. * @arg @ref LL_PWR_WAKEUP_PIN4
  892. * @arg @ref LL_PWR_WAKEUP_PIN5
  893. * @retval State of bit (1 or 0).
  894. */
  895. __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
  896. {
  897. uint32_t temp;
  898. temp = READ_BIT(PWR->CR4, WakeUpPin);
  899. return ((temp == (WakeUpPin))?1U:0U);
  900. }
  901. /**
  902. * @brief Enable GPIO pull-up state in Standby and Shutdown modes
  903. * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
  904. * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
  905. * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
  906. * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
  907. * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
  908. * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
  909. * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
  910. * @param GPIO This parameter can be one of the following values:
  911. * @arg @ref LL_PWR_GPIO_A
  912. * @arg @ref LL_PWR_GPIO_B
  913. * @arg @ref LL_PWR_GPIO_C
  914. * @arg @ref LL_PWR_GPIO_D
  915. * @arg @ref LL_PWR_GPIO_E
  916. * @arg @ref LL_PWR_GPIO_F
  917. * @arg @ref LL_PWR_GPIO_G
  918. *
  919. * (*) value not defined in all devices
  920. * @param GPIONumber This parameter can be one of the following values:
  921. * @arg @ref LL_PWR_GPIO_BIT_0
  922. * @arg @ref LL_PWR_GPIO_BIT_1
  923. * @arg @ref LL_PWR_GPIO_BIT_2
  924. * @arg @ref LL_PWR_GPIO_BIT_3
  925. * @arg @ref LL_PWR_GPIO_BIT_4
  926. * @arg @ref LL_PWR_GPIO_BIT_5
  927. * @arg @ref LL_PWR_GPIO_BIT_6
  928. * @arg @ref LL_PWR_GPIO_BIT_7
  929. * @arg @ref LL_PWR_GPIO_BIT_8
  930. * @arg @ref LL_PWR_GPIO_BIT_9
  931. * @arg @ref LL_PWR_GPIO_BIT_10
  932. * @arg @ref LL_PWR_GPIO_BIT_11
  933. * @arg @ref LL_PWR_GPIO_BIT_12
  934. * @arg @ref LL_PWR_GPIO_BIT_13
  935. * @arg @ref LL_PWR_GPIO_BIT_14
  936. * @arg @ref LL_PWR_GPIO_BIT_15
  937. * @retval None
  938. */
  939. __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
  940. {
  941. SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
  942. }
  943. /**
  944. * @brief Disable GPIO pull-up state in Standby and Shutdown modes
  945. * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
  946. * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
  947. * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
  948. * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
  949. * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
  950. * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
  951. * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
  952. * @param GPIO This parameter can be one of the following values:
  953. * @arg @ref LL_PWR_GPIO_A
  954. * @arg @ref LL_PWR_GPIO_B
  955. * @arg @ref LL_PWR_GPIO_C
  956. * @arg @ref LL_PWR_GPIO_D
  957. * @arg @ref LL_PWR_GPIO_E
  958. * @arg @ref LL_PWR_GPIO_F
  959. * @arg @ref LL_PWR_GPIO_G
  960. *
  961. * (*) value not defined in all devices
  962. * @param GPIONumber This parameter can be one of the following values:
  963. * @arg @ref LL_PWR_GPIO_BIT_0
  964. * @arg @ref LL_PWR_GPIO_BIT_1
  965. * @arg @ref LL_PWR_GPIO_BIT_2
  966. * @arg @ref LL_PWR_GPIO_BIT_3
  967. * @arg @ref LL_PWR_GPIO_BIT_4
  968. * @arg @ref LL_PWR_GPIO_BIT_5
  969. * @arg @ref LL_PWR_GPIO_BIT_6
  970. * @arg @ref LL_PWR_GPIO_BIT_7
  971. * @arg @ref LL_PWR_GPIO_BIT_8
  972. * @arg @ref LL_PWR_GPIO_BIT_9
  973. * @arg @ref LL_PWR_GPIO_BIT_10
  974. * @arg @ref LL_PWR_GPIO_BIT_11
  975. * @arg @ref LL_PWR_GPIO_BIT_12
  976. * @arg @ref LL_PWR_GPIO_BIT_13
  977. * @arg @ref LL_PWR_GPIO_BIT_14
  978. * @arg @ref LL_PWR_GPIO_BIT_15
  979. * @retval None
  980. */
  981. __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
  982. {
  983. CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
  984. }
  985. /**
  986. * @brief Check if GPIO pull-up state is enabled
  987. * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  988. * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  989. * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  990. * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  991. * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  992. * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  993. * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
  994. * @param GPIO This parameter can be one of the following values:
  995. * @arg @ref LL_PWR_GPIO_A
  996. * @arg @ref LL_PWR_GPIO_B
  997. * @arg @ref LL_PWR_GPIO_C
  998. * @arg @ref LL_PWR_GPIO_D
  999. * @arg @ref LL_PWR_GPIO_E
  1000. * @arg @ref LL_PWR_GPIO_F
  1001. * @arg @ref LL_PWR_GPIO_G
  1002. *
  1003. * (*) value not defined in all devices
  1004. * @param GPIONumber This parameter can be one of the following values:
  1005. * @arg @ref LL_PWR_GPIO_BIT_0
  1006. * @arg @ref LL_PWR_GPIO_BIT_1
  1007. * @arg @ref LL_PWR_GPIO_BIT_2
  1008. * @arg @ref LL_PWR_GPIO_BIT_3
  1009. * @arg @ref LL_PWR_GPIO_BIT_4
  1010. * @arg @ref LL_PWR_GPIO_BIT_5
  1011. * @arg @ref LL_PWR_GPIO_BIT_6
  1012. * @arg @ref LL_PWR_GPIO_BIT_7
  1013. * @arg @ref LL_PWR_GPIO_BIT_8
  1014. * @arg @ref LL_PWR_GPIO_BIT_9
  1015. * @arg @ref LL_PWR_GPIO_BIT_10
  1016. * @arg @ref LL_PWR_GPIO_BIT_11
  1017. * @arg @ref LL_PWR_GPIO_BIT_12
  1018. * @arg @ref LL_PWR_GPIO_BIT_13
  1019. * @arg @ref LL_PWR_GPIO_BIT_14
  1020. * @arg @ref LL_PWR_GPIO_BIT_15
  1021. * @retval State of bit (1 or 0).
  1022. */
  1023. __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
  1024. {
  1025. return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
  1026. }
  1027. /**
  1028. * @brief Enable GPIO pull-down state in Standby and Shutdown modes
  1029. * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
  1030. * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
  1031. * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
  1032. * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
  1033. * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
  1034. * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
  1035. * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
  1036. * @param GPIO This parameter can be one of the following values:
  1037. * @arg @ref LL_PWR_GPIO_A
  1038. * @arg @ref LL_PWR_GPIO_B
  1039. * @arg @ref LL_PWR_GPIO_C
  1040. * @arg @ref LL_PWR_GPIO_D
  1041. * @arg @ref LL_PWR_GPIO_E
  1042. * @arg @ref LL_PWR_GPIO_F
  1043. * @arg @ref LL_PWR_GPIO_G
  1044. *
  1045. * (*) value not defined in all devices
  1046. * @param GPIONumber This parameter can be one of the following values:
  1047. * @arg @ref LL_PWR_GPIO_BIT_0
  1048. * @arg @ref LL_PWR_GPIO_BIT_1
  1049. * @arg @ref LL_PWR_GPIO_BIT_2
  1050. * @arg @ref LL_PWR_GPIO_BIT_3
  1051. * @arg @ref LL_PWR_GPIO_BIT_4
  1052. * @arg @ref LL_PWR_GPIO_BIT_5
  1053. * @arg @ref LL_PWR_GPIO_BIT_6
  1054. * @arg @ref LL_PWR_GPIO_BIT_7
  1055. * @arg @ref LL_PWR_GPIO_BIT_8
  1056. * @arg @ref LL_PWR_GPIO_BIT_9
  1057. * @arg @ref LL_PWR_GPIO_BIT_10
  1058. * @arg @ref LL_PWR_GPIO_BIT_11
  1059. * @arg @ref LL_PWR_GPIO_BIT_12
  1060. * @arg @ref LL_PWR_GPIO_BIT_13
  1061. * @arg @ref LL_PWR_GPIO_BIT_14
  1062. * @arg @ref LL_PWR_GPIO_BIT_15
  1063. * @retval None
  1064. */
  1065. __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
  1066. {
  1067. SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
  1068. }
  1069. /**
  1070. * @brief Disable GPIO pull-down state in Standby and Shutdown modes
  1071. * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
  1072. * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
  1073. * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
  1074. * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
  1075. * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
  1076. * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
  1077. * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
  1078. * @param GPIO This parameter can be one of the following values:
  1079. * @arg @ref LL_PWR_GPIO_A
  1080. * @arg @ref LL_PWR_GPIO_B
  1081. * @arg @ref LL_PWR_GPIO_C
  1082. * @arg @ref LL_PWR_GPIO_D
  1083. * @arg @ref LL_PWR_GPIO_E
  1084. * @arg @ref LL_PWR_GPIO_F
  1085. * @arg @ref LL_PWR_GPIO_G
  1086. *
  1087. * (*) value not defined in all devices
  1088. * @param GPIONumber This parameter can be one of the following values:
  1089. * @arg @ref LL_PWR_GPIO_BIT_0
  1090. * @arg @ref LL_PWR_GPIO_BIT_1
  1091. * @arg @ref LL_PWR_GPIO_BIT_2
  1092. * @arg @ref LL_PWR_GPIO_BIT_3
  1093. * @arg @ref LL_PWR_GPIO_BIT_4
  1094. * @arg @ref LL_PWR_GPIO_BIT_5
  1095. * @arg @ref LL_PWR_GPIO_BIT_6
  1096. * @arg @ref LL_PWR_GPIO_BIT_7
  1097. * @arg @ref LL_PWR_GPIO_BIT_8
  1098. * @arg @ref LL_PWR_GPIO_BIT_9
  1099. * @arg @ref LL_PWR_GPIO_BIT_10
  1100. * @arg @ref LL_PWR_GPIO_BIT_11
  1101. * @arg @ref LL_PWR_GPIO_BIT_12
  1102. * @arg @ref LL_PWR_GPIO_BIT_13
  1103. * @arg @ref LL_PWR_GPIO_BIT_14
  1104. * @arg @ref LL_PWR_GPIO_BIT_15
  1105. * @retval None
  1106. */
  1107. __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
  1108. {
  1109. CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
  1110. }
  1111. /**
  1112. * @brief Check if GPIO pull-down state is enabled
  1113. * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1114. * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1115. * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1116. * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1117. * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1118. * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1119. * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
  1120. * @param GPIO This parameter can be one of the following values:
  1121. * @arg @ref LL_PWR_GPIO_A
  1122. * @arg @ref LL_PWR_GPIO_B
  1123. * @arg @ref LL_PWR_GPIO_C
  1124. * @arg @ref LL_PWR_GPIO_D
  1125. * @arg @ref LL_PWR_GPIO_E
  1126. * @arg @ref LL_PWR_GPIO_F
  1127. * @arg @ref LL_PWR_GPIO_G
  1128. *
  1129. * (*) value not defined in all devices
  1130. * @param GPIONumber This parameter can be one of the following values:
  1131. * @arg @ref LL_PWR_GPIO_BIT_0
  1132. * @arg @ref LL_PWR_GPIO_BIT_1
  1133. * @arg @ref LL_PWR_GPIO_BIT_2
  1134. * @arg @ref LL_PWR_GPIO_BIT_3
  1135. * @arg @ref LL_PWR_GPIO_BIT_4
  1136. * @arg @ref LL_PWR_GPIO_BIT_5
  1137. * @arg @ref LL_PWR_GPIO_BIT_6
  1138. * @arg @ref LL_PWR_GPIO_BIT_7
  1139. * @arg @ref LL_PWR_GPIO_BIT_8
  1140. * @arg @ref LL_PWR_GPIO_BIT_9
  1141. * @arg @ref LL_PWR_GPIO_BIT_10
  1142. * @arg @ref LL_PWR_GPIO_BIT_11
  1143. * @arg @ref LL_PWR_GPIO_BIT_12
  1144. * @arg @ref LL_PWR_GPIO_BIT_13
  1145. * @arg @ref LL_PWR_GPIO_BIT_14
  1146. * @arg @ref LL_PWR_GPIO_BIT_15
  1147. * @retval State of bit (1 or 0).
  1148. */
  1149. __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
  1150. {
  1151. return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
  1152. }
  1153. /**
  1154. * @}
  1155. */
  1156. /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
  1157. * @{
  1158. */
  1159. /**
  1160. * @brief Get Internal Wake-up line Flag
  1161. * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
  1162. * @retval State of bit (1 or 0).
  1163. */
  1164. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
  1165. {
  1166. uint32_t temp;
  1167. temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
  1168. return ((temp == (PWR_SR1_WUFI))?1U:0U);
  1169. }
  1170. /**
  1171. * @brief Get Stand-By Flag
  1172. * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
  1173. * @retval State of bit (1 or 0).
  1174. */
  1175. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
  1176. {
  1177. uint32_t temp;
  1178. temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
  1179. return ((temp == (PWR_SR1_SBF))?1U:0U);
  1180. }
  1181. /**
  1182. * @brief Get Wake-up Flag 5
  1183. * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
  1184. * @retval State of bit (1 or 0).
  1185. */
  1186. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
  1187. {
  1188. uint32_t temp;
  1189. temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
  1190. return ((temp == (PWR_SR1_WUF5))?1U:0U);
  1191. }
  1192. /**
  1193. * @brief Get Wake-up Flag 4
  1194. * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
  1195. * @retval State of bit (1 or 0).
  1196. */
  1197. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
  1198. {
  1199. uint32_t temp;
  1200. temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
  1201. return ((temp == (PWR_SR1_WUF4))?1U:0U);
  1202. }
  1203. /**
  1204. * @brief Get Wake-up Flag 3
  1205. * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
  1206. * @retval State of bit (1 or 0).
  1207. */
  1208. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
  1209. {
  1210. uint32_t temp;
  1211. temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
  1212. return ((temp == (PWR_SR1_WUF3))?1U:0U);
  1213. }
  1214. /**
  1215. * @brief Get Wake-up Flag 2
  1216. * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
  1217. * @retval State of bit (1 or 0).
  1218. */
  1219. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
  1220. {
  1221. uint32_t temp;
  1222. temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
  1223. return ((temp == (PWR_SR1_WUF2))?1U:0U);
  1224. }
  1225. /**
  1226. * @brief Get Wake-up Flag 1
  1227. * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
  1228. * @retval State of bit (1 or 0).
  1229. */
  1230. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
  1231. {
  1232. uint32_t temp;
  1233. temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
  1234. return ((temp == (PWR_SR1_WUF1))?1U:0U);
  1235. }
  1236. /**
  1237. * @brief Clear Stand-By Flag
  1238. * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
  1239. * @retval None
  1240. */
  1241. __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
  1242. {
  1243. WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
  1244. }
  1245. /**
  1246. * @brief Clear Wake-up Flags
  1247. * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
  1248. * @retval None
  1249. */
  1250. __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
  1251. {
  1252. WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
  1253. }
  1254. /**
  1255. * @brief Clear Wake-up Flag 5
  1256. * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
  1257. * @retval None
  1258. */
  1259. __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
  1260. {
  1261. WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
  1262. }
  1263. /**
  1264. * @brief Clear Wake-up Flag 4
  1265. * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
  1266. * @retval None
  1267. */
  1268. __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
  1269. {
  1270. WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
  1271. }
  1272. /**
  1273. * @brief Clear Wake-up Flag 3
  1274. * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
  1275. * @retval None
  1276. */
  1277. __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
  1278. {
  1279. WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
  1280. }
  1281. /**
  1282. * @brief Clear Wake-up Flag 2
  1283. * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
  1284. * @retval None
  1285. */
  1286. __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
  1287. {
  1288. WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
  1289. }
  1290. /**
  1291. * @brief Clear Wake-up Flag 1
  1292. * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
  1293. * @retval None
  1294. */
  1295. __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
  1296. {
  1297. WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
  1298. }
  1299. /**
  1300. * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
  1301. * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
  1302. * @retval State of bit (1 or 0).
  1303. */
  1304. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
  1305. {
  1306. uint32_t temp;
  1307. temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
  1308. return ((temp == (PWR_SR2_PVMO4))?1U:0U);
  1309. }
  1310. /**
  1311. * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
  1312. * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
  1313. * @retval State of bit (1 or 0).
  1314. */
  1315. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
  1316. {
  1317. uint32_t temp;
  1318. temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
  1319. return ((temp == (PWR_SR2_PVMO3))?1U:0U);
  1320. }
  1321. #if defined(PWR_SR2_PVMO2)
  1322. /**
  1323. * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
  1324. * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
  1325. * @retval State of bit (1 or 0).
  1326. */
  1327. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
  1328. {
  1329. uint32_t temp;
  1330. temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
  1331. return ((temp == (PWR_SR2_PVMO2))?1U:0U);
  1332. }
  1333. #endif /* PWR_SR2_PVMO2 */
  1334. #if defined(PWR_SR2_PVMO1)
  1335. /**
  1336. * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
  1337. * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
  1338. * @retval State of bit (1 or 0).
  1339. */
  1340. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
  1341. {
  1342. uint32_t temp;
  1343. temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
  1344. return ((temp == (PWR_SR2_PVMO1))?1U:0U);
  1345. }
  1346. #endif /* PWR_SR2_PVMO1 */
  1347. /**
  1348. * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
  1349. * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
  1350. * @retval State of bit (1 or 0).
  1351. */
  1352. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
  1353. {
  1354. uint32_t temp;
  1355. temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
  1356. return ((temp == (PWR_SR2_PVDO))?1U:0U);
  1357. }
  1358. /**
  1359. * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
  1360. * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
  1361. * @retval State of bit (1 or 0).
  1362. */
  1363. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
  1364. {
  1365. uint32_t temp;
  1366. temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
  1367. return ((temp == (PWR_SR2_VOSF))?1U:0U);
  1368. }
  1369. /**
  1370. * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
  1371. * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
  1372. * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
  1373. * @retval State of bit (1 or 0).
  1374. */
  1375. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
  1376. {
  1377. uint32_t temp;
  1378. temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
  1379. return ((temp == (PWR_SR2_REGLPF))?1U:0U);
  1380. }
  1381. /**
  1382. * @brief Indicate whether or not the low-power regulator is ready
  1383. * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
  1384. * @retval State of bit (1 or 0).
  1385. */
  1386. __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
  1387. {
  1388. uint32_t temp;
  1389. temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
  1390. return ((temp == (PWR_SR2_REGLPS))?1U:0U);
  1391. }
  1392. /**
  1393. * @}
  1394. */
  1395. #if defined(USE_FULL_LL_DRIVER)
  1396. /** @defgroup PWR_LL_EF_Init De-initialization function
  1397. * @{
  1398. */
  1399. ErrorStatus LL_PWR_DeInit(void);
  1400. /**
  1401. * @}
  1402. */
  1403. #endif /* USE_FULL_LL_DRIVER */
  1404. /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
  1405. * @{
  1406. */
  1407. /* Old functions name kept for legacy purpose, to be replaced by the */
  1408. /* current functions name. */
  1409. #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
  1410. #define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
  1411. #define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
  1412. #define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
  1413. #define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
  1414. #define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
  1415. #define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
  1416. #define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
  1417. #define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
  1418. #define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
  1419. #define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode
  1420. /**
  1421. * @}
  1422. */
  1423. /**
  1424. * @}
  1425. */
  1426. /**
  1427. * @}
  1428. */
  1429. #endif /* defined(PWR) */
  1430. /**
  1431. * @}
  1432. */
  1433. #ifdef __cplusplus
  1434. }
  1435. #endif
  1436. #endif /* STM32G4xx_LL_PWR_H */