stm32l0xx_hal_dma.h 29 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l0xx_hal_dma.h
  4. * @author MCD Application Team
  5. * @brief Header file of DMA HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32L0xx_HAL_DMA_H
  20. #define STM32L0xx_HAL_DMA_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32l0xx_hal_def.h"
  26. /** @addtogroup STM32L0xx_HAL_Driver
  27. * @{
  28. */
  29. /** @addtogroup DMA
  30. * @{
  31. */
  32. /* Exported types ------------------------------------------------------------*/
  33. /** @defgroup DMA_Exported_Types DMA Exported Types
  34. * @{
  35. */
  36. /**
  37. * @brief DMA Configuration Structure definition
  38. */
  39. typedef struct
  40. {
  41. uint32_t Request; /*!< Specifies the request selected for the specified channel.
  42. This parameter can be a value of @ref DMA_request */
  43. uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
  44. from memory to memory or from peripheral to memory.
  45. This parameter can be a value of @ref DMA_Data_transfer_direction */
  46. uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
  47. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  48. uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
  49. This parameter can be a value of @ref DMA_Memory_incremented_mode */
  50. uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
  51. This parameter can be a value of @ref DMA_Peripheral_data_size */
  52. uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
  53. This parameter can be a value of @ref DMA_Memory_data_size */
  54. uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
  55. This parameter can be a value of @ref DMA_mode
  56. @note The circular buffer mode cannot be used if the memory-to-memory
  57. data transfer is configured on the selected Channel */
  58. uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
  59. This parameter can be a value of @ref DMA_Priority_level */
  60. } DMA_InitTypeDef;
  61. /**
  62. * @brief HAL DMA State structures definition
  63. */
  64. typedef enum
  65. {
  66. HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
  67. HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
  68. HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
  69. HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
  70. }HAL_DMA_StateTypeDef;
  71. /**
  72. * @brief HAL DMA Error Code structure definition
  73. */
  74. typedef enum
  75. {
  76. HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
  77. HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
  78. }HAL_DMA_LevelCompleteTypeDef;
  79. /**
  80. * @brief HAL DMA Callback ID structure definition
  81. */
  82. typedef enum
  83. {
  84. HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
  85. HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
  86. HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
  87. HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
  88. HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
  89. }HAL_DMA_CallbackIDTypeDef;
  90. /**
  91. * @brief DMA handle Structure definition
  92. */
  93. typedef struct __DMA_HandleTypeDef
  94. {
  95. DMA_Channel_TypeDef *Instance; /*!< Register base address */
  96. DMA_InitTypeDef Init; /*!< DMA communication parameters */
  97. HAL_LockTypeDef Lock; /*!< DMA locking object */
  98. __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
  99. void *Parent; /*!< Parent object state */
  100. void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
  101. void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
  102. void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
  103. void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
  104. __IO uint32_t ErrorCode; /*!< DMA Error code */
  105. DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
  106. uint32_t ChannelIndex; /*!< DMA Channel Index */
  107. }DMA_HandleTypeDef;
  108. /**
  109. * @}
  110. */
  111. /* Exported constants --------------------------------------------------------*/
  112. /** @defgroup DMA_Exported_Constants DMA Exported Constants
  113. * @{
  114. */
  115. /** @defgroup DMA_Error_Code DMA Error Code
  116. * @{
  117. */
  118. #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
  119. #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
  120. #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
  121. #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
  122. #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
  123. /**
  124. * @}
  125. */
  126. /** @defgroup DMA_request DMA request
  127. * @{
  128. */
  129. #if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xC)
  130. #define DMA_REQUEST_0 0U
  131. #define DMA_REQUEST_1 1U
  132. #define DMA_REQUEST_4 4U
  133. #define DMA_REQUEST_5 5U
  134. #define DMA_REQUEST_6 6U
  135. #define DMA_REQUEST_8 8U
  136. #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
  137. ((REQUEST) == DMA_REQUEST_1) || \
  138. ((REQUEST) == DMA_REQUEST_4) || \
  139. ((REQUEST) == DMA_REQUEST_5) || \
  140. ((REQUEST) == DMA_REQUEST_6) || \
  141. ((REQUEST) == DMA_REQUEST_8))
  142. /* STM32L010x4 || STM32L010x6 || STM32L010x8 || STM32L010xC */
  143. #elif defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
  144. #define DMA_REQUEST_0 0U
  145. #define DMA_REQUEST_1 1U
  146. #define DMA_REQUEST_2 2U
  147. #define DMA_REQUEST_3 3U
  148. #define DMA_REQUEST_4 4U
  149. #define DMA_REQUEST_5 5U
  150. #define DMA_REQUEST_6 6U
  151. #define DMA_REQUEST_7 7U
  152. #define DMA_REQUEST_8 8U
  153. #define DMA_REQUEST_9 9U
  154. #define DMA_REQUEST_10 10U
  155. #define DMA_REQUEST_11 11U /* AES product only */
  156. #define DMA_REQUEST_12 12U
  157. #define DMA_REQUEST_13 13U
  158. #define DMA_REQUEST_14 14U
  159. #define DMA_REQUEST_15 15U
  160. #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
  161. ((REQUEST) == DMA_REQUEST_1) || \
  162. ((REQUEST) == DMA_REQUEST_2) || \
  163. ((REQUEST) == DMA_REQUEST_3) || \
  164. ((REQUEST) == DMA_REQUEST_4) || \
  165. ((REQUEST) == DMA_REQUEST_5) || \
  166. ((REQUEST) == DMA_REQUEST_6) || \
  167. ((REQUEST) == DMA_REQUEST_7) || \
  168. ((REQUEST) == DMA_REQUEST_8) || \
  169. ((REQUEST) == DMA_REQUEST_9) || \
  170. ((REQUEST) == DMA_REQUEST_10) || \
  171. ((REQUEST) == DMA_REQUEST_11) || \
  172. ((REQUEST) == DMA_REQUEST_12) || \
  173. ((REQUEST) == DMA_REQUEST_13) || \
  174. ((REQUEST) == DMA_REQUEST_14) || \
  175. ((REQUEST) == DMA_REQUEST_15))
  176. /* (STM32L021xx) || (STM32L041xx) || (STM32L062xx) || (STM32L063xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
  177. #else
  178. #define DMA_REQUEST_0 0U
  179. #define DMA_REQUEST_1 1U
  180. #define DMA_REQUEST_2 2U
  181. #define DMA_REQUEST_3 3U
  182. #define DMA_REQUEST_4 4U
  183. #define DMA_REQUEST_5 5U
  184. #define DMA_REQUEST_6 6U
  185. #define DMA_REQUEST_7 7U
  186. #define DMA_REQUEST_8 8U
  187. #define DMA_REQUEST_9 9U
  188. #define DMA_REQUEST_10 10U
  189. #define DMA_REQUEST_12 12U
  190. #define DMA_REQUEST_13 13U
  191. #define DMA_REQUEST_14 14U
  192. #define DMA_REQUEST_15 15U
  193. #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
  194. ((REQUEST) == DMA_REQUEST_1) || \
  195. ((REQUEST) == DMA_REQUEST_2) || \
  196. ((REQUEST) == DMA_REQUEST_3) || \
  197. ((REQUEST) == DMA_REQUEST_4) || \
  198. ((REQUEST) == DMA_REQUEST_5) || \
  199. ((REQUEST) == DMA_REQUEST_6) || \
  200. ((REQUEST) == DMA_REQUEST_7) || \
  201. ((REQUEST) == DMA_REQUEST_8) || \
  202. ((REQUEST) == DMA_REQUEST_9) || \
  203. ((REQUEST) == DMA_REQUEST_10) || \
  204. ((REQUEST) == DMA_REQUEST_12) || \
  205. ((REQUEST) == DMA_REQUEST_13) || \
  206. ((REQUEST) == DMA_REQUEST_14) || \
  207. ((REQUEST) == DMA_REQUEST_15))
  208. #endif /* (STM32L031xx) || (STM32L051xx) || (STM32L052xx) || (STM32L053xx) || (STM32L071xx) || (STM32L072xx) || (STM32L073xx) */
  209. /**
  210. * @}
  211. */
  212. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
  213. * @{
  214. */
  215. #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
  216. #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
  217. #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
  218. /**
  219. * @}
  220. */
  221. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
  222. * @{
  223. */
  224. #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
  225. #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
  226. /**
  227. * @}
  228. */
  229. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
  230. * @{
  231. */
  232. #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
  233. #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
  234. /**
  235. * @}
  236. */
  237. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
  238. * @{
  239. */
  240. #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
  241. #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
  242. #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
  243. /**
  244. * @}
  245. */
  246. /** @defgroup DMA_Memory_data_size DMA Memory data size
  247. * @{
  248. */
  249. #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
  250. #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
  251. #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
  252. /**
  253. * @}
  254. */
  255. /** @defgroup DMA_mode DMA mode
  256. * @{
  257. */
  258. #define DMA_NORMAL 0x00000000U /*!< Normal mode */
  259. #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
  260. /**
  261. * @}
  262. */
  263. /** @defgroup DMA_Priority_level DMA Priority level
  264. * @{
  265. */
  266. #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
  267. #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
  268. #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
  269. #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
  270. /**
  271. * @}
  272. */
  273. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
  274. * @{
  275. */
  276. #define DMA_IT_TC DMA_CCR_TCIE
  277. #define DMA_IT_HT DMA_CCR_HTIE
  278. #define DMA_IT_TE DMA_CCR_TEIE
  279. /**
  280. * @}
  281. */
  282. /** @defgroup DMA_flag_definitions DMA flag definitions
  283. * @{
  284. */
  285. #define DMA_FLAG_GL1 DMA_ISR_GIF1
  286. #define DMA_FLAG_TC1 DMA_ISR_TCIF1
  287. #define DMA_FLAG_HT1 DMA_ISR_HTIF1
  288. #define DMA_FLAG_TE1 DMA_ISR_TEIF1
  289. #define DMA_FLAG_GL2 DMA_ISR_GIF2
  290. #define DMA_FLAG_TC2 DMA_ISR_TCIF2
  291. #define DMA_FLAG_HT2 DMA_ISR_HTIF2
  292. #define DMA_FLAG_TE2 DMA_ISR_TEIF2
  293. #define DMA_FLAG_GL3 DMA_ISR_GIF3
  294. #define DMA_FLAG_TC3 DMA_ISR_TCIF3
  295. #define DMA_FLAG_HT3 DMA_ISR_HTIF3
  296. #define DMA_FLAG_TE3 DMA_ISR_TEIF3
  297. #define DMA_FLAG_GL4 DMA_ISR_GIF4
  298. #define DMA_FLAG_TC4 DMA_ISR_TCIF4
  299. #define DMA_FLAG_HT4 DMA_ISR_HTIF4
  300. #define DMA_FLAG_TE4 DMA_ISR_TEIF4
  301. #define DMA_FLAG_GL5 DMA_ISR_GIF5
  302. #define DMA_FLAG_TC5 DMA_ISR_TCIF5
  303. #define DMA_FLAG_HT5 DMA_ISR_HTIF5
  304. #define DMA_FLAG_TE5 DMA_ISR_TEIF5
  305. #define DMA_FLAG_GL6 DMA_ISR_GIF6
  306. #define DMA_FLAG_TC6 DMA_ISR_TCIF6
  307. #define DMA_FLAG_HT6 DMA_ISR_HTIF6
  308. #define DMA_FLAG_TE6 DMA_ISR_TEIF6
  309. #define DMA_FLAG_GL7 DMA_ISR_GIF7
  310. #define DMA_FLAG_TC7 DMA_ISR_TCIF7
  311. #define DMA_FLAG_HT7 DMA_ISR_HTIF7
  312. #define DMA_FLAG_TE7 DMA_ISR_TEIF7
  313. /**
  314. * @}
  315. */
  316. /**
  317. * @}
  318. */
  319. /* Exported macros -----------------------------------------------------------*/
  320. /** @defgroup DMA_Exported_Macros DMA Exported Macros
  321. * @{
  322. */
  323. /** @brief Reset DMA handle state
  324. * @param __HANDLE__ DMA handle
  325. * @retval None
  326. */
  327. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  328. /**
  329. * @brief Enable the specified DMA Channel.
  330. * @param __HANDLE__ DMA handle
  331. * @retval None
  332. */
  333. #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
  334. /**
  335. * @brief Disable the specified DMA Channel.
  336. * @param __HANDLE__ DMA handle
  337. * @retval None
  338. */
  339. #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
  340. /* Interrupt & Flag management */
  341. /**
  342. * @brief Return the current DMA Channel transfer complete flag.
  343. * @param __HANDLE__: DMA handle
  344. * @retval The specified transfer complete flag index.
  345. */
  346. #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
  347. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  348. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  349. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  350. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  351. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  352. DMA_FLAG_TC5)
  353. #else
  354. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  355. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
  356. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
  357. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
  358. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
  359. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
  360. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
  361. DMA_FLAG_TC7)
  362. #endif
  363. /**
  364. * @brief Return the current DMA Channel half transfer complete flag.
  365. * @param __HANDLE__ DMA handle
  366. * @retval The specified half transfer complete flag index.
  367. */
  368. #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
  369. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  370. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  371. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  372. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  373. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  374. DMA_FLAG_HT5)
  375. #else
  376. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  377. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  378. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
  379. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
  380. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
  381. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
  382. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
  383. DMA_FLAG_HT7)
  384. #endif
  385. /**
  386. * @brief Returns the current DMA Channel transfer error flag.
  387. * @param __HANDLE__ DMA handle
  388. * @retval The specified transfer error flag index.
  389. */
  390. #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
  391. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  392. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  393. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  394. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  395. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  396. DMA_FLAG_TE5)
  397. #else
  398. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  399. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
  400. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
  401. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
  402. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
  403. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
  404. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
  405. DMA_FLAG_TE7)
  406. #endif
  407. /**
  408. * @brief Returns the current DMA Channel Global interrupt flag.
  409. * @param __HANDLE__ DMA handle
  410. * @retval The specified transfer error flag index.
  411. */
  412. #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
  413. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  414. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  415. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  416. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  417. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  418. DMA_ISR_GIF5)
  419. #else
  420. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
  421. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
  422. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
  423. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
  424. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
  425. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
  426. ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
  427. DMA_ISR_GIF7)
  428. #endif
  429. /**
  430. * @brief Get the DMA Channel pending flags.
  431. * @param __HANDLE__ DMA handle
  432. * @param __FLAG__ Get the specified flag.
  433. * This parameter can be any combination of the following values:
  434. * @arg DMA_FLAG_TCIFx: Transfer complete flag
  435. * @arg DMA_FLAG_HTIFx: Half transfer complete flag
  436. * @arg DMA_FLAG_TEIFx: Transfer error flag
  437. * @arg DMA_ISR_GIFx: Global interrupt flag
  438. * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
  439. * @retval The state of FLAG (SET or RESET).
  440. */
  441. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
  442. /**
  443. * @brief Clears the DMA Channel pending flags.
  444. * @param __HANDLE__ DMA handle
  445. * @param __FLAG__ specifies the flag to clear.
  446. * This parameter can be any combination of the following values:
  447. * @arg DMA_FLAG_TCx: Transfer complete flag
  448. * @arg DMA_FLAG_HTx: Half transfer complete flag
  449. * @arg DMA_FLAG_TEx: Transfer error flag
  450. * @arg DMA_FLAG_GLx: Global interrupt flag
  451. * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
  452. * @retval None
  453. */
  454. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
  455. /**
  456. * @brief Enable the specified DMA Channel interrupts.
  457. * @param __HANDLE__ DMA handle
  458. * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
  459. * This parameter can be any combination of the following values:
  460. * @arg DMA_IT_TC: Transfer complete interrupt mask
  461. * @arg DMA_IT_HT: Half transfer complete interrupt mask
  462. * @arg DMA_IT_TE: Transfer error interrupt mask
  463. * @retval None
  464. */
  465. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
  466. /**
  467. * @brief Disable the specified DMA Channel interrupts.
  468. * @param __HANDLE__ DMA handle
  469. * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
  470. * This parameter can be any combination of the following values:
  471. * @arg DMA_IT_TC: Transfer complete interrupt mask
  472. * @arg DMA_IT_HT: Half transfer complete interrupt mask
  473. * @arg DMA_IT_TE: Transfer error interrupt mask
  474. * @retval None
  475. */
  476. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
  477. /**
  478. * @brief Check whether the specified DMA Channel interrupt is enabled or not.
  479. * @param __HANDLE__ DMA handle
  480. * @param __INTERRUPT__ specifies the DMA interrupt source to check.
  481. * This parameter can be one of the following values:
  482. * @arg DMA_IT_TC: Transfer complete interrupt mask
  483. * @arg DMA_IT_HT: Half transfer complete interrupt mask
  484. * @arg DMA_IT_TE: Transfer error interrupt mask
  485. * @retval The state of DMA_IT (SET or RESET).
  486. */
  487. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
  488. /**
  489. * @brief Return the number of remaining data units in the current DMA Channel transfer.
  490. * @param __HANDLE__ DMA handle
  491. * @retval The number of remaining data units in the current DMA Channel transfer.
  492. */
  493. #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
  494. /**
  495. * @}
  496. */
  497. /* Exported functions --------------------------------------------------------*/
  498. /** @addtogroup DMA_Exported_Functions
  499. * @{
  500. */
  501. /** @addtogroup DMA_Exported_Functions_Group1
  502. * @{
  503. */
  504. /* Initialization and de-initialization functions *****************************/
  505. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
  506. HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
  507. /**
  508. * @}
  509. */
  510. /** @addtogroup DMA_Exported_Functions_Group2
  511. * @{
  512. */
  513. /* IO operation functions *****************************************************/
  514. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  515. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  516. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  517. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
  518. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
  519. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  520. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
  521. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
  522. /**
  523. * @}
  524. */
  525. /** @addtogroup DMA_Exported_Functions_Group3
  526. * @{
  527. */
  528. /* Peripheral State and Error functions ***************************************/
  529. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  530. uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  531. /**
  532. * @}
  533. */
  534. /**
  535. * @}
  536. */
  537. /* Define the private group ***********************************/
  538. /**************************************************************/
  539. /** @defgroup DMA_Private DMA Private
  540. * @{
  541. */
  542. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
  543. ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
  544. ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
  545. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
  546. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
  547. ((STATE) == DMA_PINC_DISABLE))
  548. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
  549. ((STATE) == DMA_MINC_DISABLE))
  550. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
  551. ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
  552. ((SIZE) == DMA_PDATAALIGN_WORD))
  553. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
  554. ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
  555. ((SIZE) == DMA_MDATAALIGN_WORD ))
  556. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
  557. ((MODE) == DMA_CIRCULAR))
  558. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
  559. ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
  560. ((PRIORITY) == DMA_PRIORITY_HIGH) || \
  561. ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
  562. /**
  563. * @}
  564. */
  565. /**************************************************************/
  566. /**
  567. * @}
  568. */
  569. /**
  570. * @}
  571. */
  572. #ifdef __cplusplus
  573. }
  574. #endif
  575. #endif /* STM32L0xx_HAL_DMA_H */