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@@ -0,0 +1,380 @@
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+#include "stm32l0xx_hal.h"
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+#include "lt8920.h"
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+#include "lt8920_trs.h"
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+#include <stdio.h>
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+
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+
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+void LT8920::dump_register(uint8_t reg)
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+{
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+ uint16_t r = readRegister(reg);
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+ printf("reg: %u, value: %X\r\n", reg, r);
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+}
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+
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+LT8920::LT8920(void)
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+{
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+ _channel = DEFAULT_CHANNEL;
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+
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+ LT8920_CS_HIGH;
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+}
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+
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+void LT8920::begin()
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+{
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+ LT8920_RESET_LOW;
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+ HAL_Delay(200);
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+ LT8920_RESET_HIGH;
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+ HAL_Delay(200);
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+
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+ //setup
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+
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+ writeRegister(0, 0x6fe0);
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+ writeRegister(1, 0x5681);
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+ writeRegister(2, 0x6617);
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+ writeRegister(4, 0x9cc9); //why does this differ from powerup (5447)
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+ writeRegister(5, 0x6637); //why does this differ from powerup (f000)
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+ writeRegister(8, 0x6c90); //power (default 71af) UNDOCUMENTED
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+
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+ setCurrentControl(4, 0); // power & gain.
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+
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+ writeRegister(10, 0x7ffd); //bit 0: XTAL OSC enable
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+ writeRegister(11, 0x0000); //bit 8: Power down RSSI (0= RSSI operates normal)
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+ writeRegister(12, 0x0000);
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+ writeRegister(13, 0x48bd); //(default 4855)
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+
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+ writeRegister(22, 0x00ff);
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+ writeRegister(23, 0x8005); //bit 2: Calibrate VCO before each Rx/Tx enable
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+ writeRegister(24, 0x0067);
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+ writeRegister(25, 0x1659);
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+ writeRegister(26, 0x19e0);
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+ writeRegister(27, 0x1300); //bits 5:0, Crystal Frequency adjust
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+ writeRegister(28, 0x1800);
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+
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+ //fedcba9876543210
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+ writeRegister(32, 0x5000); //AAABBCCCDDEEFFFG A preamble length, B, syncword length, c trailer length, d packet type
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+ // E FEC_type, F BRCLK_SEL, G reserved
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+ //0x5000 = 0101 0000 0000 0000 = preamble 010 (3 bytes), B 10 (48 bits)
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+ writeRegister(33, 0x3fc7);
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+ writeRegister(34, 0x2000); //
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+ writeRegister(35, 0x0300); //POWER mode, bit 8/9 on = retransmit = 3x (default)
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+ setSyncWord(0x03805a5a03800380);
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+
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+ writeRegister(40, 0x4401); //max allowed error bits = 0 (01 = 0 error bits)
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+ writeRegister(R_PACKETCONFIG, PACKETCONFIG_CRC_ON |
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+ PACKETCONFIG_PACK_LEN_ENABLE | PACKETCONFIG_FW_TERM_TX);
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+
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+ writeRegister(42, 0xfdb0);
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+ writeRegister(43, 0x000f);
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+
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+ //setDataRate(LT8920_1MBPS);
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+
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+ writeRegister(R_FIFO, 0x0000); //TXRX_FIFO_REG (FIFO queue)
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+
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+ writeRegister(R_FIFO_CONTROL, 0x8080); //Fifo Rx/Tx queue reset
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+
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+ HAL_Delay(200);
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+ writeRegister(R_CHANNEL, _BV(CHANNEL_TX_BIT)); //set TX mode. (TX = bit 8, RX = bit 7, so RX would be 0x0080)
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+ HAL_Delay(2);
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+ writeRegister(R_CHANNEL, _channel); // Frequency = 2402 + channel
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+}
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+
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+void LT8920::setChannel(uint8_t channel)
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+{
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+ _channel = channel;
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+ writeRegister(R_CHANNEL, (_channel & CHANNEL_MASK));
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+}
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+
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+uint8_t LT8920::getChannel()
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+{
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+ return _channel;
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+}
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+
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+void LT8920::setCurrentControl(uint8_t power, uint8_t gain)
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+{
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+ writeRegister(R_CURRENT,
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+ ((power << CURRENT_POWER_SHIFT) & CURRENT_POWER_MASK) |
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+ ((gain << CURRENT_GAIN_SHIFT) & CURRENT_GAIN_MASK));
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+}
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+
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+bool LT8920::setDataRate(DataRate rate)
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+{
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+ uint16_t newValue;
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+
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+ switch (rate)
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+ {
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+ case LT8920_1MBPS:
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+ newValue = DATARATE_1MBPS;
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+ break;
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+ case LT8920_250KBPS:
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+ newValue = DATARATE_250KBPS;
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+ break;
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+ case LT8920_125KBPS:
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+ newValue = DATARATE_125KBPS;
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+ break;
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+ case LT8920_62KBPS:
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+ newValue = DATARATE_62KBPS;
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+ break;
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+ default:
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+ return false;
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+ }
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+
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+ writeRegister(R_DATARATE, newValue);
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+ return ( (readRegister(R_DATARATE) & DATARATE_MASK) == (newValue & DATARATE_MASK));
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+}
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+
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+LT8920::DataRate LT8920::getDataRate()
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+{
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+ uint16_t value = readRegister(R_DATARATE) & DATARATE_MASK;
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+ switch (value)
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+ {
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+ case DATARATE_1MBPS:
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+ return LT8920_1MBPS;
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+ case DATARATE_250KBPS:
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+ return LT8920_250KBPS;
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+ case DATARATE_125KBPS:
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+ return LT8920_125KBPS;
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+ case DATARATE_62KBPS:
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+ return LT8920_62KBPS;
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+ }
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+}
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+
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+uint16_t LT8920::readRegister(uint8_t reg)
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+{
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+ LT8920_CS_LOW;
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+ SPI.transfer(REGISTER_READ | (REGISTER_MASK & reg));
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+ uint8_t high = SPI.transfer(0x00);
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+ uint8_t low = SPI.transfer(0x00);
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+ LT8920_CS_HIGH;
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+
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+
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+ // Serial.print(reg);
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+ // Serial.print(" = ");
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+ // Serial.println(high << 8 | low);
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+
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+ return (high << 8 | low);
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+}
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+
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+uint8_t LT8920::writeRegister(uint8_t reg, uint16_t data)
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+{
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+ uint8_t high = data >> 8;
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+ uint8_t low = data & 0xFF;
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+
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+ return writeRegister2(reg, high, low);
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+}
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+
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+uint8_t LT8920::writeRegister2(uint8_t reg, uint8_t high, uint8_t low)
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+{
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+
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+ // char sbuf[32];
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+ // sprintf_P(sbuf, PSTR("%d => %02x%02x"), reg, high, low);
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+ // Serial.println(sbuf);
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+
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+
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+ LT8920_CS_LOW;
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+ uint8_t result = SPI.transfer(REGISTER_WRITE | (REGISTER_MASK & reg));
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+ SPI.transfer(high);
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+ SPI.transfer(low);
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+
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+ LT8920_CS_HIGH;
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+ return result;
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+}
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+
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+void LT8920::sleep()
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+{
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+ //set bit 14 on register 35.
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+ writeRegister(35, readRegister(35) | _BV(14));
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+}
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+
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+void LT8920::whatsUp(void)
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+{
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+ uint16_t mode = readRegister(R_CHANNEL);
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+
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+#if 0
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+ print("\nTx_EN=");
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+ println((mode & _BV(CHANNEL_TX_BIT)) != false);
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+ print("Rx_EN=");
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+ println((mode & _BV(CHANNEL_RX_BIT)) != false);
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+ print("Channel=");
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+ println(mode & CHANNEL_MASK);
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+#endif
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+
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+ //read the status register.
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+ uint16_t state = readRegister(R_STATUS);
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+
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+ bool crc_error = state & _BV(15);
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+ bool fec23_error = state & _BV(14);
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+ uint8_t framer_st = (state & 0b0011111100000000) >> 8;
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+ bool pkt_flag = state & _BV(6);
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+ bool fifo_flag = state & _BV(5);
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+
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+#if 0
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+ stream.print("CRC=");
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+ stream.println(crc_error);
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+ stream.print("FEC=");
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+ stream.println(fec23_error);
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+ stream.print("FRAMER_ST=");
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+ stream.println(framer_st);
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+ stream.print("PKT=");
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+ stream.println(pkt_flag);
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+ stream.print("FIFO=");
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+ stream.println(fifo_flag);
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+#endif
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+
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+ uint16_t fifo = readRegister(R_FIFO_CONTROL);
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+#if 0
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+ stream.print("FIFO_WR_PTR=");
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+ stream.println((fifo >> 8) & 0b111111);
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+ stream.print("FIFO_RD_PTR=");
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+ stream.println(fifo & 0b111111);
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+#endif
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+}
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+
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+bool LT8920::available()
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+{
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+ //read the PKT_FLAG state; this can also be done with a hard wire.
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+
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+ if (LT8920_GET_PKT != 0)
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+ {
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+ return true;
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+ }
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+
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+ return false;
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+}
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+
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+int LT8920::read(uint8_t *buffer, size_t maxBuffer)
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+{
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+ uint16_t value = readRegister(R_STATUS);
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+ if (bitRead(value, STATUS_CRC_BIT) == 0)
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+ {
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+ //CRC ok
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+
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+ uint16_t data = readRegister(R_FIFO);
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+ uint8_t packetSize = data >> 8;
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+ if(maxBuffer < packetSize+1)
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+ {
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+ //BUFFER TOO SMALL
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+ return -2;
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+ }
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+
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+ uint8_t pos;
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+ buffer[pos++] = (data & 0xFF);
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+ while (pos < packetSize)
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+ {
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+ data = readRegister(R_FIFO);
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+ buffer[pos++] = data >> 8;
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+ buffer[pos++] = data & 0xFF;
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+ }
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+
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+ return packetSize;
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+ }
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+ else
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+ {
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+ //CRC error
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+ return -1;
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+ }
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+}
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+
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+void LT8920::startListening()
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+{
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+ writeRegister(R_CHANNEL, _channel & CHANNEL_MASK); //turn off rx/tx
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+ HAL_Delay(3);
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+ writeRegister(R_FIFO_CONTROL, 0x0080); //flush rx
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+ writeRegister(R_CHANNEL, (_channel & CHANNEL_MASK) | _BV(CHANNEL_RX_BIT)); //enable RX
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+ HAL_Delay(5);
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+}
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+
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+/* set the BRCLK_SEL value */
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+void LT8920::setClock(uint8_t clock)
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+{
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+ //register 32, bits 3:1.
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+ uint16_t val = readRegister(35);
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+ val &= 0b1111111111110001;
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+ val |= ((clock & 0x07) << 1);;
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+
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+ writeRegister(35, val);
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+}
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+
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+bool LT8920::sendPacket(uint8_t *data, size_t packetSize)
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+{
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+ if (packetSize < 1 || packetSize > 255)
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+ {
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+ return false;
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+ }
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+
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+ writeRegister(R_CHANNEL, 0x0000);
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+ writeRegister(R_FIFO_CONTROL, 0x8000); //flush tx
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+
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+ //packets are sent in 16bit words, and the first word will be the packet size.
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+ //start spitting out words until we are done.
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+
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+ uint8_t pos = 0;
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+ writeRegister2(R_FIFO, packetSize, data[pos++]);
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+ while (pos < packetSize)
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+ {
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+ uint8_t msb = data[pos++];
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+ uint8_t lsb = data[pos++];
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+
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+ writeRegister2(R_FIFO, msb, lsb);
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+ }
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+
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+ writeRegister(R_CHANNEL, (_channel & CHANNEL_MASK) | _BV(CHANNEL_TX_BIT)); //enable TX
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+
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+ //Wait until the packet is sent.
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+ while (LT8920_GET_PKT == 0)
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+ {
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+ //do nothing.
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+ }
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+
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+ return true;
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+}
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+
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+void LT8920::setSyncWord(uint64_t syncWord)
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+{
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+ writeRegister(R_SYNCWORD1, syncWord);
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+ writeRegister(R_SYNCWORD2, syncWord >> 16);
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+ writeRegister(R_SYNCWORD3, syncWord >> 32);
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+ writeRegister(R_SYNCWORD4, syncWord >> 48);
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+}
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+
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+void LT8920::setSyncWordLength(uint8_t option)
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+{
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+ option &= 0x03;
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+ option <<= 11;
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+
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+ writeRegister(32, (readRegister(32) & 0b0001100000000000) | option);
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+}
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+
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+uint8_t LT8920::getRSSI()
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+{
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+ //RSSI: 15:10
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+ uint16_t value = readRegister(6);
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+
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+ return (value >> 10);
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+}
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+
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+void LT8920::scanRSSI(uint16_t *buffer, uint8_t start_channel, uint8_t num_channels)
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+{
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+ // writeRegister(R_CHANNEL, _BV(CHANNEL_RX_BIT));
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+ //
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+ // //add read mode.
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+ writeRegister(R_FIFO_CONTROL, 0x8080); //flush rx
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+ // writeRegister(R_CHANNEL, 0x0000);
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+
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+ //set number of channels to scan.
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+ writeRegister(42, (readRegister(42) & 0b0000001111111111) | ((num_channels-1 & 0b111111) << 10));
|
|
|
|
+
|
|
|
|
+ //set channel scan offset.
|
|
|
|
+ writeRegister(43, (readRegister(43) & 0b0000000011111111) | ((start_channel & 0b1111111) << 8));
|
|
|
|
+ writeRegister(43, (readRegister(43) & 0b0111111111111111) | _BV(15));
|
|
|
|
+
|
|
|
|
+ while (LT8920_GET_PKT == 0)
|
|
|
|
+ {
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+
|
|
|
|
+ //read the results.
|
|
|
|
+ uint8_t pos = 0;
|
|
|
|
+ while(pos < num_channels)
|
|
|
|
+ {
|
|
|
|
+ uint16_t data = readRegister(R_FIFO);
|
|
|
|
+ buffer[pos++] = data >> 8;
|
|
|
|
+ }
|
|
|
|
+}
|